Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 4:
Model-Specific Registers
NOTE: The Intel
®
64 and IA-32 Architectures Software Developer's Manual consists of ten volumes:
Basic Architecture, Order Number 253665; Instruction Set Reference, A-L, Order Number 253666;
Instruction Set Reference, M-U, Order Number 253667; Instruction Set Reference, V, Order Number
326018; Instruction Set Reference, W-Z, Order Number 334569; System Programming Guide, Part 1,
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Programming Guide, Part 3, Order Number 326019; System Programming Guide, Part 4, Order Number
332831; Model-Specific Registers, Order Number 335592. Refer to all ten volumes when evaluating
your design needs.
Order Number: 335592-084US
June 2024
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Vol. 4 iii
CONTENTS
PAGE
CHAPTER 1
ABOUT THIS MANUAL
1.1 OVERVIEW OF THE MODEL-SPECIFIC REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
CHAPTER 2
MODEL-SPECIFIC REGISTERS (MSRS)
2.1 ARCHITECTURAL MSRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 MSRS IN THE INTEL® CORE™
2 PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-65
2.3 MSRS IN THE 45 NM AND 32 NM INTEL ATOM®
PROCESSOR FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
2.4 MSRS IN INTEL PROCESSORS BASED ON SILVERMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
2.4.1 MSRs with Model-Specific Behavior in the Silvermont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-111
2.4.2 MSRs in Intel Atom® Processors Based on Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-114
2.5 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116
2.6 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142
2.7 MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT MICROARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-147
2.8 MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149
2.8.1 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-171
2.8.2 Additional MSRs in the Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-173
2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON WESTMERE MICROARCHITECTURE . . . . . . . . . . . . . . . 2-193
2.10 MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY BASED ON WESTMERE MICROARCHITECTURE. . . . . . . . . . . . . . . . . . 2-194
2.11 MSRS IN THE INTEL® PROCESSOR FAMILY BASED ON SANDY BRIDGE MICROARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . 2-197
2.11.1 MSRs in the 2nd Generation Intel® Core™ Processor Family Based on Sandy Bridge Microarchitecture. . . . . . . . . . . . . .2-219
2.11.2 MSRs in the Intel® Xeon® Processor E5 Family Based on Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . .2-225
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-230
2.12 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED ON IVY BRIDGE MICROARCHITECTURE. . . 2-236
2.12.1 MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E Microarchitecture . . . . . . . . . . . . . . . .2-239
2.12.2 Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-251
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-254
2.13 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON HASWELL MICROARCHITECTURE . . . . . . . . . . . 2-260
2.13.1 MSRs in the 4th Generation Intel® Core™ Processor Family Based on Haswell Microarchitecture . . . . . . . . . . . . . . . . . . .2-265
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-276
2.14 MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-277
2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-290
2.15 MSRS IN THE INTEL® CORE™ M PROCESSORS AND THE 5TH GENERATION INTEL® CORE™ PROCESSORS . . . . . . . . . . . . . . 2-306
2.16 MSRS IN THE INTEL® XEON® PROCESSOR E5 V4 FAMILY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-310
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-320
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-324
2.17 MSRS IN THE 6TH—13TH GENERATION INTEL® CORE™ PROCESSORS, 1ST—5TH GENERATION INTEL® XEON® SCALABLE
PROCESSOR FAMILIES, INTEL® CORE™ ULTRA 7 PROCESSORS, 8TH GENERATION INTEL® CORE™ I3 PROCESSORS, AND
INTEL® XEON® E PROCESSORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-331
2.17.1 MSRs Introduced in 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby Lake
Microarchitecture and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-355
2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-357
2.17.3 MSRs Introduced in 10th Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-363
2.17.4 MSRs Introduced in the 11th Generation Intel® Core™ Processors based on Tiger Lake Microarchitecture . . . . . . . . . .2-367
2.17.5 MSRs Introduced in the 12th and 13th Generation Intel® Core™ Processors Supporting Performance Hybrid
Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-370
2.17.6 MSRs Introduced in the Intel® Xeon® Scalable Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-380
2.17.7 MSRs Specific to the 3rd Generation Intel® Xeon® Scalable Processor Family Based on Ice Lake Microarchitecture . .2-397
2.17.8 MSRs Specific to the 4th and 5th Generation Intel® Xeon® Scalable Processor Families. . . . . . . . . . . . . . . . . . . . . . . . . . . .2-399
2.17.9 MSRs Introduced in the Intel® Core™ Ultra 7 Processor Supporting Performance Hybrid Architecture . . . . . . . . . . . . . .2-410
2.18 MSRS IN THE INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES AND THE INTEL® XEON PHI™ PROCESSOR
7215/7285/7295 SERIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-433
2.19 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-454
2.19.1 MSRs Unique to Intel® Xeon® Processor MP with L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-480
2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™
DUO PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-481
2.21 MSRS IN THE PENTIUM M PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-492
2.22 MSRS IN THE P6 FAMILY PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-499
2.23 MSRS IN PENTIUM PROCESSORS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-509
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Vol. 4 v
CONTENTS
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TABLES
Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
Table 2-2. IA-32 Architectural MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82
Table 2-5. MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel Value of
06_27H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-94
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel Value
of 06_37H, 06_4AH, 06_5AH, or 06_5DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-111
Table 2-9. Specific MSRs Supported by the Intel Atom® Processor E3000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_37H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-112
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-114
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142
Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-147
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-149
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-171
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-173
Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . 2-193
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-195
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-197
Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture) . . . . . . . . . . . . .2-220
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-221
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge Microarchitecture 2-225
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-230
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge Microarchitecture . . 2-236
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture) . . . . . . . . . 2-239
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-251
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-255
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures . . . . . . . . . . . . 2-260
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) . . . . . . . . . . . . . . . . . . . . . . 2-265
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a
CPUID Signature DisplayFamily_DisplayModel Value of 06_45H2-276
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-277
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-291
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-306
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors . . . . . . . . . . 2-308
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-310
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_56H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-321
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_4FH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-324
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation Intel®
Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-332
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™ Processors,
and 8th generation Intel® Core™ i3 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-353
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based on Kaby
Lake Microarchitecture and Coffee Lake Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-355
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-357
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture . . . . . . . . . . . . 2-361
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) . . . . . . . . . . . . . . . . . 2-364
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-367
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting Performance
Hybrid Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-371
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PAGE
Table 2-47. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-375
Table 2-48. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor E-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-376
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors . . . . . . . . . . . . . . . . . . . . . . . . . .2-377
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_55H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-380
Table 2-51. MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-397
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-399
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid Architecture2-410
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-431
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-432
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_57H or 06_85H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-433
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_85H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-452
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-454
Table 2-59. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-480
Table 2-60. MSRs Unique to Intel® Xeon® Processor 7100 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-481
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV . . . . . . . . . . . . . . .2-481
Table 2-62. MSRs in Pentium M Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-492
Table 2-63. MSRs in the P6 Family Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-499
Table 2-64. MSRs in the Pentium Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-510
Vol. 4 1-1
CHAPTER 1
ABOUT THIS MANUAL
The Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 4: Model-Specific Registers (order
number 335592) is part of a set that describes the architecture and programming environment of Intel
®
64 and IA-
32 architecture processors. Other volumes in this set are:
• Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (order number
253665).
• Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A, 2B, 2C, & 2D: Instruction Set
Reference (order numbers 253666, 253667, 326018, and 334569).
• The Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C, & 3D: System
Programming Guide (order numbers 253668, 253669, 326019, and 332831).
The Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, describes the basic architecture
and programming environment of Intel 64 and IA-32 processors. The Intel
®
64 and IA-32 Architectures Software
Developer’s Manual, Volumes 2A, 2B, 2C, & 2D, describe the instruction set of the processor and the opcode struc-
ture. These volumes apply to application programmers and to programmers who write operating systems or exec-
utives. The Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A, 3B, 3C, & 3D, describe
the operating-system support environment of Intel 64 and IA-32 processors. These volumes target operating-
system and BIOS designers. In addition, the Intel
®
64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B, and the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 3C, address the
programming environment for classes of software that host operating systems. The Intel
®
64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 4, describes the model-specific registers of Intel 64 and IA-32 proces-
sors.
1.1 OVERVIEW OF THE MODEL-SPECIFIC REGISTERS
A description of this manual’s content follows:
Chapter 1 — About This Manual. Gives an overview of all volumes of the Intel
®
64 and IA-32 Architectures Soft-
ware Developer’s Manual, with chapter-specific details for the current volume.
Chapter 2 — Model-Specific Registers (MSRs). Lists the MSRs available in Intel processors, and describes their
functions.
1-2 Vol. 4
ABOUT THIS MANUAL
Vol. 4 2-1
CHAPTER 2
MODEL-SPECIFIC REGISTERS (MSRS)
This chapter lists MSRs across Intel processor families. All MSRs listed can be read with the RDMSR and written with
the WRMSR instructions. The scope of an MSR defines the set of processors that access the same MSR with RDMSR
and WRMSR. Thread-scope MSRs are unique to every logical processor. Core-scope MSRs are shared by the threads
in the same core; similarly for module-scope, die-scope, and package-scope.
When a processor package contains a single die, die-scope and package-scope are synonymous. When a package
contains multiple die, they are distinct.
NOTE
For information on hierarchical level types supported, refer to the CPUID Leaf 1FH definition for the
actual level type numbers: “V2 Extended Topology Enumeration Leaf” in the Intel
®
64 and IA-32
Architectures Software Developer’s Manual, Volume 2A. Also see Section 9.9.1, “Hierarchical
Mapping of Shared Resources,” in the Intel
®
64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A.
Register addresses are given in both hexadecimal and decimal. The register name is the mnemonic register name
and the bit description describes individual bits in registers.
Model specific registers and its bit-fields may be supported for a finite range of processor families/models. To distin-
guish between different processor family and/or models, software must use CPUID.01H leaf function to query the
combination of DisplayFamily and DisplayModel to determine model-specific availability of MSRs (see CPUID
instruction in Chapter 3, “Instruction Set Reference, A-L,” in the Intel
®
64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 2A). Table 2-1 lists the signature values of DisplayFamily and DisplayModel for various
processor families or processor number series.
Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel
DisplayFamily_DisplayModel Processor Families/Processor Number Series
06_85H Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series based on Knights Mill microarchitecture
06_57H Intel® Xeon Phi™ Processor 3200, 5200, 7200 Series based on Knights Landing microarchitecture
06_AAH Intel® Core™ Ultra 7 processors supporting Meteor Lake performance hybrid architecture
06_CFH 5th generation Intel® Xeon® Scalable Processor Family based on Emerald Rapids microarchitecture
06_8FH 4th generation Intel® Xeon® Scalable Processor Family based on Sapphire Rapids microarchitecture
06_BAH, 06_B7H, 06_BFH 13th generation Intel® Core™ processors supporting Raptor Lake performance hybrid architecture
06_97H, 06_9AH 12th generation Intel® Core™ processors supporting Alder Lake performance hybrid architecture
06_8CH, 06_8DH 11th generation Intel® Core™ processors based on Tiger Lake microarchitecture
06_A7H 11th generation Intel® Core™ processors based on Rocket Lake microarchitecture
06_7DH, 06_7EH 10th generation Intel® Core™ processors based on Ice Lake microarchitecture
06_A5H, 06_A6H 10th generation Intel® Core™ processors based on Comet Lake microarchitecture
06_66H Intel® Core™ processors based on Cannon Lake microarchitecture
06_8EH, 06_9EH 7th generation Intel® Core™ processors based on Kaby Lake microarchitecture, 8th and 9th generation
Intel® Core™ processors based on Coffee Lake microarchitecture, Intel® Xeon® E processors based on
Coffee Lake microarchitecture
06_6AH, 06_6CH 3rd generation Intel® Xeon® Scalable Processor Family based on Ice Lake microarchitecture
06_55H Intel® Xeon® Scalable Processor Family based on Skylake microarchitecture, 2nd generation Intel®
Xeon® Scalable Processor Family based on Cascade Lake product, and 3rd generation Intel® Xeon®
Scalable Processor Family based on Cooper Lake product
2-2 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
06_4EH, 06_5EH 6th generation Intel Core processors and Intel Xeon processor E3-1500m v5 product family and E3-
1200 v5 product family based on Skylake microarchitecture
06_56H Intel Xeon processor D-1500 product family based on Broadwell microarchitecture
06_4FH Intel Xeon processor E5 v4 Family based on Broadwell microarchitecture, Intel Xeon processor E7 v4
Family, Intel Core i7-69xx Processor Extreme Edition
06_47H 5th generation Intel Core processors, Intel Xeon processor E3-1200 v4 product family based on
Broadwell microarchitecture
06_3DH Intel Core M-5xxx Processor, 5th generation Intel Core processors based on Broadwell
microarchitecture
06_3FH Intel Xeon processor E5-4600/2600/1600 v3 product families, Intel Xeon processor E7 v3 product
families based on Haswell-E microarchitecture, Intel Core i7-59xx Processor Extreme Edition
06_3CH, 06_45H, 06_46H 4th Generation Intel Core processor and Intel Xeon processor E3-1200 v3 product family based on
Haswell microarchitecture
06_3EH Intel Xeon processor E7-8800/4800/2800 v2 product families based on Ivy Bridge-E
microarchitecture
06_3EH Intel Xeon processor E5-2600/1600 v2 product families and Intel Xeon processor E5-2400 v2
product family based on Ivy Bridge-E microarchitecture, Intel Core i7-49xx Processor Extreme Edition
06_3AH 3rd Generation Intel Core Processor and Intel Xeon processor E3-1200 v2 product family based on Ivy
Bridge microarchitecture
06_2DH Intel Xeon processor E5 Family based on Sandy Bridge microarchitecture, Intel Core i7-39xx
Processor Extreme Edition
06_2FH Intel Xeon Processor E7 Family
06_2AH Intel Xeon processor E3-1200 product family; 2nd Generation Intel Core i7, i5, i3 Processors 2xxx
Series
06_2EH Intel Xeon processor 7500, 6500 series
06_25H, 06_2CH Intel Xeon processors 3600, 5600 series, Intel Core i7, i5, and i3 Processors
06_1EH, 06_1FH Intel Core i7 and i5 Processors
06_1AH Intel Core i7 Processor, Intel Xeon processor 3400, 3500, 5500 series
06_1DH Intel Xeon processor MP 7400 series
06_17H Intel Xeon processor 3100, 3300, 5200, 5400 series, Intel Core 2 Quad processors 8000, 9000
series
06_0FH Intel Xeon processor 3000, 3200, 5100, 5300, 7300 series, Intel Core 2 Quad processor 6000 series,
Intel Core 2 Extreme 6000 series, Intel Core 2 Duo 4000, 5000, 6000, 7000 series processors, Intel
Pentium dual-core processors
06_0EH Intel Core Duo, Intel Core Solo processors
06_0DH Intel Pentium M processor
06_86H, 06_96H, 06_9CH Intel Atom® processors, Intel® Celeron® processors, Intel® Pentium® processors, and Intel® Pentium®
Silver processors based on Tremont Microarchitecture
06_7AH Intel Atom processors based on Goldmont Plus microarchitecture
06_5FH Intel Atom processors based on Goldmont microarchitecture (Denverton)
06_5CH Intel Atom processors based on Goldmont microarchitecture
06_4CH Intel Atom processor X7-Z8000 and X5-Z8000 series based on Airmont microarchitecture
06_5DH Intel Atom processor X3-C3000 based on Silvermont microarchitecture
06_5AH Intel Atom processor Z3500 series
06_4AH Intel Atom processor Z3400 series
Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel (Contd.)
DisplayFamily_DisplayModel Processor Families/Processor Number Series
Vol. 4 2-3
MODEL-SPECIFIC REGISTERS (MSRS)
2.1 ARCHITECTURAL MSRS
Many MSRs have carried over from one generation of IA-32 processors to the next and to Intel 64 processors. A
subset of MSRs and associated bit fields, which do not change on future processor generations, are now considered
architectural MSRs. For historical reasons (beginning with the Pentium 4 processor), these “architectural MSRs”
were given the prefix “IA32_”. Table 2-2 lists the architectural MSRs, their addresses, their current names, their
names in previous IA-32 processors, and bit fields that are considered architectural. MSR addresses outside Table
2-2 and certain bit fields in an MSR address that may overlap with architectural MSR addresses are model-specific.
Code that accesses a model-specific MSR and that is executed on a processor that does not support that MSR will
generate an exception.
Architectural MSR or individual bit fields in an architectural MSR may be introduced or transitioned at the granu-
larity of certain processor family/model or the presence of certain CPUID feature flags. The right-most column of
Table 2-2 provides information on the introduction of each architectural MSR or its individual fields. This informa-
tion is expressed either as signature values of “DF_DM” (see Table 2-1) or via CPUID flags.
Certain bit field position may be related to the maximum physical address width, the value of which is expressed
as “MAXPHYADDR” in Table 2-2. “MAXPHYADDR” is reported by CPUID.8000_0008H leaf.
MSR address range between 40000000H - 4000FFFFH is marked as a specially reserved range. All existing and
future processors will not implement any features using any MSR in this range.
06_37H Intel Atom processor E3000 series, Z3600 series, Z3700 series
06_4DH Intel Atom processor C2000 series
06_36H Intel Atom processor S1000 Series
06_1CH, 06_26H, 06_27H,
06_35H, 06_36H
Intel Atom processor family, Intel Atom processor D2000, N2000, E2000, Z2000, C1000 series
0F_06H Intel Xeon processor 7100, 5000 Series, Intel Xeon Processor MP, Intel Pentium 4, Pentium D
processors
0F_03H, 0F_04H Intel Xeon processor, Intel Xeon processor MP, Intel Pentium 4, Pentium D processors
06_09H Intel Pentium M processor
0F_02H Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors
0F_0H, 0F_01H Intel Xeon Processor, Intel Xeon processor MP, Intel Pentium 4 processors
06_7H, 06_08H, 06_0AH,
06_0BH
Intel Pentium III Xeon processor, Intel Pentium III processor
06_03H, 06_05H Intel Pentium II Xeon processor, Intel Pentium II processor
06_01H Intel Pentium Pro processor
05_01H, 05_02H, 05_04H Intel Pentium processor, Intel Pentium processor with MMX Technology
The Intel® Quark™ SoC X1000 processor can be identified by the signature of DisplayFamily_DisplayModel = 05_09H and
SteppingID = 0
Table 2-2. IA-32 Architectural MSRs
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Register Address: 0H, 0 IA32_P5_MC_ADDR (P5_MC_ADDR)
See Section 2.23, “MSRs in Pentium Processors.” Pentium Processor (05_01H)
Register Address: 1H, 1 IA32_P5_MC_TYPE (P5_MC_TYPE)
See Section 2.23, “MSRs in Pentium Processors.” DF_DM = 05_01H
Table 2-1. CPUID Signature Values of DisplayFamily_DisplayModel (Contd.)
DisplayFamily_DisplayModel Processor Families/Processor Number Series
2-4 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” 0F_03H
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER (TSC)
See Section 18.17, “Time-Stamp Counter.” 05_01H
Register Address: 17H, 23 IA32_PLATFORM_ID (MSR_PLATFORM_ID)
Platform ID (R/O)
The operating system can use this MSR to determine “slot” information for the processor and the
proper microcode update to load.
06_01H
49:0 Reserved.
52:50 Platform ID (R/O)
Contains information concerning the intended platform for the
processor.
52 51 50
0 0 0 Processor Flag 0
0 0 1 Processor Flag 1
0 1 0 Processor Flag 2
0 1 1 Processor Flag 3
1 0 0 Processor Flag 4
1 0 1 Processor Flag 5
1 1 0 Processor Flag 6
1 1 1 Processor Flag 7
63:53 Reserved.
Register Address: 1BH, 27 IA32_APIC_BASE (APIC_BASE)
This register holds the APIC base address, permitting the relocation of the APIC memory map. See
Section 11.4.4, “Local APIC Status and Location,” and Section 11.4.5, “Relocating the Local APIC
Registers.”
06_01H
7:0 Reserved.
8BSP Flag (R/W)
9Reserved.
10 Enable x2APIC mode. 06_1AH
11 APIC Global Enable (R/W)
(MAXPHYADDR -1):12 APIC Base (R/W)
63: MAXPHYADDR Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W) If any one enumeration condition
for defined bit field holds.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-5
MODEL-SPECIFIC REGISTERS (MSRS)
0 Lock bit (R/WO): (1 = locked).
When set, locks this MSR from being written; writes to this bit will result
in GP(0).
Note: Once the Lock bit is set, the contents of this register cannot be
modified. Therefore the lock bit must be set after configuring support for
Intel Virtualization Technology and prior to transferring control to an
option ROM or the OS. Hence, once the Lock bit is set, the entire
IA32_FEATURE_CONTROL contents are preserved across RESET when
PWRGOOD is not deasserted.
If any one enumeration condition
for defined bit field position
greater than bit 0 holds.
1 Enable VMX inside SMX operation (R/WL) This bit enables a system
executive to use VMX in conjunction with SMX to support Intel® Trusted
Execution Technology.
BIOS must set this bit only when the CPUID function 1 returns VMX
feature flag and SMX feature flag set (ECX bits 5 and 6 respectively).
If CPUID.01H:ECX[5] = 1 &&
CPUID.01H:ECX[6] = 1
2 Enable VMX outside SMX operation (R/WL) This bit enables VMX for a
system executive that does not require SMX.
BIOS must set this bit only when the CPUID function 1 returns the VMX
feature flag set (ECX bit 5).
If CPUID.01H:ECX[5] = 1
7:3 Reserved.
14:8 SENTER Local Function Enables (R/WL) When set, each bit in the field
represents an enable control for a corresponding SENTER function. This
field is supported only if CPUID.1:ECX.[bit 6] is set.
If CPUID.01H:ECX[6] = 1
15 SENTER Global Enable (R/WL)
This bit must be set to enable SENTER leaf functions. This bit is
supported only if CPUID.1:ECX.[bit 6] is set.
If CPUID.01H:ECX[6] = 1
16 Reserved.
17 SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime re-configuration of SGX Launch
Control via the IA32_SGXLEPUBKEYHASHn MSR.
If CPUID.(EAX=07H, ECX=0H):
ECX[30] = 1
18 SGX Global Enable (R/WL)
This bit must be set to enable SGX leaf functions.
If CPUID.(EAX=07H, ECX=0H):
EBX[2] = 1
19 Reserved.
20 LMCE On (R/WL)
When set, system software can program the MSRs associated with LMCE
to configure delivery of some machine check exceptions to a single
logical processor.
If IA32_MCG_CAP[27] = 1
63:21 Reserved.
Register Address: 3BH, 59 IA32_TSC_ADJUST
Per Logical Processor TSC Adjust (R/Write to clear) If CPUID.(EAX=07H, ECX=0H):
EBX[1] = 1
63:0 THREAD_ADJUST
Local offset value of the IA32_TSC for a logical processor. Reset value is
zero. A write to IA32_TSC will modify the local offset in
IA32_TSC_ADJUST and the content of IA32_TSC, but does not affect the
internal invariant TSC hardware.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-6 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 48H, 72 IA32_SPEC_CTRL
Speculation Control (R/W)
The MSR bits are defined as logical processor scope. On some core implementations, the bits may
impact sibling logical processors on the same core.
This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#.
If any one of the enumeration
conditions for defined bit field
positions holds.
0 Indirect Branch Restricted Speculation (IBRS). Restricts speculation of
indirect branch.
If CPUID.(EAX=07H,
ECX=0):EDX[26]=1
1 Single Thread Indirect Branch Predictors (STIBP). Prevents indirect
branch predictions on all logical processors on the core from being
controlled by any sibling logical processor in the same core.
If CPUID.(EAX=07H,
ECX=0):EDX[27]=1
2 Speculative Store Bypass Disable (SSBD) delays speculative execution of
a load until the addresses for all older stores are known.
If CPUID.(EAX=07H,
ECX=0):EDX[31]=1
3 IPRED_DIS_U
If 1, enables IPRED_DIS control for CPL3.
If CPUID.(EAX=07H,
ECX=2):EDX[1]=1
4 IPRED_DIS_S
If 1, enables IPRED_DIS control for CPL0/1/2.
If CPUID.(EAX=07H,
ECX=2):EDX[1]=1
5 RRSBA_DIS_U
If 1, disables RRSBA behavior for CPL3.
If CPUID.(EAX=07H,
ECX=2):EDX[2]=1
6 RRSBA_DIS_S
If 1, disables RRSBA behavior for CPL0/1/2.
If CPUID.(EAX=07H,
ECX=2):EDX[2]=1
7PSFD
If 1, disables Fast Store Forwarding Predictor. Note that setting bit 2
(SSBD) also disables this.
If CPUID.(EAX=07H,
ECX=2):EDX[0]=1
8 DDPD_U
If 1, disables the Data Dependent Prefetcher that examines data values
in memory while CPL = 3. Note that setting bit 2 (SSBD) also disables
this.
If CPUID.(EAX=07H,
ECX=2):EDX[3]=1
9Reserved.
10 BHI_DIS_S
When ‘1, enables BHI_DIS_S behavior.
If CPUID.(EAX=07H,
ECX=2):EDX[4]=1
63:11 Reserved.
Register Address: 49H, 73 IA32_PRED_CMD
Prediction Command (WO)
Gives software a way to issue commands that affect the state of predictors.
If any one of the enumeration
conditions for defined bit field
positions holds.
0 Indirect Branch Prediction Barrier (IBPB) If CPUID.(EAX=07H,
ECX=0):EDX[26]=1
63:1 Reserved.
Register Address: 4EH, 78 IA32_PPIN_CTL
Protected Processor Inventory Number Enable Control (R/W) If CPUID.(EAX=07H,
ECX=01H):EBX[0]=1
1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-7
MODEL-SPECIFIC REGISTERS (MSRS)
0LockOut (R/WO)
If 0, indicates that further writes to IA32_PPIN_CTL is allowed.
If 1, indicates that further writes to IA32_PPIN_CTL is disallowed.
Writing 1 to this bit is only permitted if the Enable_PPIN bit is clear.
The Privileged System Software Inventory Agent should read
IA32_PPIN_CTL[bit 1] to determine if IA32_PPIN is accessible.
The Privileged System Software Inventory Agent is not expected to
write to this MSR.
1Enable_PPIN (R/W)
If 1, indicates that IA32_PPIN is accessible using RDMSR.
If 0, indicates that IA32_PPIN is inaccessible using RDMSR. Any attempt
to read IA32_PPIN will cause #GP.
63:2 Reserved.
Register Address: 4FH, 79 IA32_PPIN
Protected Processor Inventory Number (R/O) If CPUID.(EAX=07H,
ECX=01H):EBX[0]=1
1
63:0 Protected Processor Inventory Number (R/O)
A unique value within a given CPUID family/model/stepping signature
that a privileged inventory initialization agent can access to identify each
physical processor, when access to IA32_PPIN is enabled. Access to
IA32_PPIN is permitted only if IA32_PPIN_CTL[bits 1:0] = ‘10b’.
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG (BIOS_UPDT_TRIG)
BIOS Update Trigger (W)
Executing a WRMSR instruction to this MSR causes a microcode update to be loaded into the
processor. See Section 10.11.6, “Microcode Update Loader.”
A processor may prevent writing to this MSR when loading guest states on VM entries or saving
guest states on VM exits.
06_01H
Register Address: 7AH, 122 IA32_FEATURE_ACTIVATION
Feature Activation (R/W)
Implements Feature Activation command. WRMSR to this address activates all 'activatable'
features on this thread.
0 Reserved.
1KL
Keylocker feature activation.
63:2 Reserved.
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID (BIOS_SIGN/BBL_CR_D3)
BIOS Update Signature (R/W)
Returns the microcode update signature following the execution of CPUID.01H.
A processor may prevent writing to this MSR when loading guest states on VM entries or saving
guest states on VM exits.
06_01H
31:0 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-8 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:32 PATCH_SIGN_ID
It is recommended that this field be preloaded with zero prior to
executing CPUID. If the field remains zero following the execution of
CPUID, this indicates that no microcode update is loaded. Any non-zero
value is the microcode update signature patch signature ID.
Register Address: 8CH, 140 IA32_SGXLEPUBKEYHASH0
IA32_SGXLEPUBKEYHASH[63:0] (R/W)
Bits 63:0 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset,
the default value is the digest of Intel’s signing key.
Read permitted If
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1 && CPUID.(EAX=07H,
ECX=0H):ECX[30]=1.
Write permitted if
CPUID.(EAX=12H,ECX=0H):
EAX[0]=1 &&
IA32_FEATURE_CONTROL[17] = 1
&& IA32_FEATURE_CONTROL[0]
= 1.
Register Address: 8DH, 141 IA32_SGXLEPUBKEYHASH1
IA32_SGXLEPUBKEYHASH[127:64] (R/W)
Bits 127:64 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset,
the default value is the digest of Intel’s signing key.
Same comment in MSR listing for
IA32_SGXLEPUBKEYHASH0 (MSR
address 8CH, 140) applies here.
Register Address: 8EH, 142 IA32_SGXLEPUBKEYHASH2
IA32_SGXLEPUBKEYHASH[191:128] (R/W)
Bits 191:128 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On
reset, the default value is the digest of Intel’s signing key.
Same comment in MSR listing for
IA32_SGXLEPUBKEYHASH0 (MSR
address 8CH, 140) applies here.
Register Address: 8FH, 143 IA32_SGXLEPUBKEYHASH3
IA32_SGXLEPUBKEYHASH[255:192] (R/W)
Bits 255:192 of the SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On
reset, the default value is the digest of Intel’s signing key.
Same comment in MSR listing for
IA32_SGXLEPUBKEYHASH0 (MSR
address 8CH, 140) applies here.
Register Address: 9BH, 155 IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W) If CPUID.01H: ECX[5]=1 ||
CPUID.01H: ECX[6] = 1
0Valid (R/W)
1Reserved.
2 Controls SMI unblocking by VMXOFF (see Section 32.14.4). If IA32_VMX_MISC[28]
11:3 Reserved.
31:12 MSEG Base (R/W)
63:32 Reserved.
Register Address: 9EH, 158 IA32_SMBASE
Base address of the logical processor’s SMRAM image (R/O, SMM only). If IA32_VMX_MISC[15]
Register Address: BCH, 188 IA32_MISC_PACKAGE_CTLS
Power Filtering Control (R/W)
This MSR has a value of 0 after reset and is unaffected by INIT# or SIPI#.
If IA32_ARCH_CAPABILITIES
[10] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-9
MODEL-SPECIFIC REGISTERS (MSRS)
0 ENERGY_FILTERING_ENABLE (R/W)
If set, RAPL MSRs report filtered processor power consumption data.
This bit can be changed from 0 to 1, but cannot be changed from 1 to 0.
After setting, all attempts to clear it are ignored until the next processor
reset.
If IA32_ARCH_CAPABILITIES
[11] = 1
63:1 Reserved.
Register Address: BDH, 189 IA32_XAPIC_DISABLE_STATUS
xAPIC Disable Status (R/O) If CPUID.(EAX-07H,
ECX=0):EDX[29]=1 and
IA32_ARCH_CAPABILITIES [21] =
1
0 LEGACY_XAPIC_DISABLED
When set, indicates that the local APIC is in x2APIC mode
(IA32_APIC_BASE.EXTD = 1) and that attempts to clear
IA32_APIC_BASE.EXTD will fail (e.g., WRMSR will #GP).
63:1 Reserved.
Register Address: C1H, 193 IA32_PMC0 (PERFCTR0)
General Performance Counter 0 (R/W) If CPUID.0AH: EAX[15:8] > 0
Register Address: C2H, 194 IA32_PMC1 (PERFCTR1)
General Performance Counter 1 (R/W) If CPUID.0AH: EAX[15:8] > 1
Register Address: C3H, 195 IA32_PMC2
General Performance Counter 2 (R/W) If CPUID.0AH: EAX[15:8] > 2
Register Address: C4H, 196 IA32_PMC3
General Performance Counter 3 (R/W) If CPUID.0AH: EAX[15:8] > 3
Register Address: C5H, 197 IA32_PMC4
General Performance Counter 4 (R/W) If CPUID.0AH: EAX[15:8] > 4
Register Address: C6H, 198 IA32_PMC5
General Performance Counter 5 (R/W) If CPUID.0AH: EAX[15:8] > 5
Register Address: C7H, 199 IA32_PMC6
General Performance Counter 6 (R/W) If CPUID.0AH: EAX[15:8] > 6
Register Address: C8H, 200 IA32_PMC7
General Performance Counter 7 (R/W) If CPUID.0AH: EAX[15:8] > 7
Register Address: CFH, 207 IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register If CPUID.(EAX=07H,
ECX=0):EDX[30] = 1
63:0 Reserved. No architecturally defined bits.
Register Address: E1H, 225 IA32_UMWAIT_CONTROL
UMWAIT Control (R/W)
0 C0.2 is not allowed by the OS. Value of “1” means all C0.2 requests revert
to C0.1.
1 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-10 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
31:2 Determines the maximum time in TSC-quanta that the processor can
reside in either C0.1 or C0.2. A zero value indicates no maximum time.
The maximum time value is a 32-bit value where the upper 30 bits come
from this field and the lower two bits are zero.
Register Address: E7H, 231 IA32_MPERF
TSC Frequency Clock Counter (R/Write to clear) If CPUID.06H: ECX[0] = 1
63:0 C0_MCNT: C0 TSC Frequency Clock Count
Increments at fixed interval (relative to TSC freq.) when the logical
processor is in C0.
Cleared upon overflow / wrap-around of IA32_APERF.
Register Address: E8H, 232 IA32_APERF
Actual Performance Clock Counter (R/Write to clear) If CPUID.06H: ECX[0] = 1
63:0 C0_ACNT: C0 Actual Frequency Clock Count
Accumulates core clock counts at the coordinated clock frequency, when
the logical processor is in C0.
Cleared upon overflow / wrap-around of IA32_MPERF.
Register Address: FEH, 254 IA32_MTRRCAP (MTRRcap)
MTRR Capability (R/O)
See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
06_01H
7:0 VCNT: The number of variable memory type ranges in the processor.
8 Fixed range MTRRs are supported when set.
9Reserved.
10 WC Supported when set.
11 SMRR Supported when set.
12 PRMRR supported when set.
63:13 Reserved.
Register Address: 10AH, 266 IA32_ARCH_CAPABILITIES
Enumeration of Architectural Features (R/O) If CPUID.(EAX=07H,
ECX=0):EDX[29]=1
0 RDCL_NO: The processor is not susceptible to Rogue Data Cache Load
(RDCL).
1 IBRS_ALL: The processor supports enhanced IBRS.
2 RSBA: The processor supports RSB Alternate. Alternative branch
predictors may be used by RET instructions when the RSB is empty. SW
using retpoline may be affected by this behavior.
3 SKIP_L1DFL_VMENTRY: A value of 1 indicates the hypervisor need not
flush the L1D on VM entry.
4 SSB_NO: Processor is not susceptible to Speculative Store Bypass.
5 MDS_NO: Processor is not susceptible to Microarchitectural Data
Sampling (MDS).
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-11
MODEL-SPECIFIC REGISTERS (MSRS)
6 IF_PSCHANGE_MC_NO: The processor is not susceptible to a machine
check error due to modifying the size of a code page without TLB
invalidation.
7 TSX_CTRL: If 1, indicates presence of IA32_TSX_CTRL MSR.
8 TAA_NO: If 1, processor is not affected by TAA.
9 MCU_CONTROL: If 1, the processor supports the IA32_MCU_CONTROL
MSR.
10 MISC_PACKAGE_CTLS: The processor supports
IA32_MISC_PACKAGE_CTLS MSR.
11 ENERGY_FILTERING_CTL: The processor supports setting and reading
the IA32_MISC_PACKAGE_CTLS[0] (ENERGY_FILTERING_ENABLE) bit.
12 DOITM: If 1, the processor supports Data Operand Independent Timing
Mode.
13 SBDR_SSDP_NO: The processor is not affected by either the Shared
Buffers Data Read (SBDR) vulnerability or the Sideband Stale Data
Propagator (SSDP).
14 FBSDP_NO: The processor is not affected by the Fill Buffer Stale Data
Propagator (FBSDP).
15 PSDP_NO: The processor is not affected by vulnerabilities involving the
Primary Stale Data Propagator (PSDP).
16 Reserved.
17 FB_CLEAR: If 1, the processor supports overwrite of fill buffer values as
part of MD_CLEAR operations with the VERW instruction.
18 FB_CLEAR_CTRL: If 1, the processor supports the IA32_MCU_OPT_CTRL
MSR and allows software to set bit 3 of that MSR (FB_CLEAR_DIS).
19 RRSBA: A value of 1 indicates the processor may have the RRSBA
alternate prediction behavior, if not disabled by RRSBA_DIS_U or
RRSBA_DIS_S.
20 BHI_NO: A value of 1 indicates BHI_NO branch prediction behavior,
regardless of the value of IA32_SPEC_CTRL[BHI_DIS_S] MSR bit.
21 XAPIC_DISABLE_STATUS: Enumerates that the
IA32_XAPIC_DISABLE_STATUS MSR exists, and that bit 0 specifies
whether the legacy xAPIC is disabled and APIC state is locked to x2APIC.
22 Reserved.
23 OVERCLOCKING_STATUS: If set, the IA32_OVERCLOCKING_STATUS MSR
exists.
24 PBRSB_NO: If 1, the processor is not affected by issues related to Post-
Barrier Return Stack Buffer Predictions.
25 GDS_CTRL: If 1, the processor supports the GDS_MITG_DIS and
GDS_MITG_LOCK bits of the IA32_MCU_OPT_CTRL MSR.
26 GDS_NO: If 1, the processor is not affected by Gather Data Sampling.
27 RFDS_NO: If 1, the processor is not affected by Register File Data
Sampling.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-12 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
28 RFDS_CLEAR: If 1, when VERW is executed the processor will clear stale
data from register files affected by Register File Data Sampling.
29 IGN_UMONITOR_SUPPORT
If 0, IA32_MCU_OPT_CTRL bit 6 (IGN_UMONITOR) is not supported.
If 1, it indicates support of IA32_MCU_OPT_CTRL bit 6 (IGN_UMONITOR).
30 MON_UMON_MITG_SUPPORT
If 0, IA32_MCU_OPT_CTRL bit 7 (MON_UMON_MITG) is not supported.
If 1, it indicates support of IA32_MCU_OPT_CTRL bit 7
(MON_UMON_MITG).
63:31 Reserved.
Register Address: 10BH, 267 IA32_FLUSH_CMD
Flush Command (WO)
Gives software a way to invalidate structures with finer granularity than other architectural
methods.
If any one of the enumeration
conditions for defined bit field
positions holds.
0L1D_FLUSH
Writeback and invalidate the L1 data cache.
If CPUID.(EAX=07H,
ECX=0):EDX[28]=1
63:1 Reserved.
Register Address: 10FH, 271 IA32_TSX_FORCE_ABORT
TSX Force Abort If CPUID.(EAX=07H,
ECX=0):EDX[13]=1
0 RTM_FORCE_ABORT
If 1, all RTM transactions abort with EAX code 0.
R/W, Default: 0
If CPUID.(EAX=07H,ECX=0):
EDX[11]=1, bit 0 is always 1 and
writes to change it are ignored.
If SDV_ENABLE_RTM is 1, bit 0 is
always 0 and writes to change it
are ignored.
1 TSX_CPUID_CLEAR
When set, CPUID.(EAX=07H,ECX=0):EBX[11]=0 and
CPUID.(EAX=07H,ECX=0):EBX[4]=0.
R/W, Default: 0
Can be set only if
CPUID.(EAX=07H,ECX=0):
EDX[11]=1 or if
SDV_ENABLE_RTM is 1.
2SDV_ENABLE_RTM
When set, CPUID.(EAX=07H,ECX=0):EDX[11]=0 and the processor may
not force abort RTM. This unsupported mode should only be used for
software development and not for production usage.
R/W, Default: 0
If 0, can be set only if
CPUID.(EAX=07H,ECX=0):
EDX[11]=1.
63:3 Reserved.
Register Address: 122H, 290 IA32_TSX_CTRL
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-13
MODEL-SPECIFIC REGISTERS (MSRS)
IA32_TSX_CTRL Thread scope. Not architecturally
serializing.
Available when
CPUID.ARCH_CAP(EAX=7H, ECX =
0):EDX[29] = 1 and
IA32_ARCH_CAPABILITIES.bit 7 =
1.
0 RTM_DISABLE
When set to 1, XBEGIN will always abort with EAX code 0.
1TSX_CPUID_CLEAR
When set to 1, CPUID.07H.EBX.RTM [bit 11] and CPUID.07H.EBX.HLE [bit
4] report 0.
When set to 0 and the SKU supports TSX, these bits will return 1.
63:2 Reserved.
Register Address: 123H, 291 IA32_MCU_OPT_CTRL
Microcode Update Option Control (R/W) If CPUID.(EAX=07H,
ECX=0):EDX[9]=1 or
IA32_ARCH_CAPABILITIES [18] =
1 or IA32_ARCH_CAPABILITIES.
FB_CLEAR_CTRL=1
0 RNGDS_MITG_DIS (R/W)
If 0 (default), SRBDS mitigation is enabled for RDRAND and RDSEED.
If 1, SRBDS mitigation is disabled for RDRAND and RDSEED executed
outside of Intel SGX enclaves.
If CPUID.(EAX=07H,
ECX=0):EDX[9]=1
1 RTM_ALLOW
If 0, XBEGIN will always abort with EAX code 0.
If 1, XBEGIN behavior depends on the value of
IA32_TSX_CTRL[RTM_DISABLE].
Read/Write
Setting RTM_LOCKED prevents
writes to this bit.
2RTM_LOCKED
When 1, RTM_ALLOW is locked at zero, writes to RTM_ALLOW will be
ignored.
Read-Only status bit.
3FB_CLEAR_DIS
If 1, prevents the VERW instruction from performing an FB_CLEAR
action.
If IA32_ARCH_CAPABILITIES.
FB_CLEAR_CTRL=1
4 GDS_MITG_DIS
If 0, the Gather Data Sampling mitigation is enabled (patch load time
default).
If 1 on all threads for a given core, the Gather Data Sampling mitigation is
disabled.
5GDS_MITG_LOCK
If 0, not locked, and GDS_MITG_DIS is under OS control.
If 1, locked and GDS_MITG_DIS is forced to 0 (writes are ignored).
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-14 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
6IGN_UMONITOR
If 0, enable CPL0-3 software to use the UMONITOR/UMWAIT
instructions.
If 1 (default), disable UMONITOR functionality. CPL0-3 software will be
able to call the UMONITOR instruction without causing a fault, however
the address monitoring hardware will not be armed. When UMWAIT is
called, it will not enter an implementation-dependent optimized state.
7 MON_UMON_MITG
If 0 (default), disabled.
If 1, enable: Flush the thread’s previously monitored address from the
CPU caches as part of the (U)MONITOR instruction. Additionally, for
every 4th (U)MONITOR instruction within a core, flush the peer
hyperthread's monitored address from the CPU caches as well. This will
increase the latency of the instruction. This may have a minor impact on
workloads using the (U)MONITOR instruction.
63:8 Reserved.
Register Address: 174H, 372 IA32_SYSENTER_CS
SYSENTER_CS_MSR (R/W) 06_01H
15:0 CS Selector.
31:16 Not used. Can be read and written.
63:32 Not used. Writes ignored; reads
return zero.
Register Address: 175H, 373 IA32_SYSENTER_ESP
SYSENTER_ESP_MSR (R/W) 06_01H
Register Address: 176H, 374 IA32_SYSENTER_EIP
SYSENTER_EIP_MSR (R/W) 06_01H
Register Address: 179H, 377 IA32_MCG_CAP (MCG_CAP)
Global Machine Check Capability (R/O) 06_01H
7:0 Count: Number of reporting banks.
8 MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
9 MCG_EXT_P: Extended machine check state registers are present if this
bit is set.
10 MCP_CMCI_P: Support for corrected MC error event is present. 06_01H
11 MCG_TES_P: Threshold-based error status register are present if this bit
is set.
15:12 Reserved.
23:16 MCG_EXT_CNT: Number of extended machine check state registers
present.
24 MCG_SER_P: The processor supports software error recovery if this bit is
set.
25 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-15
MODEL-SPECIFIC REGISTERS (MSRS)
26 MCG_ELOG_P: Indicates that the processor allows platform firmware to
be invoked when an error is detected so that it may provide additional
platform specific information in an ACPI format “Generic Error Data
Entry” that augments the data included in machine check bank registers.
06_3EH
27 MCG_LMCE_P: Indicates that the processor supports extended state in
IA32_MCG_STATUS and associated MSR necessary to configure Local
Machine Check Exception (LMCE).
06_3EH
63:28 Reserved.
Register Address: 17AH, 378 IA32_MCG_STATUS (MCG_STATUS)
Global Machine Check Status (R/W) 06_01H
0 RIPV. Restart IP valid. 06_01H
1 EIPV. Error IP valid. 06_01H
2 MCIP. Machine check in progress. 06_01H
3 LMCE_S. If IA32_MCG_CAP.LMCE_P[27] =1
63:4 Reserved.
Register Address: 17BH, 379 IA32_MCG_CTL (MCG_CTL)
Global Machine Check Control (R/W) If IA32_MCG_CAP.CTL_P[8] =1
Register Address: 180H−185H, 384−389 N/A
Reserved 06_0EH
2
Register Address: 186H, 390 IA32_PERFEVTSEL0 (PERFEVTSEL0)
Performance Event Select Register 0 (R/W) If CPUID.0AH: EAX[15:8] > 0
7:0 Event Select: Selects a performance event logic unit.
15:8 UMask: Qualifies the microarchitectural condition to detect on the
selected event logic.
16 USR: Counts while in privilege level is not ring 0.
17 OS: Counts while in privilege level is ring 0.
18 Edge: Enables edge detection if set.
19 PC: Enables pin control.
20 INT: Enables interrupt on counter overflow.
21 AnyThread: When set to 1, it enables counting the associated event
conditions occurring across all logical processors sharing a processor
core. When set to 0, the counter only increments the associated event
conditions occurring in the logical processor which programmed the MSR.
22 EN: Enables the corresponding performance counter to commence
counting when this bit is set.
23 INV: Invert the CMASK.
31:24 CMASK: When CMASK is not zero, the corresponding performance
counter increments each cycle if the event count is greater than or equal
to the CMASK.
63:32 Reserved.
Register Address: 187H, 391 IA32_PERFEVTSEL1 (PERFEVTSEL1)
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-16 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Performance Event Select Register 1 (R/W) If CPUID.0AH: EAX[15:8] > 1
Register Address: 188H, 392 IA32_PERFEVTSEL2
Performance Event Select Register 2 (R/W) If CPUID.0AH: EAX[15:8] > 2
Register Address: 189H, 393 IA32_PERFEVTSEL3
Performance Event Select Register 3 (R/W) If CPUID.0AH: EAX[15:8] > 3
Register Address: 18AH, 394 IA32_PERFEVTSEL4
Performance Event Select Register 4 (R/W) If CPUID.0AH: EAX[15:8] > 4
Register Address: 18BH, 395 IA32_PERFEVTSEL5
Performance Event Select Register 5 (R/W) If CPUID.0AH: EAX[15:8] > 5
Register Address: 18CH, 396 IA32_PERFEVTSEL6
Performance Event Select Register 6 (R/W) If CPUID.0AH: EAX[15:8] > 6
Register Address: 18DH, 397 IA32_PERFEVTSEL7
Performance Event Select Register 7 (R/W) If CPUID.0AH: EAX[15:8] > 7
Register Address: 18AH−194H, 394−404 N/A
Reserved. 06_0EH
3
Register Address: 195H, 405 IA32_OVERCLOCKING_STATUS
Overclocking Status (R/O)
IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR.
0 Overclocking Utilized
Indicates if specific forms of overclocking have been enabled on this boot
or reset cycle: 0 indicates no, 1 indicates yes.
1 Undervolt Protection
Indicates if the “Dynamic OC Undervolt Protection” security feature is
active: 0 indicates disabled, 1indicates enabled.
2 Overclocking Secure Status
Indicates that overclocking capabilities have been unlocked by BIOS, with
or without overclocking: 0 indicates Not Secured, 1 indicates Secure.
63:4 Reserved.
Register Address: 196H−197H, 406−407 N/A
Reserved. 06_0EH
3
Register Address: 198H, 408 IA32_PERF_STATUS
Current Performance Status (R/O)
See Section 15.1.1, “Software Interface For Initiating Performance State Transitions.”
0F_03H
15:0 Current Performance State Value.
63:16 Reserved.
Register Address: 199H, 409 IA32_PERF_CTL
Performance Control MSR (R/W)
Software makes a request for a new Performance state (P-State) by writing this MSR. See
Section 15.1.1, “Software Interface For Initiating Performance State Transitions.”
0F_03H
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-17
MODEL-SPECIFIC REGISTERS (MSRS)
15:0 Target performance State Value.
31:16 Reserved.
32 Intel® Dynamic Acceleration Technology Engage (R/W)
When set to 1: Disengages Intel Dynamic Acceleration Technology.
06_0FH (Mobile only)
63:33 Reserved.
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation Control (R/W)
See Section 15.8.3, “Software Controlled Clock Modulation.”
If CPUID.01H:EDX[22] = 1
0 Extended On-Demand Clock Modulation Duty Cycle. If CPUID.06H:EAX[5] = 1
3:1 On-Demand Clock Modulation Duty Cycle: Specific encoded values for
target duty cycle modulation.
If CPUID.01H:EDX[22] = 1
4 On-Demand Clock Modulation Enable: Set 1 to enable modulation. If CPUID.01H:EDX[22] = 1
63:5 Reserved.
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
Enables and disables the generation of an interrupt on temperature transitions detected with the
processor’s thermal sensors and thermal monitor.
See Section 15.8.2, “Thermal Monitor.”
If CPUID.01H:EDX[22] = 1
0 High-Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1
1 Low-Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1
2 PROCHOT# Interrupt Enable If CPUID.01H:EDX[22] = 1
3 FORCEPR# Interrupt Enable If CPUID.01H:EDX[22] = 1
4 Critical Temperature Interrupt Enable If CPUID.01H:EDX[22] = 1
7:5 Reserved.
14:8 Threshold #1 Value If CPUID.01H:EDX[22] = 1
15 Threshold #1 Interrupt Enable If CPUID.01H:EDX[22] = 1
22:16 Threshold #2 Value If CPUID.01H:EDX[22] = 1
23 Threshold #2 Interrupt Enable If CPUID.01H:EDX[22] = 1
24 Power Limit Notification Enable If CPUID.06H:EAX[4] = 1
25 Hardware Feedback Notification Enable If CPUID.06H:EAX[24] = 1
63:26 Reserved.
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Status Information (R/O)
Contains status information about the processor’s thermal sensor and automatic thermal
monitoring facilities.
See Section 15.8.2, “Thermal Monitor.”
If CPUID.01H:EDX[22] = 1
0 Thermal Status (R/O) If CPUID.01H:EDX[22] = 1
1 Thermal Status Log (R/W) If CPUID.01H:EDX[22] = 1
2 PROCHOT # or FORCEPR# event (R/O) If CPUID.01H:EDX[22] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-18 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
3 PROCHOT # or FORCEPR# log (R/WC0) If CPUID.01H:EDX[22] = 1
4 Critical Temperature Status (R/O) If CPUID.01H:EDX[22] = 1
5 Critical Temperature Status log (R/WC0) If CPUID.01H:EDX[22] = 1
6 Thermal Threshold #1 Status (R/O) If CPUID.01H:ECX[8] = 1
7 Thermal Threshold #1 log (R/WC0) If CPUID.01H:ECX[8] = 1
8 Thermal Threshold #2 Status (R/O) If CPUID.01H:ECX[8] = 1
9 Thermal Threshold #2 log (R/WC0) If CPUID.01H:ECX[8] = 1
10 Power Limitation Status (R/O) If CPUID.06H:EAX[4] = 1
11 Power Limitation log (R/WC0) If CPUID.06H:EAX[4] = 1
12 Current Limit Status (R/O) If CPUID.06H:EAX[7] = 1
13 Current Limit log (R/WC0) If CPUID.06H:EAX[7] = 1
14 Cross Domain Limit Status (R/O) If CPUID.06H:EAX[7] = 1
15 Cross Domain Limit log (R/WC0) If CPUID.06H:EAX[7] = 1
22:16 Digital Readout (R/O) If CPUID.06H:EAX[0] = 1
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O) If CPUID.06H:EAX[0] = 1
31 Reading Valid (R/O) If CPUID.06H:EAX[0] = 1
63:32 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0 Fast-Strings Enable
When set, the fast-strings feature (for REP MOVS and REP STORS) is
enabled (default). When clear, fast-strings are disabled.
0F_0H
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
1 = Setting this bit enables the thermal control circuit (TCC) portion of
the Intel Thermal Monitor feature. This allows the processor to
automatically reduce power consumption in response to TCC
activation.
0 = Disabled.
Note: In some products clearing this bit might be ignored in critical
thermal conditions, and TM1, TM2, and adaptive thermal throttling will
still be activated.
The default value of this field varies with product. See respective tables
where default value is listed.
0F_0H
6:4 Reserved.
7 Performance Monitoring Available (R)
1 = Performance monitoring enabled.
0 = Performance monitoring disabled.
0F_0H
10:8 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-19
MODEL-SPECIFIC REGISTERS (MSRS)
11 Branch Trace Storage Unavailable (R/O)
1 = Processor doesn’t support branch trace storage (BTS).
0 = BTS is supported.
0F_0H
12 Processor Event Based Sampling (PEBS) Unavailable (R/O)
1 = PEBS is not supported.
0 = PEBS is supported.
06_0FH
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
0= Enhanced Intel SpeedStep Technology disabled.
1 = Enhanced Intel SpeedStep Technology enabled.
If CPUID.01H: ECX[7] =1
17 Reserved.
18 ENABLE MONITOR FSM (R/W)
When this bit is set to 0, the MONITOR feature flag is not set
(CPUID.01H:ECX[bit 3] = 0). This indicates that MONITOR/MWAIT are not
supported.
Software attempts to execute MONITOR/MWAIT will cause #UD when
this bit is 0.
When this bit is set to 1 (default), MONITOR/MWAIT are supported
(CPUID.01H:ECX[bit 3] = 1).
If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 0] = 0), the
OS must not attempt to alter this bit. BIOS must leave it in the default
state. Writing this bit when the SSE3 feature flag is set to 0 may
generate a #GP exception.
0F_03H
21:19 Reserved.
22 Limit CPUID Maxval (R/W)
When this bit is set to 1, CPUID.00H returns a maximum value in
EAX[7:0] of 2.
BIOS should contain a setup question that allows users to specify when
the installed OS does not support CPUID functions greater than 2.
Before setting this bit, BIOS must execute the CPUID.0H and examine
the maximum value returned in EAX[7:0]. If the maximum value is
greater than 2, this bit is supported.
Otherwise, this bit is not supported. Setting this bit when the maximum
value is not greater than 2 may generate a #GP exception.
Setting this bit may cause unexpected behavior in software that
depends on the availability of CPUID leaves greater than 2.
0F_03H
23 xTPR Message Disable (R/W)
When set to 1, xTPR messages are disabled. xTPR messages are optional
messages that allow the processor to inform the chipset of its priority.
If CPUID.01H:ECX[14] = 1
63:24 Reserved.
Note: Some older processors defined one of these bits as a disable for
the execute-disable feature of paging. If a processor supports this bit,
this information is provided in the model-specific tables. See Table 2-3
for the definition of this bit.
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-20 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Performance Energy Bias Hint (R/W) If CPUID.6H:ECX[3] = 1
3:0 Power Policy Preference:
0 indicates preference to highest performance.
15 indicates preference to maximize energy saving.
63:4 Reserved.
Register Address: 1B1H, 433 IA32_PACKAGE_THERM_STATUS
Package Thermal Status Information (R/O)
Contains status information about the package’s thermal sensor.
See Section 15.9, “Package Level Thermal Management.”
If CPUID.06H: EAX[6] = 1
0Pkg Thermal Status (R/O)
1 Pkg Thermal Status Log (R/W)
2 Pkg PROCHOT # event. (R/O)
3Pkg PROCHOT # log. (R/WC0)
4 Pkg Critical Temperature Status. (R/O)
5 Pkg Critical Temperature Status Log. (R/WC0)
6 Pkg Thermal Threshold #1 Status. (R/O)
7 Pkg Thermal Threshold #1 Log. (R/WC0)
8 Pkg Thermal Threshold #2 Status. (R/O)
9 Pkg Thermal Threshold #1 Log. (R/WC0)
10 Pkg Power Limitation Status. (R/O)
11 Pkg Power Limitation Log. (R/WC0)
15:12 Reserved.
22:16 Pkg Digital Readout. (R/O)
25:23 Reserved.
26 Hardware Feedback Interface Structure Change Status. If CPUID.06H:EAX.[19] = 1
63:27 Reserved.
Register Address: 1B2H, 434 IA32_PACKAGE_THERM_INTERRUPT
Pkg Thermal Interrupt Control (R/W)
Enables and disables the generation of an interrupt on temperature transitions detected with the
package’s thermal sensor.
See Section 15.9, “Package Level Thermal Management.”
If CPUID.06H: EAX[6] = 1
0 Pkg High-Temperature Interrupt Enable.
1 Pkg Low-Temperature Interrupt Enable.
2 Pkg PROCHOT# Interrupt Enable.
3Reserved.
4 Pkg Overheat Interrupt Enable.
7:5 Reserved.
14:8 Pkg Threshold #1 Value.
15 Pkg Threshold #1 Interrupt Enable.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-21
MODEL-SPECIFIC REGISTERS (MSRS)
22:16 Pkg Threshold #2 Value.
23 Pkg Threshold #2 Interrupt Enable.
24 Pkg Power Limit Notification Enable.
25 Hardware Feedback Interrupt Enable. If CPUID.06H:EAX.[19] = 1
63:26 Reserved.
Register Address: 1C4H, 452 IA32_XFD
Extended Feature Disable Control (R/W)
Controls which XSAVE-enabled features are temporarily disabled.
See Section 13.14 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual,
Volume 1.
If CPUID.(EAX=0DH,ECX=1):
EAX[4] = 1
Register Address: 1C5H, 453 IA32_XFD_ERR
Extended Feature Disable Error Code (R/W)
Reports which XSAVE-enabled features caused a fault due to being disabled.
See Section 13.14 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual,
Volume 1.
If CPUID.(EAX=0DH,ECX=1):
EAX[4] = 1
Register Address: 1D9H, 473 IA32_DEBUGCTL (MSR_DEBUGCTLA, MSR_DEBUGCTLB)
Trace/Profile Resource Control (R/W) 06_0EH
0 LBR: Setting this bit to 1 enables the processor to record a running trace
of the most recent branches taken by the processor in the LBR stack.
06_01H
1 BTF: Setting this bit to 1 enables the processor to treat EFLAGS.TF as
single-step on branches instead of single-step on instructions.
06_01H
2 BLD: Enable OS bus-lock detection. See Section 18.3.1.6 of the Intel
®
64
and IA-32 Architectures Software Developer’s Manual, Volume 3B.
If (CPUID.(EAX=07H,
ECX=0):ECX[24] = 1)
5:3 Reserved.
6 TR: Setting this bit to 1 enables branch trace messages to be sent. 06_0EH
7 BTS: Setting this bit enables branch trace messages (BTMs) to be logged
in a BTS buffer.
06_0EH
8 BTINT: When clear, BTMs are logged in a BTS buffer in circular fashion.
When this bit is set, an interrupt is generated by the BTS facility when
the BTS buffer is full.
06_0EH
9 1: BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. 06_0FH
10 BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. 06_0FH
11 FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a PMI
request.
If CPUID.01H: ECX[15] = 1 &&
CPUID.0AH: EAX[7:0] > 1
12 FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the global
counter control MSR are frozen (address 38FH) on a PMI request.
If CPUID.01H: ECX[15] = 1 &&
CPUID.0AH: EAX[7:0] > 1
13 ENABLE_UNCORE_PMI: When set, enables the logical processor to
receive and generate PMI on behalf of the uncore.
06_1AH
14 FREEZE_WHILE_SMM: When set, freezes perfmon and trace messages
while in SMM.
If IA32_PERF_CAPABILITIES[12]
= 1
15 RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If (CPUID.(EAX=07H,
ECX=0):EBX[11] = 1)
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-22 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:16 Reserved.
Register Address: 1DDH, 477 IA32_LER_FROM_IP
Last Event Record Source IP Register (R/W)
63:0 FROM_IP
The source IP of the recorded branch or event, in canonical form.
Reset Value: 0
Register Address: 1DEH, 478 IA32_LER_TO_IP
Last Event Record Destination IP Register (R/W)
63:0 TO_IP
The destination IP of the recorded branch or event, in canonical form.
Reset Value: 0
Register Address: 1E0H, 480 IA32_LER_INFO
Last Event Record Info Register (R/W)
55:0 Undefined, may be zero or non-zero. Writes of non- zero values do not
fault, but reads may return a different value.
Reset Value: 0
59:56 BR_TYPE
The branch type recorded by this LBR. Encodings match those of
IA32_LBR_x_INFO.
Reset Value: 0
60 Undefined, may be zero or non-zero. Writes of non- zero values do not
fault, but reads may return a different value.
Reset Value: 0
61 TSX_ABORT
This LBR record is a TSX abort. On processors that do not support Intel®
TSX (CPUID.07H.EBX.HLE[bit 4]=0 and CPUID.07H.EBX.RTM[bit 11]=0),
this bit is undefined.
Reset Value: 0
62 IN_TSX
This LBR record records a branch that retired during a TSX transaction.
On processors that do not support Intel® TSX (CPUID.07H.EBX.HLE[bit
4]=0 and CPUID.07H.EBX.RTM[bit 11]=0), this bit is undefined.
Reset Value: 0
63 MISPRED
The recorded branch taken/not-taken resolution (for conditional
branches) or target (for any indirect branch, including RETs) was
mispredicted.
Reset Value: 0
Register Address: 1F2H, 498 IA32_SMRR_PHYSBASE
SMRR Base Address (Writeable only in SMM)
Base address of SMM memory range.
If IA32_MTRRCAP.SMRR[11] = 1
7:0 Type. Specifies memory type of the range.
11:8 Reserved.
31:12 PhysBase
SMRR physical Base Address.
63:32 Reserved.
Register Address: 1F3H, 499 IA32_SMRR_PHYSMASK
SMRR Range Mask (Writeable only in SMM)
Range Mask of SMM memory range.
If IA32_MTRRCAP[SMRR] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-23
MODEL-SPECIFIC REGISTERS (MSRS)
10:0 Reserved.
11 Valid
Enable range mask.
31:12 PhysMask
SMRR address range mask.
63:32 Reserved.
Register Address: 1F8H, 504 IA32_PLATFORM_DCA_CAP
DCA Capability (R) If CPUID.01H: ECX[18] = 1
Register Address: 1F9H, 505 IA32_CPU_DCA_CAP
If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1
Register Address: 1FAH, 506 IA32_DCA_0_CAP
DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1
0 DCA_ACTIVE: Set by HW when DCA is fuse-enabled and no defeatures
are set.
2:1 TRANSACTION
6:3 DCA_TYPE
10:7 DCA_QUEUE_SIZE
12:11 Reserved.
16:13 DCA_DELAY: Writes will update the register but have no HW side-effect.
23:17 Reserved.
24 SW_BLOCK: SW can request DCA block by setting this bit.
25 Reserved.
26 HW_BLOCK: Set when DCA is blocked by HW (e.g., CR0.CD = 1).
31:27 Reserved.
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0 (MTRRphysBase0)
See Section 12.11.2.3, “Variable Range MTRRs.” If IA32_MTRRCAP[7:0] > 0
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
MTRRphysMask0 If IA32_MTRRCAP[7:0] > 0
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
MTRRphysBase1 If IA32_MTRRCAP[7:0] > 1
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
MTRRphysMask1 If IA32_MTRRCAP[7:0] > 1
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
MTRRphysBase2 If IA32_MTRRCAP[7:0] > 2
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
MTRRphysMask2 If IA32_MTRRCAP[7:0] > 2
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
MTRRphysBase3 If IA32_MTRRCAP[7:0] > 3
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-24 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
MTRRphysMask3 If IA32_MTRRCAP[7:0] > 3
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
MTRRphysBase4 If IA32_MTRRCAP[7:0] > 4
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
MTRRphysMask4 If IA32_MTRRCAP[7:0] > 4
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
MTRRphysBase5 If IA32_MTRRCAP[7:0] > 5
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
MTRRphysMask5 If IA32_MTRRCAP[7:0] > 5
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
MTRRphysBase6 If IA32_MTRRCAP[7:0] > 6
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
MTRRphysMask6 If IA32_MTRRCAP[7:0] > 6
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
MTRRphysBase7 If IA32_MTRRCAP[7:0] > 7
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
MTRRphysMask7 If IA32_MTRRCAP[7:0] > 7
Register Address: 210H, 528 IA32_MTRR_PHYSBASE8
MTRRphysBase8 If IA32_MTRRCAP[7:0] > 8
Register Address: 211H, 529 IA32_MTRR_PHYSMASK8
MTRRphysMask8 If IA32_MTRRCAP[7:0] > 8
Register Address: 212H, 530 IA32_MTRR_PHYSBASE9
MTRRphysBase9 If IA32_MTRRCAP[7:0] > 9
Register Address: 213H, 531 IA32_MTRR_PHYSMASK9
MTRRphysMask9 If IA32_MTRRCAP[7:0] > 9
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
MTRRfix64K_00000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
MTRRfix16K_80000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
MTRRfix16K_A0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000 (MTRRfix4K_C0000)
See Section 12.11.2.2, “Fixed Range MTRRs.” If CPUID.01H: EDX.MTRR[12] =1
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
MTRRfix4K_C8000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-25
MODEL-SPECIFIC REGISTERS (MSRS)
MTRRfix4K_D0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
MTRRfix4K_D8000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
MTRRfix4K_E0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
MTRRfix4K_E8000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
MTRRfix4K_F0000 If CPUID.01H: EDX.MTRR[12] =1
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1
Register Address: 277H, 631 IA32_PAT
IA32_PAT (R/W) If CPUID.01H: EDX.MTRR[16] =1
2:0 PA0
7:3 Reserved.
10:8 PA1
15:11 Reserved.
18:16 PA2
23:19 Reserved.
26:24 PA3
31:27 Reserved.
34:32 PA4
39:35 Reserved.
42:40 PA5
47:43 Reserved.
50:48 PA6
55:51 Reserved.
58:56 PA7
63:59 Reserved.
Register Address: 280H, 640 IA32_MC0_CTL2
MSR to enable/disable CMCI capability for bank 0. (R/W)
See Section 16.3.2.5, “IA32_MC
i_CTL2 MSRs.”
If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 0
14:0 Corrected error count threshold.
29:15 Reserved.
30 CMCI_EN
63:31 Reserved.
Register Address: 281H, 641 IA32_MC1_CTL2
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-26 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 1
Register Address: 282H, 642 IA32_MC2_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 2
Register Address: 283H, 643 IA32_MC3_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 3
Register Address: 284H, 644 IA32_MC4_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 4
Register Address: 285H, 645 IA32_MC5_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 5
Register Address: 286H, 646 IA32_MC6_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 6
Register Address: 287H, 647 IA32_MC7_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 7
Register Address: 288H, 648 IA32_MC8_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 8
Register Address: 289H, 649 IA32_MC9_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 9
Register Address: 28AH, 650 IA32_MC10_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 10
Register Address: 28BH, 651 IA32_MC11_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 11
Register Address: 28CH, 652 IA32_MC12_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 12
Register Address: 28DH, 653 IA32_MC13_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 13
Register Address: 28EH, 654 IA32_MC14_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 14
Register Address: 28FH, 655 IA32_MC15_CTL2
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-27
MODEL-SPECIFIC REGISTERS (MSRS)
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 15
Register Address: 290H, 656 IA32_MC16_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 16
Register Address: 291H, 657 IA32_MC17_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 17
Register Address: 292H, 658 IA32_MC18_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 18
Register Address: 293H, 659 IA32_MC19_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 19
Register Address: 294H, 660 IA32_MC20_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 20
Register Address: 295H, 661 IA32_MC21_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 21
Register Address: 296H, 662 IA32_MC22_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 22
Register Address: 297H, 663 IA32_MC23_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 23
Register Address: 298H, 664 IA32_MC24_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 24
Register Address: 299H, 665 IA32_MC25_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 25
Register Address: 29AH, 666 IA32_MC26_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 26
Register Address: 29BH, 667 IA32_MC27_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 27
Register Address: 29CH, 668 IA32_MC28_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 28
Register Address: 29DH, 669 IA32_MC29_CTL2
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-28 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 29
Register Address: 29EH, 670 IA32_MC30_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 30
Register Address: 29FH, 671 IA32_MC31_CTL2
Same fields as IA32_MC0_CTL2. (R/W) If IA32_MCG_CAP[10] = 1 &&
IA32_MCG_CAP[7:0] > 31
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
MTRRdefType (R/W) If CPUID.01H: EDX.MTRR[12] =1
2:0 Default Memory Type
9:3 Reserved.
10 Fixed Range MTRR Enable
11 MTRR Enable
63:12 Reserved.
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If CPUID.0AH: EDX[4:0] > 0
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If CPUID.0AH: EDX[4:0] > 1
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If CPUID.0AH: EDX[4:0] > 2
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
Read Only MSR that enumerates the existence of performance monitoring features. (R/O) If CPUID.01H: ECX[15] = 1
5:0 LBR format
6 PEBS Trap
7 PEBSSaveArchRegs
11:8 PEBS Record Format
12 1: Freeze while SMM is supported.
13 1: Full width of counter writable via IA32_A_PMCx.
14 PEBS_BASELINE
15 1: Performance metrics available.
16 1: PEBS output will be written into the Intel PT trace stream. If CPUID.0x7.0.EBX[25]=1
63:17 Reserved.
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function Performance Counter Control (R/W)
Counter increments while the results of ANDing respective enable bit in
IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits in this MSR is true.
If CPUID.0AH: EAX[7:0] > 1
0 EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
1 EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-29
MODEL-SPECIFIC REGISTERS (MSRS)
2 AnyThr0: When set to 1, it enables counting the associated event
conditions occurring across all logical processors sharing a processor
core. When set to 0, the counter only increments the associated event
conditions occurring in the logical processor which programmed the MSR.
If CPUID.0AH:EAX[7:0] > 2 &&
CPUID.0AH:EDX[15]=0
3 EN0_PMI: Enable PMI when fixed counter 0 overflows.
4 EN1_OS: Enable Fixed Counter 1to count while CPL = 0.
5 EN1_Usr: Enable Fixed Counter 1to count while CPL > 0.
6 AnyThr1: When set to 1, it enables counting the associated event
conditions occurring across all logical processors sharing a processor
core. When set to 0, the counter only increments the associated event
conditions occurring in the logical processor which programmed the MSR.
If CPUID.0AH:EAX[7:0] > 2 &&
CPUID.0AH:EDX[15]=0
7 EN1_PMI: Enable PMI when fixed counter 1 overflows.
8 EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
9 EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
10 AnyThr2: When set to 1, it enables counting the associated event
conditions occurring across all logical processors sharing a processor
core. When set to 0, the counter only increments the associated event
conditions occurring in the logical processor which programmed the MSR.
If CPUID.0AH:EAX[7:0] > 2 &&
CPUID.0AH:EDX[15]=0
11 EN2_PMI: Enable PMI when fixed counter 2 overflows.
12 EN3_OS: Enable Fixed Counter 3 to count while CPL = 0.
13 EN3_Usr: Enable Fixed Counter 3 to count while CPL > 0.
14 Reserved.
15 EN3_PMI: Enable PMI when fixed counter 3 overflows.
63:16 Reserved.
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
Global Performance Counter Status (R/O) If CPUID.0AH: EAX[7:0] > 0 II
(CPUID.(EAX=07H,
ECX=0):EBX[25] = 1 &&
CPUID.(EAX=014H, ECX=0):ECX[0]
= 1)
0 Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: EAX[15:8] > 0
1 Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: EAX[15:8] > 1
2 Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: EAX[15:8] > 2
3 Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: EAX[15:8] > 3
n Ovf_PMCn: Overflow status of IA32_PMCn. If CPUID.0AH: EAX[15:8] > n
31:n+1 Reserved.
32 Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If CPUID.0AH: EAX[7:0] > 1
33 Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If CPUID.0AH: EAX[7:0] > 1
34 Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If CPUID.0AH: EAX[7:0] > 1
32+m Ovf_FixedCtrm: Overflow status of IA32_FIXED_CTRm. If CPUID.0AH:ECX[m] == 1 ||
CPUID.0AH:EDX[4:0] > m
47:33+m Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-30 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
48 OVF_PERF_METRICS: If this bit is set, it indicates that PERF_METRIC
counter has overflowed and a PMI is triggered; however, an overflow of
fixed counter 3 should normally happen first. If this bit is clear no
overflow occurred.
54:49 Reserved.
55 Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory buffer
that was completely filled.
If CPUID.(EAX=07H,
ECX=0):EBX[25] = 1 &&
CPUID.(EAX=014H, ECX=0):ECX[0]
= 1
57:56 Reserved.
58 LBR_Frz. LBRs are frozen due to:
• IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1.
•The LBR stack overflowed.
If CPUID.0AH: EAX[7:0] > 3
59 CTR_Frz. Performance counters in the core PMU are frozen due to:
• IA32_DEBUGCTL.FREEZE_PERFMON_ON_PMI=1.
• One or more core PMU counters overflowed.
If CPUID.0AH: EAX[7:0] > 3
60 ASCI: Data in the performance counters in the core PMU may include
contributions from the direct or indirect operation Intel SGX to protect an
enclave.
If CPUID.(EAX=07H,
ECX=0):EBX[2] = 1
61 Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: EAX[7:0] > 2
62 OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: EAX[7:0] > 0
63 CondChgd: Status bits of this register have changed. If CPUID.0AH: EAX[7:0] > 0
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
Global Performance Counter Control (R/W)
Counter increments while the result of ANDing the respective enable bit in this MSR with the
corresponding OS or USR bits in the general-purpose or fixed counter control MSR is true.
If CPUID.0AH: EAX[7:0] > 0
0 EN_PMC0 If CPUID.0AH: EAX[15:8] > 0
1 EN_PMC1 If CPUID.0AH: EAX[15:8] > 1
2 EN_PMC2 If CPUID.0AH: EAX[15:8] > 2
n EN_PMCn If CPUID.0AH: EAX[15:8] > n
31:n+1 Reserved.
32 EN_FIXED_CTR0 If CPUID.0AH: EDX[4:0] > 0
33 EN_FIXED_CTR1 If CPUID.0AH: EDX[4:0] > 1
34 EN_FIXED_CTR2 If CPUID.0AH: EDX[4:0] > 2
32+m EN_FIXED_CTRm If CPUID.0AH:ECX[m] == 1 ||
CPUID.0AH:EDX[4:0] > m
47:33+m Reserved.
48 EN_PERF_METRICS: If this bit is set and fixed counter 3 is effectively
enabled, built-in performance metrics are enabled.
63:49 Reserved.
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-31
MODEL-SPECIFIC REGISTERS (MSRS)
Global Performance Counter Overflow Control (R/W) If CPUID.0AH: EAX[7:0] > 0 &&
CPUID.0AH: EAX[7:0] <= 3
0 Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > 0
1 Set 1 to Clear Ovf_PMC1 bit. If CPUID.0AH: EAX[15:8] > 1
2 Set 1 to Clear Ovf_PMC2 bit. If CPUID.0AH: EAX[15:8] > 2
n Set 1 to Clear Ovf_PMCn bit. If CPUID.0AH: EAX[15:8] > n
31:n Reserved.
32 Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > 0
33 Set 1 to Clear Ovf_FIXED_CTR1 bit. If CPUID.0AH: EDX[4:0] > 1
34 Set 1 to Clear Ovf_FIXED_CTR2 bit. If CPUID.0AH: EDX[4:0] > 2
54:35 Reserved.
55 Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) &&
IA32_RTIT_CTL.ToPA = 1
60:56 Reserved.
61 Set 1 to Clear Ovf_Uncore bit. 06_2EH
62 Set 1 to Clear OvfBuf bit. If CPUID.0AH: EAX[7:0] > 0
63 Set 1 to clear CondChgd bit. If CPUID.0AH: EAX[7:0] > 0
Register Address: 390H, 912 IA32_PERF_GLOBAL_STATUS_RESET
Global Performance Counter Overflow Reset Control (R/W) If CPUID.0AH: EAX[7:0] > 3 II
(CPUID.(EAX=07H,
ECX=0):EBX[25] = 1 &&
CPUID.(EAX=14H, ECX=0):ECX[0]
= 1)
0 Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > 0
1 Set 1 to Clear Ovf_PMC1 bit. If CPUID.0AH: EAX[15:8] > 1
2 Set 1 to Clear Ovf_PMC2 bit. If CPUID.0AH: EAX[15:8] > 2
n Set 1 to Clear Ovf_PMCn bit. If CPUID.0AH: EAX[15:8] > n
31:n Reserved.
32 Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > 0
33 Set 1 to Clear Ovf_FIXED_CTR1 bit. If CPUID.0AH: EDX[4:0] > 1
34 Set 1 to Clear Ovf_FIXED_CTR2 bit. If CPUID.0AH: EDX[4:0] > 2
32+m Set 1 to Clear Ovf_FIXED_CTRm bit. If CPUID.0AH:ECX[m] == 1 ||
CPUID.0AH:EDX[4:0] > m
47:33+m Reserved.
48 RESET_OVF_PERF_METRICS: If this bit is set, it will clear the status bit in
the IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS
counters.
54:49 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-32 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
55 Set 1 to Clear Trace_ToPA_PMI bit. If CPUID.(EAX=07H,
ECX=0):EBX[25] = 1 &&
CPUID.(EAX=014H, ECX=0):ECX[0]
= 1
57:56 Reserved.
58 Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3
59 Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3
58 Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3
61 Set 1 to Clear Ovf_Uncore bit. 06_2EH
62 Set 1 to Clear OvfBuf bit. If CPUID.0AH: EAX[7:0] > 0
63 Set 1 to clear CondChgd bit. If CPUID.0AH: EAX[7:0] > 0
Register Address: 391H, 913 IA32_PERF_GLOBAL_STATUS_SET
Global Performance Counter Overflow Set Control (R/W) If CPUID.0AH: EAX[7:0] > 3 II
(CPUID.(EAX=07H,
ECX=0):EBX[25] = 1 &&
CPUID.(EAX=014H, ECX=0):ECX[0]
= 1)
0 Set 1 to cause Ovf_PMC0 = 1. If CPUID.0AH: EAX[7:0] > 3
1 Set 1 to cause Ovf_PMC1 = 1. If CPUID.0AH: EAX[15:8] > 1
2 Set 1 to cause Ovf_PMC2 = 1. If CPUID.0AH: EAX[15:8] > 2
n Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[15:8] > n
31:n Reserved.
32 Set 1 to cause Ovf_FIXED_CTR0 = 1. If CPUID.0AH: EAX[7:0] > 3
33 Set 1 to cause Ovf_FIXED_CTR1 = 1. If CPUID.0AH: EAX[7:0] > 3
34 Set 1 to cause Ovf_FIXED_CTR2 = 1. If CPUID.0AH: EAX[7:0] > 3
32+m Set 1 to cause Ovf_FIXED_CTRm = 1. If CPUID.0AH:ECX[m] == 1 ||
CPUID.0AH:EDX[4:0] > m
47:33+m Reserved.
48 SET_OVF_PERF_METRICS: If this bit is set, it will set the status bit in the
IA32_PERF_GLOBAL_STATUS register for the PERF_METRICS counters.
54:49 Reserved.
55 Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.(EAX=07H,
ECX=0):EBX[25] = 1 &&
CPUID.(EAX=014H, ECX=0):ECX[0]
= 1
57:56 Reserved.
58 Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3
59 Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3
58 Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3
61 Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3
62 Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-33
MODEL-SPECIFIC REGISTERS (MSRS)
63 Reserved.
Register Address: 392H, 914 IA32_PERF_GLOBAL_INUSE
Indicator that core perfmon interface is in use. (R/O) If CPUID.0AH: EAX[7:0] > 3
0 IA32_PERFEVTSEL0 in use.
1 IA32_PERFEVTSEL1 in use. If CPUID.0AH: EAX[15:8] > 1
2 IA32_PERFEVTSEL2 in use. If CPUID.0AH: EAX[15:8] > 2
n IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[15:8] > n
31:n+1 Reserved.
32 IA32_FIXED_CTR0 in use.
33 IA32_FIXED_CTR1 in use.
34 IA32_FIXED_CTR2 in use.
62:35 Reserved or model specific.
63 PMI in use.
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE
PEBS Control (R/W)
0 Enable PEBS on IA32_PMC0. 06_0FH
3:1 Reserved or model specific.
31:4 Reserved.
35:32 Reserved or model specific.
63:36 Reserved.
Register Address: 400H, 1024 IA32_MC0_CTL
MC0_CTL If IA32_MCG_CAP.CNT >0
Register Address: 401H, 1025 IA32_MC0_STATUS
MC0_STATUS If IA32_MCG_CAP.CNT >0
Register Address: 402H, 1026 IA32_MC0_ADDR
1
MC0_ADDR If IA32_MCG_CAP.CNT >0
Register Address: 403H, 1027 IA32_MC0_MISC
MC0_MISC If IA32_MCG_CAP.CNT >0
Register Address: 404H, 1028 IA32_MC1_CTL
MC1_CTL If IA32_MCG_CAP.CNT >1
Register Address: 405H, 1029 IA32_MC1_STATUS
MC1_STATUS If IA32_MCG_CAP.CNT >1
Register Address: 406H, 1030 IA32_MC1_ADDR
2
MC1_ADDR If IA32_MCG_CAP.CNT >1
Register Address: 407H, 1031 IA32_MC1_MISC
MC1_MISC If IA32_MCG_CAP.CNT >1
Register Address: 408H, 1032 IA32_MC2_CTL
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-34 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MC2_CTL If IA32_MCG_CAP.CNT >2
Register Address: 409H, 1033 IA32_MC2_STATUS
MC2_STATUS If IA32_MCG_CAP.CNT >2
Register Address: 40AH, 1034 IA32_MC2_ADDR
1
MC2_ADDR If IA32_MCG_CAP.CNT >2
Register Address: 40BH, 1035 IA32_MC2_MISC
MC2_MISC If IA32_MCG_CAP.CNT >2
Register Address: 40CH, 1036 IA32_MC3_CTL
MC3_CTL If IA32_MCG_CAP.CNT >3
Register Address: 40DH, 1037 IA32_MC3_STATUS
MC3_STATUS If IA32_MCG_CAP.CNT >3
Register Address: 40EH, 1038 IA32_MC3_ADDR
1
MC3_ADDR If IA32_MCG_CAP.CNT >3
Register Address: 40FH, 1039 IA32_MC3_MISC
MC3_MISC If IA32_MCG_CAP.CNT >3
Register Address: 410H, 1040 IA32_MC4_CTL
MC4_CTL If IA32_MCG_CAP.CNT >4
Register Address: 411H, 1041 IA32_MC4_STATUS
MC4_STATUS If IA32_MCG_CAP.CNT >4
Register Address: 412H, 1042 IA32_MC4_ADDR
1
MC4_ADDR If IA32_MCG_CAP.CNT >4
Register Address: 413H, 1043 IA32_MC4_MISC
MC4_MISC If IA32_MCG_CAP.CNT >4
Register Address: 414H, 1044 IA32_MC5_CTL
MC5_CTL If IA32_MCG_CAP.CNT >5
Register Address: 415H, 1045 IA32_MC5_STATUS
MC5_STATUS If IA32_MCG_CAP.CNT >5
Register Address: 416H, 1046 IA32_MC5_ADDR
1
MC5_ADDR If IA32_MCG_CAP.CNT >5
Register Address: 417H, 1047 IA32_MC5_MISC
MC5_MISC If IA32_MCG_CAP.CNT >5
Register Address: 418H, 1048 IA32_MC6_CTL
MC6_CTL If IA32_MCG_CAP.CNT >6
Register Address: 419H, 1049 IA32_MC6_STATUS
MC6_STATUS If IA32_MCG_CAP.CNT >6
Register Address: 41AH, 1050 IA32_MC6_ADDR
1
MC6_ADDR If IA32_MCG_CAP.CNT >6
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-35
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41BH, 1051 IA32_MC6_MISC
MC6_MISC If IA32_MCG_CAP.CNT >6
Register Address: 41CH, 1052 IA32_MC7_CTL
MC7_CTL If IA32_MCG_CAP.CNT >7
Register Address: 41DH, 1053 IA32_MC7_STATUS
MC7_STATUS If IA32_MCG_CAP.CNT >7
Register Address: 41EH, 1054 IA32_MC7_ADDR
1
MC7_ADDR If IA32_MCG_CAP.CNT >7
Register Address: 41FH, 1055 IA32_MC7_MISC
MC7_MISC If IA32_MCG_CAP.CNT >7
Register Address: 420H, 1056 IA32_MC8_CTL
MC8_CTL If IA32_MCG_CAP.CNT >8
Register Address: 421H, 1057 IA32_MC8_STATUS
MC8_STATUS If IA32_MCG_CAP.CNT >8
Register Address: 422H, 1058 IA32_MC8_ADDR
1
MC8_ADDR If IA32_MCG_CAP.CNT >8
Register Address: 423H, 1059 IA32_MC8_MISC
MC8_MISC If IA32_MCG_CAP.CNT >8
Register Address: 424H, 1060 IA32_MC9_CTL
MC9_CTL If IA32_MCG_CAP.CNT >9
Register Address: 425H, 1061 IA32_MC9_STATUS
MC9_STATUS If IA32_MCG_CAP.CNT >9
Register Address: 426H, 1062 IA32_MC9_ADDR
1
MC9_ADDR If IA32_MCG_CAP.CNT >9
Register Address: 427H, 1063 IA32_MC9_MISC
MC9_MISC If IA32_MCG_CAP.CNT >9
Register Address: 428H, 1064 IA32_MC10_CTL
MC10_CTL If IA32_MCG_CAP.CNT >10
Register Address: 429H, 1065 IA32_MC10_STATUS
MC10_STATUS If IA32_MCG_CAP.CNT >10
Register Address: 42AH, 1066 IA32_MC10_ADDR
1
MC10_ADDR If IA32_MCG_CAP.CNT >10
Register Address: 42BH, 1067 IA32_MC10_MISC
MC10_MISC If IA32_MCG_CAP.CNT >10
Register Address: 42CH, 1068 IA32_MC11_CTL
MC11_CTL If IA32_MCG_CAP.CNT >11
Register Address: 42DH, 1069 IA32_MC11_STATUS
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-36 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MC11_STATUS If IA32_MCG_CAP.CNT >11
Register Address: 42EH, 1070 IA32_MC11_ADDR
1
MC11_ADDR If IA32_MCG_CAP.CNT >11
Register Address: 42FH, 1071 IA32_MC11_MISC
MC11_MISC If IA32_MCG_CAP.CNT >11
Register Address: 430H, 1072 IA32_MC12_CTL
MC12_CTL If IA32_MCG_CAP.CNT >12
Register Address: 431H, 1073 IA32_MC12_STATUS
MC12_STATUS If IA32_MCG_CAP.CNT >12
Register Address: 432H, 1074 IA32_MC12_ADDR
1
MC12_ADDR If IA32_MCG_CAP.CNT >12
Register Address: 433H, 1075 IA32_MC12_MISC
MC12_MISC If IA32_MCG_CAP.CNT >12
Register Address: 434H, 1076 IA32_MC13_CTL
MC13_CTL If IA32_MCG_CAP.CNT >13
Register Address: 435H, 1077 IA32_MC13_STATUS
MC13_STATUS If IA32_MCG_CAP.CNT >13
Register Address: 436H, 1078 IA32_MC13_ADDR
1
MC13_ADDR If IA32_MCG_CAP.CNT >13
Register Address: 437H, 1079 IA32_MC13_MISC
MC13_MISC If IA32_MCG_CAP.CNT >13
Register Address: 438H, 1080 IA32_MC14_CTL
MC14_CTL If IA32_MCG_CAP.CNT >14
Register Address: 439H, 1081 IA32_MC14_STATUS
MC14_STATUS If IA32_MCG_CAP.CNT >14
Register Address: 43AH, 1082 IA32_MC14_ADDR
1
MC14_ADDR If IA32_MCG_CAP.CNT >14
Register Address: 43BH, 1083 IA32_MC14_MISC
MC14_MISC If IA32_MCG_CAP.CNT >14
Register Address: 43CH, 1084 IA32_MC15_CTL
MC15_CTL If IA32_MCG_CAP.CNT >15
Register Address: 43DH, 1085 IA32_MC15_STATUS
MC15_STATUS If IA32_MCG_CAP.CNT >15
Register Address: 43EH, 1086 IA32_MC15_ADDR
1
MC15_ADDR If IA32_MCG_CAP.CNT >15
Register Address: 43FH, 1087 IA32_MC15_MISC
MC15_MISC If IA32_MCG_CAP.CNT >15
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-37
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 440H, 1088 IA32_MC16_CTL
MC16_CTL If IA32_MCG_CAP.CNT >16
Register Address: 441H, 1089 IA32_MC16_STATUS
MC16_STATUS If IA32_MCG_CAP.CNT >16
Register Address: 442H, 1090 IA32_MC16_ADDR
1
MC16_ADDR If IA32_MCG_CAP.CNT >16
Register Address: 443H, 1091 IA32_MC16_MISC
MC16_MISC If IA32_MCG_CAP.CNT >16
Register Address: 444H, 1092 IA32_MC17_CTL
MC17_CTL If IA32_MCG_CAP.CNT >17
Register Address: 445H, 1093 IA32_MC17_STATUS
MC17_STATUS If IA32_MCG_CAP.CNT >17
Register Address: 446H, 1094 IA32_MC17_ADDR
1
MC17_ADDR If IA32_MCG_CAP.CNT >17
Register Address: 447H, 1095 IA32_MC17_MISC
MC17_MISC If IA32_MCG_CAP.CNT >17
Register Address: 448H, 1096 IA32_MC18_CTL
MC18_CTL If IA32_MCG_CAP.CNT >18
Register Address: 449H, 1097 IA32_MC18_STATUS
MC18_STATUS If IA32_MCG_CAP.CNT >18
Register Address: 44AH, 1098 IA32_MC18_ADDR
1
MC18_ADDR If IA32_MCG_CAP.CNT >18
Register Address: 44BH, 1099 IA32_MC18_MISC
MC18_MISC If IA32_MCG_CAP.CNT >18
Register Address: 44CH, 1100 IA32_MC19_CTL
MC19_CTL If IA32_MCG_CAP.CNT >19
Register Address: 44DH, 1101 IA32_MC19_STATUS
MC19_STATUS If IA32_MCG_CAP.CNT >19
Register Address: 44EH, 1102 IA32_MC19_ADDR
1
MC19_ADDR If IA32_MCG_CAP.CNT >19
Register Address: 44FH, 1103 IA32_MC19_MISC
MC19_MISC If IA32_MCG_CAP.CNT >19
Register Address: 450H, 1104 IA32_MC20_CTL
MC20_CTL If IA32_MCG_CAP.CNT >20
Register Address: 451H, 1105 IA32_MC20_STATUS
MC20_STATUS If IA32_MCG_CAP.CNT >20
Register Address: 452H, 11061106 IA32_MC20_ADDR
1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-38 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MC20_ADDR If IA32_MCG_CAP.CNT >20
Register Address: 453H, 1107 IA32_MC20_MISC
MC20_MISC If IA32_MCG_CAP.CNT >20
Register Address: 454H, 1108 IA32_MC21_CTL
MC21_CTL If IA32_MCG_CAP.CNT >21
Register Address: 455H, 1109 IA32_MC21_STATUS
MC21_STATUS If IA32_MCG_CAP.CNT >21
Register Address: 456H, 1110 IA32_MC21_ADDR
1
MC21_ADDR If IA32_MCG_CAP.CNT >21
Register Address: 457H, 1111 IA32_MC21_MISC
MC21_MISC If IA32_MCG_CAP.CNT >21
Register Address: 458H, 1112 IA32_MC22_CTL
MC22_CTL If IA32_MCG_CAP.CNT >22
Register Address: 459H, 1113 IA32_MC22_STATUS
MC22_STATUS If IA32_MCG_CAP.CNT >22
Register Address: 45AH, 1114 IA32_MC22_ADDR
1
MC22_ADDR If IA32_MCG_CAP.CNT >22
Register Address: 45BH, 1115 IA32_MC22_MISC
MC22_MISC If IA32_MCG_CAP.CNT >22
Register Address: 45CH, 1116 IA32_MC23_CTL
MC23_CTL If IA32_MCG_CAP.CNT >23
Register Address: 45DH, 1117 IA32_MC23_STATUS
MC23_STATUS If IA32_MCG_CAP.CNT >23
Register Address: 45EH, 1118 IA32_MC23_ADDR
1
MC23_ADDR If IA32_MCG_CAP.CNT >23
Register Address: 45FH, 1119 IA32_MC23_MISC
MC23_MISC If IA32_MCG_CAP.CNT >23
Register Address: 460H, 1120 IA32_MC24_CTL
MC24_CTL If IA32_MCG_CAP.CNT >24
Register Address: 461H, 1121 IA32_MC24_STATUS
MC24_STATUS If IA32_MCG_CAP.CNT >24
Register Address: 462H, 1122 IA32_MC24_ADDR
1
MC24_ADDR If IA32_MCG_CAP.CNT >24
Register Address: 463H, 1123 IA32_MC24_MISC
MC24_MISC If IA32_MCG_CAP.CNT >24
Register Address: 464H, 1124 IA32_MC25_CTL
MC25_CTL If IA32_MCG_CAP.CNT >25
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-39
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 465H, 1125 IA32_MC25_STATUS
MC25_STATUS If IA32_MCG_CAP.CNT >25
Register Address: 466H, 1126 IA32_MC25_ADDR
1
MC25_ADDR If IA32_MCG_CAP.CNT >25
Register Address: 467H, 1127 IA32_MC25_MISC
MC25_MISC If IA32_MCG_CAP.CNT >25
Register Address: 468H, 1128 IA32_MC26_CTL
MC26_CTL If IA32_MCG_CAP.CNT >26
Register Address: 469H, 1129 IA32_MC26_STATUS
MC26_STATUS If IA32_MCG_CAP.CNT >26
Register Address: 46AH, 1130 IA32_MC26_ADDR
1
MC26_ADDR If IA32_MCG_CAP.CNT >26
Register Address: 46BH, 1131 IA32_MC26_MISC
MC26_MISC If IA32_MCG_CAP.CNT >26
Register Address: 46CH, 1132 IA32_MC27_CTL
MC27_CTL If IA32_MCG_CAP.CNT >27
Register Address: 46DH, 1133 IA32_MC27_STATUS
MC27_STATUS If IA32_MCG_CAP.CNT >27
Register Address: 46EH, 1134 IA32_MC27_ADDR
1
MC27_ADDR If IA32_MCG_CAP.CNT >27
Register Address: 46FH, 1135 IA32_MC27_MISC
MC27_MISC If IA32_MCG_CAP.CNT >27
Register Address: 470H, 1136 IA32_MC28_CTL
MC28_CTL If IA32_MCG_CAP.CNT >28
Register Address: 471H, 1137 IA32_MC28_STATUS
MC28_STATUS If IA32_MCG_CAP.CNT >28
Register Address: 472H, 1138 IA32_MC28_ADDR
1
MC28_ADDR If IA32_MCG_CAP.CNT >28
Register Address: 473H, 1139 IA32_MC28_MISC
MC28_MISC If IA32_MCG_CAP.CNT >28
Register Address: 474H, 1140 IA32_MC29_CTL
MC29_CTL If IA32_MCG_CAP.CNT >29
Register Address: 475H, 1141 IA32_MC29_STATUS
MC29_STATUS If IA32_MCG_CAP.CNT >29
Register Address: 476H, 1142 IA32_MC29_ADDR
MC29_ADDR If IA32_MCG_CAP.CNT >29
Register Address: 477H, 1143 IA32_MC29_MISC
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-40 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MC29_MISC If IA32_MCG_CAP.CNT >29
Register Address: 478H, 1144 IA32_MC30_CTL
MC30_CTL If IA32_MCG_CAP.CNT >30
Register Address: 479H, 1145 IA32_MC30_STATUS
MC30_STATUS If IA32_MCG_CAP.CNT >30
Register Address: 47AH, 1146 IA32_MC30_ADDR
MC30_ADDR If IA32_MCG_CAP.CNT >30
Register Address: 47BH, 1147 IA32_MC30_MISC
MC30_MISC If IA32_MCG_CAP.CNT >30
Register Address: 47CH, 1148 IA32_MC31_CTL
MC31_CTL If IA32_MCG_CAP.CNT >31
Register Address: 47DH, 1149 IA32_MC31_STATUS
MC31_STATUS If IA32_MCG_CAP.CNT >31
Register Address: 47EH, 1150 IA32_MC31_ADDR
MC31_ADDR If IA32_MCG_CAP.CNT >31
Register Address: 47FH, 1151 IA32_MC31_MISC
MC31_MISC If IA32_MCG_CAP.CNT >31
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Appendix A.1, “Basic VMX Information.”
If CPUID.01H:ECX.[5] = 1
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Appendix A.3.1, “Pin-Based VM-Execution Controls.”
If CPUID.01H:ECX.[5] = 1
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3.2, “Primary Processor-Based VM-Execution Controls.”
If CPUID.01H:ECX.[5] = 1
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of Primary VM-Exit Controls (R/O)
See Appendix A.4.1, “Primary VM-Exit Controls.”
If CPUID.01H:ECX.[5] = 1
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls.”
If CPUID.01H:ECX.[5] = 1
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data.”
If CPUID.01H:ECX.[5] = 1
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0.”
If CPUID.01H:ECX.[5] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-41
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0.”
If CPUID.01H:ECX.[5] = 1
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4.”
If CPUID.01H:ECX.[5] = 1
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4.”
If CPUID.01H:ECX.[5] = 1
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration.”
If CPUID.01H:ECX.[5] = 1
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3.3, “Secondary Processor-Based VM-Execution Controls.”
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_PROCBASED_CTLS[63
])
Register Address: 48CH, 1164 IA32_VMX_EPT_VPID_CAP
Capability Reporting Register of EPT and VPID (R/O)
See Appendix A.10, “VPID and EPT Capabilities.”
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_PROCBASED_CTLS[63
] && (
IA32_VMX_PROCBASED_CTLS2[3
3] ||
IA32_VMX_PROCBASED_CTLS2[3
7]) )
Register Address: 48DH, 1165 IA32_VMX_TRUE_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)
See Appendix A.3.1, “Pin-Based VM-Execution Controls.”
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_BASIC[55] )
Register Address: 48EH, 1166 IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)
See Appendix A.3.2, “Primary Processor-Based VM-Execution Controls.”
If( CPUID.01H:ECX.[5] &&
IA32_VMX_BASIC[55] )
Register Address: 48FH, 1167 IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-Exit Flex Controls (R/O)
See Appendix A.4, “VM-Exit Controls.”
If( CPUID.01H:ECX.[5] &&
IA32_VMX_BASIC[55] )
Register Address: 490H, 1168 IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VM-Entry Flex Controls (R/O)
See Appendix A.5, “VM-Entry Controls.”
If( CPUID.01H:ECX.[5] &&
IA32_VMX_BASIC[55] )
Register Address: 491H, 1169 IA32_VMX_VMFUNC
Capability Reporting Register of VM-Function Controls (R/O) If( CPUID.01H:ECX.[5] &&
IA32_VMX_PROCBASED_CTLS[63
] &&
IA32_VMX_PROCBASED_CTLS2[4
5])
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-42 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 492H, 1170 IA32_VMX_PROCBASED_CTLS3
Capability Reporting Register of Tertiary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3.4, “Tertiary Processor-Based VM-Execution Controls.”
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_PROCBASED_CTLS[49
])
Register Address: 493H, 1171 IA32_VMX_EXIT_CTLS2
Capability Reporting Register of Secondary VM-Exit Controls (R/O)
See Appendix A.4.2, “Secondary VM-Exit Controls.”
If ( CPUID.01H:ECX.[5] &&
IA32_VMX_EXIT_CTLS[63])
Register Address: 4C1H, 1217 IA32_A_PMC0
Full Width Writable IA32_PMC0 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 0) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C2H, 1218 IA32_A_PMC1
Full Width Writable IA32_PMC1 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 1) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C3H, 1219 IA32_A_PMC2
Full Width Writable IA32_PMC2 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 2) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C4H, 1220 IA32_A_PMC3
Full Width Writable IA32_PMC3 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 3) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C5H, 1221 IA32_A_PMC4
Full Width Writable IA32_PMC4 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 4) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C6H, 1222 IA32_A_PMC5
Full Width Writable IA32_PMC5 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 5) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C7H, 1223 IA32_A_PMC6
Full Width Writable IA32_PMC6 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 6) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4C8H, 1224 IA32_A_PMC7
Full Width Writable IA32_PMC7 Alias (R/W) (If CPUID.0AH: EAX[15:8] > 7) &&
IA32_PERF_CAPABILITIES[13] = 1
Register Address: 4D0H, 1232 IA32_MCG_EXT_CTL
Allows software to signal some MCEs to only a single logical processor in the system. (R/W)
See Section 16.3.1.4, “IA32_MCG_EXT_CTL MSR.”
If IA32_MCG_CAP.LMCE_P =1
0LMCE_EN
63:1 Reserved.
Register Address: 500H, 1280 IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support for ACM (R/O) If CPUID.(EAX=07H, ECX=0H):
EBX[2] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-43
MODEL-SPECIFIC REGISTERS (MSRS)
0 Lock. See Section 39.11.3, “Interactions
with Authenticated Code Modules
(ACMs).”
15:1 Reserved.
23:16 SGX_SVN_SINIT See Section 39.11.3, “Interactions
with Authenticated Code Modules
(ACMs).”
63:24 Reserved.
Register Address: 560H, 1376 IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W) If ((CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) && (
(CPUID.(EAX=14H,ECX=0):ECX[0]
= 1) ||
(CPUID.(EAX=14H,ECX=0):ECX[2]
= 1) ) )
6:0 Reserved.
MAXPHYADDR
4
-1:7 Base physical address.
63:MAXPHYADDR Reserved.
Register Address: 561H, 1377 IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W) If ((CPUID.(EAX=07H,
ECX=0):EBX[25] = 1) && (
(CPUID.(EAX=14H,ECX=0):ECX[0]
= 1) ||
(CPUID.(EAX=14H,ECX=0):ECX[2]
= 1) ) )
6:0 Reserved.
31:7 MaskOrTableOffset.
63:32 Output Offset.
Register Address: 570H, 1392 IA32_RTIT_CTL
Trace Control Register (R/W) If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1)
0 TraceEn
1 CYCEn If (CPUID.(EAX=07H,
ECX=0):EBX[1] = 1)
2OS
3User
4 PwrEvtEn If (CPUID.(EAX=07H,
ECX=1):EBX[5] = 1)
5 FUPonPTW If (CPUID.(EAX=07H,
ECX=1):EBX[4] = 1)
6 FabricEn If (CPUID.(EAX=07H,
ECX=0):ECX[3] = 1)
7 CR3Filter If (CPUID.(EAX=14H,
ECX=0):EBX[0] = 1)
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-44 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
8ToPA
9 MTCEn If (CPUID.(EAX=07H,
ECX=0):EBX[3] = 1)
10 TSCEn
11 DisRETC
12 PTWEn If (CPUID.(EAX=07H,
ECX=1):EBX[4] = 1)
13 BranchEn
17:14 MTCFreq. If (CPUID.(EAX=07H,
ECX=0):EBX[3] = 1)
18 Reserved, must be zero.
22:19 CycThresh If (CPUID.(EAX=07H,
ECX=0):EBX[1] = 1)
23 Reserved, must be zero.
27:24 PSBFreq If (CPUID.(EAX=07H,
ECX=0):EBX[1] = 1)
30:28 Reserved, must be zero.
31 EventEn If (CPUID.(EAX=14H,
ECX=0):EBX[7] = 1)
35:32 ADDR0_CFG If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 0)
39:36 ADDR1_CFG If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 1)
43:40 ADDR2_CFG If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 2)
47:44 ADDR3_CFG If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 3)
54:48 Reserved, must be zero.
55 DisTNT If (CPUID.(EAX=14H,
ECX=0):EBX[8] = 1)
56 InjectPsbPmiOnEnable If (CPUID.(EAX=07H,
ECX=1):EBX[6] = 1)
63:57 Reserved, must be zero.
Register Address: 571H, 1393 IA32_RTIT_STATUS
Tracing Status Register (R/W) If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1)
0 FilterEn (writes ignored). If (CPUID.(EAX=07H,
ECX=0):EBX[2] = 1)
1ContexEn (writes ignored).
2 TriggerEn (writes ignored).
3Reserved.
4 Error
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-45
MODEL-SPECIFIC REGISTERS (MSRS)
5Stopped
6 PendPSB If (CPUID.(EAX=07H,
ECX=0):EBX[6] = 1)
7 PendToPAPMI If (CPUID.(EAX=07H,
ECX=0):EBX[6] = 1)
31:8 Reserved, must be zero.
48:32 PacketByteCnt If (CPUID.(EAX=07H,
ECX=0):EBX[1] > 3)
63:49 Reserved.
Register Address: 572H, 1394 IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W) If (CPUID.(EAX=07H,
ECX=0):EBX[25] = 1)
4:0 Reserved.
63:5 CR3[63:5] value to match.
Register Address: 580H, 1408 IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 0)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 581H, 1409 IA32_RTIT_ADDR0_B
Region 0 End Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 0)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 582H, 1410 IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 1)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 583H, 1411 IA32_RTIT_ADDR1_B
Region 1 End Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 1)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 584H, 1412 IA32_RTIT_ADDR2_A
Region 2 Start Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 2)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 585H, 1413 IA32_RTIT_ADDR2_B
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-46 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Region 2 End Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 2)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 586H, 1414 IA32_RTIT_ADDR3_A
Region 3 Start Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 3)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 587H, 1415 IA32_RTIT_ADDR3_B
Region 3 End Address (R/W) If (CPUID.(EAX=07H,
ECX=1):EAX[2:0] > 3)
47:0 Virtual Address.
63:48 SignExt_VA
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
Points to the linear address of the first byte of the DS buffer management area, which is used to
manage the BTS and PEBS buffers.
See Section 20.6.3.4, “Debug Store (DS) Mechanism.”
If( CPUID.01H:EDX.DS[21] = 1
63:0 The linear address of the first byte of the DS buffer management area, if
IA-32e mode is active.
31:0 The linear address of the first byte of the DS buffer management area, if
not in IA-32e mode.
63:32 Reserved if not in IA-32e mode.
Register Address: 6A0H, 1696 IA32_U_CET
Configure User Mode CET (R/W) Bits 1:0 are defined if
CPUID.(EAX=07H,
ECX=0H):ECX.CET_SS[07] = 1.
Bits 5:2 and bits 63:10 are defined
if CPUID.(EAX=07H,
ECX=0H):EDX.CET_IBT[20] = 1.
0 SH_STK_EN: When set to 1, enable shadow stacks at CPL3.
1 WR_SHSTK_EN: When set to 1, enables the WRSSD/WRSSQ instructions.
2ENDBR_EN: When set to 1, enables indirect branch tracking.
3 LEG_IW_EN: Enable legacy compatibility treatment for indirect branch
tracking.
4 NO_TRACK_EN: When set to 1, enables use of no-track prefix for indirect
branch tracking.
5 SUPPRESS_DIS: When set to 1, disables suppression of CET indirect
branch tracking on legacy compatibility.
9:6 Reserved; must be zero.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-47
MODEL-SPECIFIC REGISTERS (MSRS)
10 SUPPRESS: When set to 1, indirect branch tracking is suppressed. This bit
can be written to 1 only if TRACKER is written as IDLE.
11 TRACKER: Value of the indirect branch tracking state machine. Values:
IDLE (0), WAIT_FOR_ENDBRANCH(1).
63:12 EB_LEG_BITMAP_BASE: Linear address bits 63:12 of a legacy code page
bitmap used for legacy compatibility when indirect branch tracking is
enabled.
If the processor does not support Intel 64 architecture, these fields have
only 32 bits; bits 63:32 of the MSRs are reserved. On processors that
support Intel 64 architecture this value cannot represent a non-canonical
address. In protected mode, only 31:0 are used.
Register Address: 6A2H, 1698 IA32_S_CET
Configure Supervisor Mode CET (R/W) See IA32_U_CET (6A0H) for
reference; similar format.
Register Address: 6A4H, 1700 IA32_PL0_SSP
Linear address to be loaded into SSP on transition to privilege level 0. (R/W)
If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32
of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot
represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR
must be 0. Transitions to privilege level 0 will check that bit 2 is also 0.
If CPUID.(EAX=07H,
ECX=0H):ECX.CET_SS[07] = 1
Register Address: 6A5H, 1701 IA32_PL1_SSP
Linear address to be loaded into SSP on transition to privilege level 1. (R/W)
If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32
of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot
represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR
must be 0. Transitions to privilege level 1 from a higher privilege level will check that bit 2 is also
0.
If CPUID.(EAX=07H,
ECX=0H):ECX.CET_SS[07] = 1
Register Address: 6A6H, 1702 IA32_PL2_SSP
Linear address to be loaded into SSP on transition to privilege level 2. (R/W)
If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32
of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot
represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR
must be 0. Transitions to privilege level 2 from a higher privilege level will check that bit 2 is also
0.
If CPUID.(EAX=07H,
ECX=0H):ECX.CET_SS[07] = 1
Register Address: 6A7H, 1703 IA32_PL3_SSP
Linear address to be loaded into SSP on transition to privilege level 3. (R/W)
If the processor does not support Intel 64 architecture, these fields have only 32 bits; bits 63:32
of the MSRs are reserved. On processors that support Intel 64 architecture this value cannot
represent a non-canonical address. In protected mode, only 31:0 are loaded. Bits 1:0 of the MSR
must be 0.
If CPUID.(EAX=07H,
ECX=0H):ECX.CET_SS[07] = 1
Register Address: 6A8H, 1704 IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using
the IST index (when not 0) from the interrupt gate descriptor. (R/W)
This MSR is not present on processors that do not support Intel 64 architecture. This field cannot
represent a non-canonical address.
If CPUID.(EAX=07H,
ECX=0H):ECX.CET_SS[07] = 1
Register Address: 6E0H, 1760 IA32_TSC_DEADLINE
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-48 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
TSC Target of Local APIC’s TSC Deadline Mode (R/W) If CPUID.01H:ECX.[24] = 1
Register Address: 6E1H, 1761 IA32_PKRS
Specifies the PK permissions associated with each protection domain for supervisor pages (R/W) If CPUID.(EAX=07H,
ECX=0H):ECX.PKS [31] = 1
31:0 For domain i (i between 0 and 15), bits 2i and 2i+1 contain the AD and
WD permissions, respectively.
63:32 Reserved.
Register Address: 770H, 1904 IA32_PM_ENABLE
Enable/disable HWP (R/W) If CPUID.06H:EAX.[7] = 1
0HWP_ENABLE (R/W)
Note this bit can only be enabled once from the default value. Once set,
writes to the HWP_ENABLE bit are ignored. Only RESET will clear this bit.
Default = 0. See Section 15.4.2, “Enabling HWP.”
If CPUID.06H:EAX.[7] = 1
63:1 Reserved.
Register Address: 771H, 1905 IA32_HWP_CAPABILITIES
HWP Performance Range Enumeration (R/O) If CPUID.06H:EAX.[7] = 1
7:0 Highest_Performance
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.”
If CPUID.06H:EAX.[7] = 1
15:8 Guaranteed_Performance
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.”
If CPUID.06H:EAX.[7] = 1
23:16 Most_Efficient_Performance
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities”.
If CPUID.06H:EAX.[7] = 1
31:24 Lowest_Performance
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.”
If CPUID.06H:EAX.[7] = 1
63:32 Reserved.
Register Address: 772H, 1906 IA32_HWP_REQUEST_PKG
Power Management Control Hints for All Logical Processors in a Package (R/W) If CPUID.06H:EAX.[11] = 1
7:0 Minimum_Performance
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[11] = 1
15:8 Maximum_Performance
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[11] = 1
23:16 Desired_Performance
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[11] = 1
31:24 Energy_Performance_Preference
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[11] = 1 &&
CPUID.06H:EAX.[10] = 1
41:32 Activity_Window
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[11] = 1 &&
CPUID.06H:EAX.[9] = 1
63:42 Reserved.
Register Address: 773H, 1907 IA32_HWP_INTERRUPT
Control HWP Native Interrupts (R/W) If CPUID.06H:EAX.[8] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-49
MODEL-SPECIFIC REGISTERS (MSRS)
0 EN_Guaranteed_Performance_Change
See Section 15.4.6, “HWP Notifications.”
If CPUID.06H:EAX.[8] = 1
1EN_Excursion_Minimum
See Section 15.4.6, “HWP Notifications.”
If CPUID.06H:EAX.[8] = 1
63:2 Reserved.
Register Address: 774H, 1908 IA32_HWP_REQUEST
Power Management Control Hints to a Logical Processor (R/W) If CPUID.06H:EAX.[7] = 1
7:0 Minimum_Performance
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[7] = 1
15:8 Maximum_Performance
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[7] = 1
23:16 Desired_Performance
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[7] = 1
31:24 Energy_Performance_Preference
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[7] = 1 &&
CPUID.06H:EAX.[10] = 1
41:32 Activity_Window
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[7] = 1 &&
CPUID.06H:EAX.[9] = 1
42 Package_Control
See Section 15.4.4, “Managing HWP.”
If CPUID.06H:EAX.[7] = 1 &&
CPUID.06H:EAX.[11] = 1
63:43 Reserved.
Register Address: 775H, 1909 IA32_PECI_HWP_REQUEST_INFO
IA32_PECI_HWP_REQUEST_INFO
7:0 Minimum Performance (MINIMUM_PERFORMANCE): Used by OS to read
the latest value of PECI minimum performance input. Default value is 0.
15:8 Maximum Performance (MAXIMUM_PERFORMANCE): Used by OS to read
the latest value of PECI maximum performance input. Default value is 0.
23:16 Reserved.
31:24 Energy Performance Preference
(ENERGY_PERFORMANCE_PREFERENCE): Used by OS to read the latest
value of PECI Energy Performance Preference input. Default value is 0.
59:32 Reserved.
60 EPP PECI Override (EPP_PECI_OVERRIDE):
Indicates whether PECI is currently overriding the Energy Performance
Preference input. If set to ‘1’, PECI is overriding the Energy Performance
Preference input. If clear (0), OS has control over Energy Performance
Preference input. Default value is 0.
61 Reserved.
62 Max PECI Override (MAX_PECI_OVERRIDE):
Indicates whether PECI is currently overriding the Maximum
Performance input. If set to ‘1’, PECI is overriding the Maximum
Performance input. If clear (0), OS has control over Maximum
Performance input. Default value is 0.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-50 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63 Min PECI Override (MIN_PECI_OVERRIDE):
Indicates whether PECI is currently overriding the Minimum Performance
input. If set to ‘1’, PECI is overriding the Minimum Performance input. If
clear (0), OS has control over Minimum Performance input. Default value
is 0.
Register Address: 776H, 1910 IA32_HWP_CTL
IA32_HWP_CTL If CPUID.06H:EAX.[22] = 1
0 PKG_CTL_POLARITY
Defines which HWP Request MSR is used whether Thread level or
package level. When package MSR is used, the thread MSR valid bits
define which thread MSR fields override the package.
Default value is 0.
If CPUID.06H:EAX.[22] = 1
63:1 Reserved.
Register Address: 777H, 1911 IA32_HWP_STATUS
Log bits indicating changes to Guaranteed & excursions to Minimum (R/W) If CPUID.06H:EAX.[7] = 1
0 Guaranteed_Performance_Change (R/WC0)
See Section 15.4.5, “HWP Feedback.”
If CPUID.06H:EAX.[7] = 1
1Reserved.
2 Excursion_To_Minimum (R/WC0)
See Section 15.4.5, “HWP Feedback.”
If CPUID.06H:EAX.[7] = 1
63:3 Reserved.
Register Address: 802H, 2050 IA32_X2APIC_APICID
x2APIC ID Register (R/O) If CPUID.01H:ECX[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 803H, 2051 IA32_X2APIC_VERSION
x2APIC Version Register (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 808H, 2056 IA32_X2APIC_TPR
x2APIC Task Priority Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 80AH, 2058 IA32_X2APIC_PPR
x2APIC Processor Priority Register (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 80BH, 2059 IA32_X2APIC_EOI
x2APIC EOI Register (W/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 80DH, 2061 IA32_X2APIC_LDR
x2APIC Logical Destination Register (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 80FH, 2063 IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-51
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 810H, 2064 IA32_X2APIC_ISR0
x2APIC In-Service Register Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 811H, 2065 IA32_X2APIC_ISR1
x2APIC In-Service Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 812H, 2066 IA32_X2APIC_ISR2
x2APIC In-Service Register Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 813H, 2067 IA32_X2APIC_ISR3
x2APIC In-Service Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 814H, 2068 IA32_X2APIC_ISR4
x2APIC In-Service Register Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 815H, 2069 IA32_X2APIC_ISR5
x2APIC In-Service Register Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 816H, 2070 IA32_X2APIC_ISR6
x2APIC In-Service Register Bits 223:192 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 817H, 2071 IA32_X2APIC_ISR7
x2APIC In-Service Register Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 818H, 2072 IA32_X2APIC_TMR0
x2APIC Trigger Mode Register Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 819H, 2073 IA32_X2APIC_TMR1
x2APIC Trigger Mode Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 81AH, 2074 IA32_X2APIC_TMR2
x2APIC Trigger Mode Register Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 81BH, 2075 IA32_X2APIC_TMR3
x2APIC Trigger Mode Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 81CH, 2076 IA32_X2APIC_TMR4
x2APIC Trigger Mode Register Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 81DH, 2077 IA32_X2APIC_TMR5
x2APIC Trigger Mode Register Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-52 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 81EH, 2078 IA32_X2APIC_TMR6
x2APIC Trigger Mode Register Bits 223:192 (R/O) If ( CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1)
Register Address: 81FH, 2079 IA32_X2APIC_TMR7
x2APIC Trigger Mode Register Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 820H, 2080 IA32_X2APIC_IRR0
x2APIC Interrupt Request Register Bits 31:0 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 821H, 2081 IA32_X2APIC_IRR1
x2APIC Interrupt Request Register Bits 63:32 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 822H, 2082 IA32_X2APIC_IRR2
x2APIC Interrupt Request Register Bits 95:64 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 823H, 2083 IA32_X2APIC_IRR3
x2APIC Interrupt Request Register Bits 127:96 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 824H, 2084 IA32_X2APIC_IRR4
x2APIC Interrupt Request Register Bits 159:128 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 825H, 2085 IA32_X2APIC_IRR5
x2APIC Interrupt Request Register Bits 191:160 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 826H, 2086 IA32_X2APIC_IRR6
x2APIC Interrupt Request Register Bits 223:192 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 827H, 2087 IA32_X2APIC_IRR7
x2APIC Interrupt Request Register Bits 255:224 (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 828H, 2088 IA32_X2APIC_ESR
x2APIC Error Status Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 82FH, 2095 IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 830H, 2096 IA32_X2APIC_ICR
x2APIC Interrupt Command Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 832H, 2098 IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-53
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 833H, 2099 IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 834H, 2100 IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor Interrupt Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 835H, 2101 IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 836H, 2102 IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 837H, 2103 IA32_X2APIC_LVT_ERROR
x2APIC LVT Error Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 838H, 2104 IA32_X2APIC_INIT_COUNT
x2APIC Initial Count Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 839H, 2105 IA32_X2APIC_CUR_COUNT
x2APIC Current Count Register (R/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 83EH, 2110 IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration Register (R/W) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 83FH, 2111 IA32_X2APIC_SELF_IPI
x2APIC Self IPI Register (W/O) If CPUID.01H:ECX.[21] = 1 &&
IA32_APIC_BASE.[10] = 1
Register Address: 981H, 2433 IA32_TME_CAPABILITY
Memory Encryption Capability MSR If CPUID.07H:ECX.[13] = 1
0 Support for AES-XTS 128-bit encryption algorithm.
(NIST standard)
1 Support for AES-XTS 128-bit encryption with integrity algorithm.
2 Support for AES-XTS 256-bit encryption algorithm.
29:3 Reserved.
30 SUPPORT_IA32_TME_CLEAR_SAVED_KEY
Support for the IA32_TME_CLEAR_SAVED_KEY MSR.
31 TME encryption bypass supported.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-54 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
35:32 MK_TME_MAX_KEYID_BITS
Number of bits which can be allocated for usage as key identifiers for
multi-key memory encryption.
4 bits allow for a maximum value of 15, which could address 32K keys.
Zero if TME-MK is not supported.
50:36 MK_TME_MAX_KEYS
Indicates the maximum number of keys which are available for usage.
This value may not be a power of 2.
KeyID 0 is specially reserved and is not accounted for in this field.
63:51 Reserved.
Register Address: 982H, 2434 IA32_TME_ACTIVATE
Memory Encryption Activation MSR
This MSR is used to lock the MSRs listed below. Any write to the following MSRs will be ignored
after they are locked. The lock is reset when CPU is reset.
• IA32_TME_ACTIVATE
• IA32_TME_EXCLUDE_MASK
• IA32_TME_EXCLUDE_BASE
Note that IA32_TME_EXCLUDE_MASK and IA32_TME_EXCLUDE_BASE must be configured before
IA32_TME_ACTIVATE.
If CPUID.07H:ECX.[13] = 1
0 Lock R/O – Will be set upon successful WRMSR (or first SMI); written
value ignored.
1 Hardware Encryption Enable
This bit also enables TME-MK; TME-MK cannot be enabled without
enabling encryption hardware.
2Key Select
0: Create a new TME key (expected cold/warm boot).
1: Restore the TME key from storage (Expected when resume from
standby).
3 Save TME Key for Standby
Save key into storage to be used when resume from standby.
Note: This may not be supported in all processors.
7:4 TME Policy/Encryption Algorithm
Only algorithms enumerated in IA32_TME_CAPABILITY are allowed.
For example:
0000 – AES-XTS-128.
0001 – AES-XTS-128 with integrity.
0010 – AES-XTS-256.
Other values are invalid.
30:8 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-55
MODEL-SPECIFIC REGISTERS (MSRS)
31 TME Encryption Bypass Enable
When encryption hardware is enabled:
• Total Memory Encryption is enabled using a CPU generated ephemeral
key based on a hardware random number generator when this bit is
set to 0.
• Total Memory Encryption is bypassed (no encryption/decryption for
KeyID0) when this bit is set to 1.
Software must inspect Hardware Encryption Enable (bit 1) and TME
encryption bypass Enable (bit 31) to determine if TME encryption is
enabled.
35:32 MK_TME_KEYID_BITS
Reserved if TME-MK is not enumerated, otherwise:
The number of key identifier bits to allocate to TME-MK usage. Similar to
enumeration, this is an encoded value.
Writing a value greater than MK_TME_MAX_KEYID_BITS will result in
#GP.
Writing a non-zero value to this field will #GP if bit 1 of EAX (Hardware
Encryption Enable) is not also set to ‘1, as encryption hardware must be
enabled to use TME-MK.
Example: To support 255 keys, this field would be set to a value of 8.
47:36 Reserved.
63:48 MK_TME_CRYPTO_ALGS
Reserved if TME-MK is not enumerated, otherwise:
Bit 48: AES-XTS 128.
Bit 49: AES-XTS 128 with integrity.
Bit 50: AES-XTS 256.
Bit 63:51: Reserved (#GP)
Bitmask for BIOS to set which encryption algorithms are allowed for
TME-MK, would be later enforced by the key loading ISA (‘1 = allowed).
Register Address: 983H, 2435 IA32_TME_EXCLUDE_MASK
Memory Encryption Exclude Mask If CPUID.07H:ECX.[13] = 1
10:0 Reserved.
11 Enable: When set to ‘1’, then TME_EXCLUDE_BASE and
TME_EXCLUDE_MASK are used to define an exclusion region for
TME/TME-MK (for KeyID=0).
MAXPHYADDR-1:12 TMEEMASK: This field indicates the bits that must match TMEEBASE in
order to qualify as a TME/TME-MK (for KeyID=0) exclusion memory range
access.
63:MAXPHYADDR Reserved; must be zero.
Register Address: 984H, 2436 IA32_TME_EXCLUDE_BASE
Memory Encryption Exclude Base IF CPUID.07H:ECX.[13] = 1
11:0 Reserved.
MAXPHYADDR-1:12 TMEEBASE: Base physical address to be excluded for TME/TME-MK (for
KeyID=0) encryption.
63:MAXPHYADDR Reserved; must be zero.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-56 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 985H, 2437 IA32_UINTR_RR
User Interrupt Request Register (R/W) IF CPUID.07H.01H:EDX[13]=1
63:0 UIRR
Bitmap of requested user interrupt vectors.
Register Address: 986H, 2438 IA32_UINTR_HANDLER
User Interrupt Handler Address (R/W) IF CPUID.07H.01H:EDX[13]=1
63:0 UIHANDLER
User interrupt handler linear address.
Register Address: 987H, 2439 IA32_UINTR_STACKADJUST
User Interrupt Stack Adjustment (R/W) IF CPUID.07H.01H:EDX[13]=1
0LOAD_RSP
User interrupt stack mode.
2:1 Reserved.
63:3 STACK_ADJUST
Stack adjust value.
Register Address: 988H, 2440 IA32_UINTR_MISC
User-Interrupt Target-Table Size and Notification Vector (R/W) If CPUID.07H.01H:EDX[13]=1
31:0 UITTSZ
The highest index of a valid entry in the user-interrupt target table. Valid
entries are indices 0..UITTSZ (inclusive).
39:32 UINV
User-interrupt notification vector.
63:40 Reserved.
Register Address: 989H, 2441 IA32_UINTR_PD
User Interrupt PID Address (R/W) If CPUID.07H.01H:EDX[13]=1
5:0 Reserved.
63:6 UPIDADDR
User-interrupt notification processing accesses a UPID at this linear
address.
Register Address: 98AH, 2442 IA32_UINTR_TT
User-Interrupt Target Table (R/W) If CPUID.07H.01H:EDX[13]=1
0 SENDUIPI_ENABLE
User-interrupt target table is valid.
3:1 Reserved.
63:4 UITTADDR
User-interrupt target table base linear address.
Register Address: 990H, 2448 IA32_COPY_STATUS
5
Status of Most Recent Platform to Local or Local to Platform Copies (R/O) If ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(07H,0).ECX[23] = 1))
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-57
MODEL-SPECIFIC REGISTERS (MSRS)
0 IWKEY_COPY_SUCCESSFUL
Status of most recent copy to or from IWKeyBackup.
If ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(07H,0).ECX[23] = 1))
63:1 Reserved.
Register Address: 991H, 2449 IA32_IWKEYBACKUP_STATUS
5
Information about IWKeyBackup Register (R/O) If ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(07H,0).ECX[23] =1))
0Backup/Restore Valid
Cleared when a write to IWKeyBackup is initiated, and then set when the
latest write of IWKeyBackup has been written to storage that persists
across S3/S4 sleep state. If S3/S4 is entered between when an
IWKeyBackup write occurs and when this bit is set, then IWKeyBackup
may not be recovered after S3/S4 exit. During S3/S4 sleep state exit
(system wake up), this bit is cleared. It is set again when IWKeyBackup is
restored from persistent storage and thus available to be copied to
IWKey using IA32_COPY_PLATFORM_TO_LOCAL MSR. Another write to
IWKeyBackup (via IA32_COPY_LOCAL_TO_PLATFORM MSR) may fail if a
previous write has not yet set this bit.
IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(07H,0).ECX[23] =1))
1 Reserved.
2 Backup Key Storage Read/Write Error
Updated prior to backup/restore valid being set. Set when an error is
encountered while backing up or restoring a key to persistent storage.
IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(07H,0).ECX[23] =1))
3 IWKeyBackup Consumed
Set after the previous backup operation has been consumed by the
platform. This does not indicate that the system is ready for a second
IWKeyBackup write as the previous IWKeyBackup write may still need to
set Backup/restore valid.
IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(07H,0).ECX[23] =1))
63:4 Reserved.
Register Address: 9FBH, 2555 IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_SAVED_KEY (W/O)
0 TME_CLEAR_SAVED_KEY
Clear saved TME keys.
63:1 Reserved.
Register Address: C80H, 3200 IA32_DEBUG_INTERFACE
Silicon Debug Feature Control (R/W) If CPUID.01H:ECX.[11] = 1
0Enable (R/W)
BIOS set 1 to enable Silicon debug features. Default is 0.
If CPUID.01H:ECX.[11] = 1
29:1 Reserved.
30 Lock (R/W): If 1, locks any further change to the MSR. The lock bit is set
automatically on the first SMI assertion even if not explicitly set by BIOS.
Default is 0.
If CPUID.01H:ECX.[11] = 1
31 Debug Occurred (R/O): This “sticky bit” is set by hardware to indicate the
status of bit 0. Default is 0.
If CPUID.01H:ECX.[11] = 1
63:32 Reserved.
Register Address: C81H, 3201 IA32_L3_QOS_CFG
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-58 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
L3 QOS Configuration (R/W) If (CPUID.(EAX=10H,
ECX=1):ECX.[2] = 1)
0Enable (R/W)
Set 1 to enable L3 CAT masks and CLOS to operate in Code and Data
Prioritization (CDP) mode.
63:1 Reserved. Attempts to write to reserved bits result in a #GP(0).
Register Address: C82H, 3202 IA32_L2_QOS_CFG
L2 QOS Configuration (R/W) If (CPUID.(EAX=10H,
ECX=2):ECX.[2] = 1)
0Enable (R/W)
Set 1 to enable L2 CAT masks and CLOS to operate in Code and Data
Prioritization (CDP) mode.
63:1 Reserved. Attempts to write to reserved bits result in a #GP(0).
Register Address: C83H, 3203 IA32_L3_IO_QOS_CFG
L3 I/O QOS Configuration (R/W)
This MSR is used to enable the I/O RDT features.
If (CPUID.(EAX=0FH,
ECX=1):EAX.[10:9] = 1)
0 L3 I/O RDT Allocation Enable.
1 L3 I/O RDT Monitoring Enable.
63:2 Reserved.
Register Address: C8DH, 3213 IA32_QM_EVTSEL
Monitoring Event Select Register (R/W) If (CPUID.(EAX=07H,
ECX=0):EBX.[12] = 1)
7:0 Event ID: ID of a supported monitoring event to report via IA32_QM_CTR.
31: 8 Reserved.
N+31:32 Resource Monitoring ID: ID for monitoring hardware to report monitored
data via IA32_QM_CTR.
N = Ceil (Log
2
(CPUID.(EAX= 0FH,
ECX=0H).EBX[31:0] +1))
63:N+32 Reserved.
Register Address: C8EH, 3214 IA32_QM_CTR
Monitoring Counter Register (R/O) If (CPUID.(EAX=07H,
ECX=0):EBX.[12] = 1)
61:0 Resource Monitored Data.
62 Unavailable: If 1, indicates data for this RMID is not available or not
monitored for this resource or RMID.
63 Error: If 1, indicates an unsupported RMID or event type was written to
IA32_PQR_QM_EVTSEL.
Register Address: C8FH, 3215 IA32_PQR_ASSOC
Resource Association Register (R/W) If ((CPUID.(EAX=07H,
ECX=0):EBX[12] =1) or
(CPUID.(EAX=07H,
ECX=0):EBX[15] =1))
N-1:0 Resource Monitoring ID (R/W): ID for monitoring hardware to track
internal operation, e.g., memory access.
N = Ceil (Log
2
(CPUID.(EAX= 0FH,
ECX=0H).EBX[31:0] +1))
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-59
MODEL-SPECIFIC REGISTERS (MSRS)
31:N Reserved.
63:32 CLOS (R/W): The class of service (CLOS) to enforce (on writes); returns
the current CLOS when read.
If ( CPUID.(EAX=07H,
ECX=0):EBX.[15] = 1 )
Register Address: C90H−D8FH, 3216−3471 Reserved MSR Address Space for CAT Mask Registers
See Section 18.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology.”
Register Address: C90H, 3216 IA32_L3_MASK_0
L3 CAT Mask for COS0 (R/W) If (CPUID.(EAX=10H,
ECX=0H):EBX[1] != 0)
31:0 Capacity Bit Mask (R/W)
63:32 Reserved.
Register Address: C90H+n, 3216+n IA32_L3_MASK_n
L3 CAT Mask for COSn (R/W) n = CPUID.(EAX=10H,
ECX=1H):EDX[15:0]
31:0 Capacity Bit Mask (R/W)
63:32 Reserved.
Register Address: D10H−D4FH, 3344−3407 Reserved MSR Address Space for L2 CAT Mask Registers
See Section 18.19.4.1, “Enumeration and Detection Support of Cache Allocation Technology.”
Register Address: D10H, 3344 IA32_L2_MASK_0
L2 CAT Mask for COS0 (R/W) If (CPUID.(EAX=10H,
ECX=0H):EBX[2] != 0)
31:0 Capacity Bit Mask (R/W)
63:32 Reserved.
Register Address: D10H+n, 3344+n IA32_L2_MASK_n
L2 CAT Mask for COSn (R/W) n = CPUID.(EAX=10H,
ECX=2H):EDX[15:0]
31:0 Capacity Bit Mask (R/W)
63:32 Reserved.
Register Address: D90H, 3472 IA32_BNDCFGS
Supervisor State of MPX Configuration (R/W) If (CPUID.(EAX=07H,
ECX=0H):EBX[14] = 1)
0 EN: Enable Intel MPX in supervisor mode.
1 BNDPRESERVE: Preserve the bounds registers for near branch
instructions in the absence of the BND prefix.
11:2 Reserved, must be zero.
63:12 Base Address of Bound Directory.
Register Address: D91H, 3473 IA32_COPY_LOCAL_TO_PLATFORM
5
Copy Local State to Platform State (W) IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-60 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
0IWKeyBackup
Copy IWKey to IWKeyBackup.
IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
63:1 Reserved.
Register Address: D92H, 3474 IA32_COPY_PLATFORM_TO_LOCAL
5
Copy Platform State to Local State (W) IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
0IWKeyBackup
Copy IWKeyBackup to IWKey.
IF ((CPUID.19H:EBX[4] = 1) &&
(CPUID.(EAX=07H,
ECX=0H).ECX[23] = 1))
63:1 Reserved.
Register Address: D93H, 3475 IA32_PASID
Process Address Space Identifier. (R/W)
19:0 Process address space identifier (PASID). Specifies the PASID of the
currently running software thread.
30:20 Reserved.
31 Valid. Execution of ENQCMD causes a #GP if this bit is clear.
63:32 Reserved.
Register Address: DA0H, 3488 IA32_XSS
Extended Supervisor State Mask (R/W) If( CPUID.(0DH, 1):EAX.[3] = 1
7:0 Reserved.
8PT State (R/W)
9Reserved.
10 PASID State (R/W)
11 CET_U State (R/W)
12 CET_S State (R/W)
13 HDC State (R/W)
14 UINTR State (R/W)
15 LBR State (R/W)
16 HWP State (R/W)
63:17 Reserved.
Register Address: DB0H, 3504 IA32_PKG_HDC_CTL
Package Level Enable/Disable HDC (R/W) If CPUID.06H:EAX.[13] = 1
0 HDC_Pkg_Enable (R/W)
Force HDC idling or wake up HDC-idled logical processors in the package.
See Section 15.5.2, “Package level Enabling HDC.”
If CPUID.06H:EAX.[13] = 1
63:1 Reserved.
Register Address: DB1H, 3505 IA32_PM_CTL1
Enable/Disable the HDC Thread Level Activity (R/W) If CPUID.06H:EAX.[13] = 1
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-61
MODEL-SPECIFIC REGISTERS (MSRS)
0SDC_ALLOWED (R/W)
Set this bit to allow this thread to be forced into HDC idle state. Clearing
this bit blocks HDC-enter (HW) request. Default value: 1. See Section
15.5.3.
If CPUID.06H:EAX.[13] = 1
63:1 Reserved.
Register Address: DB2H, 3506 IA32_THREAD_STALL
Per-Logical_Processor_ID HDC Idle Residency (R/0) If CPUID.06H:EAX.[13] = 1
63:0 Stall_Cycle_Cnt (R/W)
Stalled cycles due to HDC forced idle on this logical processor. See
Section 15.5.4.1.
If CPUID.06H:EAX.[13] = 1
Register Address: 1200H−121FH, 4608−4639 IA32_LBR_x_INFO
Last Branch Record Entry X Info Register (R/W)
An attempt to read or write IA32_LBR_x_INFO such that x
≥ IA32_LBR_DEPTH.DEPTH will #GP.
15:0 CYC_CNT
The elapsed CPU cycles (saturating) since the last LBR was recorded. See
Section 18.1.3.3.
Reset Value: 0
55:16 Undefined, may be zero or non-zero. Writes of non- zero values do not
fault, but reads may return a different value.
Reset Value: 0
59:56 BR_TYPE
The branch type recorded by this LBR. Encodings:
0000B: COND
0001B: JMP Indirect
0010B: JMP Direct
0011B: CALL Indirect
0100B: CALL Direct
0101B: RET
011xB: Reserved
1xxxB: Other Branch
Reset Value: 0
60 CYC_CNT_VALID
CYC_CNT value is valid. See Section 19.1.3.3.
Reset Value: 0
61 TSX_ABORT
This LBR record is a TSX abort. On processors that do not support Intel
TSX (CPUID.07H.EBX.HLE[bit 4]=0 and CPUID.07H.EBX.RTM[bit 11]=0),
this bit is undefined.
Reset Value: 0
62 IN_TSX
This LBR record records a branch that retired during a TSX transaction.
On processors that do not support Intel TSX (CPUID.07H.EBX.HLE[bit
4]=0 and CPUID.07H.EBX.RTM[bit 11]=0), this bit is undefined.
Reset Value: 0
63 MISPRED
The recorded branch direction (conditional branch) or target (indirect
branch) was mispredicted.
Reset Value: 0
Register Address: 1406H, 5126 IA32_MCU_CONTROL
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-62 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
MCU Control (R/W)
Controls the behavior of the Microcode Update Trigger MSR, IA32_BIOS_UPDT_TRIG.
If CPUID.07H.0H:EDX[29]=1 &&
MSR.IA32_ARCH_CAPABILITIES.M
CU_CONTROL=1
0LOCK
Once set, further writes to this MSR will cause a #GP(0) fault. Bypassed
during SMM if EN_SMM_BYPASS (bit 2) is set.
1 DIS_MCU_LOAD
If this bit is set on a given logical processor, then any subsequent
attempts to load a microcode update by that logical processor will be
silently dropped (WRMSR 0x79 has no effect).
2 EN_SMM_BYPASS
If set, then writes to IA32_MCU_CONTROL are allowed during SMM
regardless of the LOCK bit. This enables BIOS to Opt-In to the SMM
Bypass functionality.
63:3 Reserved.
Register Address: 14CEH, 5326 IA32_LBR_CTL
Last Branch Record Enabling and Configuration Register (R/W)
0LBREn
When set, enables LBR recording.
Reset Value: 0
1OS
When set, allows LBR recording when CPL == 0.
Reset Value: 0
2USR
When set, allows LBR recording when CPL != 0.
Reset Value: 0
3 CALL_STACK
When set, records branches in call-stack mode. See Section 19.1.2.4.
Reset Value: 0
15:4 Reserved. Reset Value: 0
16 COND
When set, records taken conditional branches. See Section 19.1.2.3.
17 NEAR_REL_JMP
When set, records near relative JMPs. See Section 19.1.2.3.
18 NEAR_IND_JMP
When set, records near indirect JMPs. See Section 19.1.2.3.
19 NEAR_REL_CALL
When set, records near relative CALLs. See Section 19.1.2.3.
20 NEAR_IND_CALL
When set, records near indirect CALLs. See Section 19.1.2.3.
21 NEAR_RET
When set, records near RETs. See Section 19.1.2.3.
22 OTHER_BRANCH
When set, records other branches. See Section 19.1.2.3.
63:23 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-63
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 14CFH, 5327 IA32_LBR_DEPTH
Last Branch Record Maximum Stack Depth Register (R/W)
N:0 DEPTH
The number of LBRs to be used for recording. Supported values are
indicated by the bitmap in CPUID.(EAX=01CH,ECX=0):EAX[7:0]. The reset
value will match the maximum supported by the CPU. Writes of
unsupported values will #GP fault.
Reset Value: Varies
63:N+1 Reserved. Reset Value: 0
Register Address: 1500H−151FH, 5376−5407 IA32_LBR_x_FROM_IP
Last Branch Record entry X source IP register (R/W).
An attempt to read or write IA32_LBR_x_FROM_IP such that x
≥ IA32_LBR_DEPTH.DEPTH will
#GP.
63:0 FROM_IP
The source IP of the recorded branch or event, in canonical form. Writes
to bits above MAXLINADDR-1 are ignored.
Reset Value: 0
Register Address: 1600H−161FH, 5632−5663 IA32_LBR_x_TO_IP
Last Branch Record Entry X Destination IP Register (R/W)
An attempt to read or write IA32_LBR_x_TO_IP such that x
≥ IA32_LBR_DEPTH.DEPTH will #GP.
63:0 TO_IP
The destination IP of the recorded branch or event, in canonical form.
Writes to bits above MAXLINADDR-1 are ignored.
Reset Value: 0
Register Address: 17D0H, 6096 IA32_HW_FEEDBACK_PTR
Hardware Feedback Interface Pointer If CPUID.06H:EAX.[19] = 1
0Valid (R/W)
When set to 1, indicates a valid pointer is programmed into the ADDR
field of the MSR.
11:1 Reserved.
(MAXPHYADDR-1):12 ADDR (R/W)
Physical address of the page frame of the first page of the hardware
feedback interface structure.
63:MAXPHYADDR Reserved.
Register Address: 17D1H, 6097 IA32_HW_FEEDBACK_CONFIG
Hardware Feedback Interface Configuration If CPUID.06H:EAX.[19] = 1
0Enable (R/W)
When set to 1, enables the hardware feedback interface.
63:1 Reserved.
Register Address: 17D2H, 6098 IA32_THREAD_FEEDBACK_CHAR
Thread Feedback Characteristics (R/O) If CPUID.06H:EAX.[23] = 1
7:0 Application Class ID, pointing into the Intel Thread Director structure.
62:8 Reserved.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-64 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63 Valid bit. When set to 1 the OS Scheduler can use the Class ID (in bits 7:0)
for its scheduling decisions.
If this bit is 0, the Class ID field should be ignored. It is recommended that
the OS uses the last known Class ID of the software thread for its
scheduling decisions.
Register Address: 17D4H, 6100 IA32_HW_FEEDBACK_THREAD_CONFIG
Hardware Feedback Thread Configuration (R/W)
0 Enables Intel Thread Director. When set to 1, logical processor scope Intel
Thread Director is enabled. Default is 0 (disabled).
63:1 Reserved.
Register Address: 17DAH, 6106 IA32_HRESET_ENABLE
History Reset Enable (R/W)
0 Enable reset of the Intel Thread Director history.
31:1 Reserved for other capabilities that can be reset by the HRESET
instruction.
63:32 Reserved.
Register Address: 1B01H, 6913 IA32_UARCH_MISC_CTL
IA32_UARCH_MISC_CTL If
IA32_ARCH_CAPABILITIES[12]=1
0 Data Operand Independent Timing Mode (DOITM). If
IA32_ARCH_CAPABILITIES[12]=1
63:1 Reserved.
Register Address: 4000_0000H−4000_00FFH Reserved MSR Address Space
All existing and future processors will not implement MSRs in this range.
Register Address: C000_0080H IA32_EFER
Extended Feature Enables If ( CPUID.80000001H:EDX.[20] ||
CPUID.80000001H:EDX.[29])
0 SYSCALL Enable: IA32_EFER.SCE (R/W)
Enables SYSCALL/SYSRET instructions in 64-bit mode.
7:1 Reserved.
8 IA-32e Mode Enable: IA32_EFER.LME (R/W)
Enables IA-32e mode operation.
9Reserved.
10 IA-32e Mode Active: IA32_EFER.LMA (R)
Indicates IA-32e mode is active when set.
11 Execute Disable Bit Enable: IA32_EFER.NXE (R/W)
63:12 Reserved.
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0082H IA32_LSTAR
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
Vol. 4 2-65
MODEL-SPECIFIC REGISTERS (MSRS)
2.2 MSRS IN THE INTEL® CORE™
2 PROCESSOR FAMILY
Table 2-3 lists model-specific registers (MSRs) for the Intel Core 2 processor family and for Intel Xeon processors
based on Intel Core microarchitecture, architectural MSR addresses are also included in Table 2-3. These proces-
sors have a CPUID Signature DisplayFamily_DisplayModel value of 06_0FH, see Table 2-1.
MSRs listed in Table 2-2 and Table 2-3 are also supported by processors based on the Enhanced Intel Core microar-
chitecture. Processors based on the Enhanced Intel Core microarchitecture have a CPUID Signature DisplayFami-
ly_DisplayModel value of 06_17H.
IA-32e Mode System Call Target Address (R/W)
Target RIP for the called procedure when SYSCALL is executed in 64-bit mode.
If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0083H IA32_CSTAR
IA-32e Mode System Call Target Address (R/W)
Not used, as the SYSCALL instruction is not recognized in compatibility mode.
If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W) If CPUID.80000001:EDX.[29] = 1
Register Address: C000_0103H IA32_TSC_AUX
Auxiliary TSC (R/W) If CPUID.80000001H: EDX[27] = 1
or CPUID.(EAX=7,ECX=0):ECX[bit
22] = 1
31:0 AUX: Auxiliary signature of TSC.
63:32 Reserved.
NOTES:
1. Some older processors may have supported this MSR as model-specific and do not enumerate it with CPUID.
2. In processors based on Intel NetBurst® microarchitecture, MSR addresses 180H-197H are supported, software must treat them as
model-specific. Starting with Intel Core Duo processors, MSR addresses 180H-185H, 188H-197H are reserved.
3. The *_ADDR MSRs may or may not be present; this depends on flag settings in IA32_MCi_STATUS. See Section 16.3.2.3 and Section
16.3.2.4 for more information.
4. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
5. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html
.
Table 2-2. IA-32 Architectural MSRs (Contd.)
Register Address: Hex, Decimal Architectural MSR Name (Former MSR Name)
Bit Fields MSR/Bit Description Comment
2-66 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
The column “Shared/Unique” applies to multi-core processors based on Intel Core microarchitecture. “Unique”
means each processor core has a separate MSR, or a bit field in an MSR governs only a core independently.
“Shared” means the MSR or the bit field in an MSR address governs the operation of both processor cores.
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Unique
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.” Unique
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Unique
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Unique
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
Shared
Register Address: 17H, 23 MSR_PLATFORM_ID
Model Specific Platform ID (R) Shared
7:0 Reserved.
12:8 Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
49:13 Reserved.
52:50 See Table 2-2.
63:53 Reserved.
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Unique
Register Address: 2AH, 42 MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current processor configuration.
Shared
0 Reserved.
1 Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processors implement R/W.
2 Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processor implements R/W.
3 MCERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processors implement R/W.
Vol. 4 2-67
MODEL-SPECIFIC REGISTERS (MSRS)
4 Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processors implement R/W.
5 Reserved.
6 Reserved.
7 BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processors implement R/W.
8 Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled.
9Execute BIST (R/O)
1 = Enabled; 0 = Disabled.
10 MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
11 Intel TXT Capable Chipset. (R/O)
1 = Present; 0 = Not Present.
12 BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
13 Reserved.
14 1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes.
15 Reserved.
17:16 APIC Cluster ID (R/O)
18 N/2 Non-Integer Bus Ratio (R/O)
0 = Integer ratio; 1 = Non-integer ratio.
19 Reserved.
21: 20 Symmetric Arbitration ID (R/O)
26:22 Integer Bus Frequency Ratio (R/O)
Register Address: 3AH, 58 MSR_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Unique
3SMRR Enable (R/WL)
When this bit is set and the lock bit is set, this makes the SMRR_PHYS_BASE
and SMRR_PHYS_MASK registers read visible and writeable while in SMM.
Unique
Register Address: 40H, 64 MSR_LASTBRANCH_0_FROM_IP
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-68 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 0 From IP (R/W)
One of four pairs of last branch record registers on the last branch record stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.5.
Unique
Register Address: 41H, 65 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 42H, 66 MSR_LASTBRANCH_2_FROM_IP
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 43H, 67 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 60H, 96 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of four pairs of last branch record registers on the last branch record stack. This To_IP part of the stack contains
pointers to the destination instruction.
Unique
Register Address: 61H, 97 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 62H, 98 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 63H, 99 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Unique
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Unique
Register Address: A0H, 160 MSR_SMRR_PHYSBASE
System Management Mode Base Address register (WO in SMM)
Model-specific implementation of SMRR-like interface, read visible and write only in SMM.
Unique
11:0 Reserved.
31:12 PhysBase: SMRR physical Base Address.
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-69
MODEL-SPECIFIC REGISTERS (MSRS)
63:32 Reserved.
Register Address: A1H, 161 MSR_SMRR_PHYSMASK
System Management Mode Physical Address Mask register (WO in SMM)
Model-specific implementation of SMRR-like interface, read visible and write only in SMM.
Unique
10:0 Reserved.
11 Valid: Physical address base and range mask are valid.
31:12 PhysMask: SMRR physical address range mask.
63:32 Reserved.
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
See Table 2-2.
Unique
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Unique
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed for processors based on Intel Core microarchitecture.
Shared
2:0 • 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
• 010B: 200 MHz (FSB 800)
• 000B: 267 MHz (FSB 1067)
• 100B: 333 MHz (FSB 1333)
133.33 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 000B.
333.33 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 100B.
63:3 Reserved.
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed for processors based on Enhanced Intel Core
microarchitecture.
Shared
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-70 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2:0 • 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
• 010B: 200 MHz (FSB 800)
• 000B: 267 MHz (FSB 1067)
• 100B: 333 MHz (FSB 1333)
• 110B: 400 MHz (FSB 1600)
133.33 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 110B.
333.33 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 111B.
63:3 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Unique
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Unique
Register Address: FEH, 254 IA32_MTRRCAP
See Table 2-2. Unique
11 SMRR Capability Using MSR 0A0H and 0A1H (R) Unique
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Unique
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Unique
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Unique
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Unique
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Unique
0RIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) can be
used to restart the program. If cleared, the program cannot be reliably
restarted.
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-71
MODEL-SPECIFIC REGISTERS (MSRS)
1EIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) is
directly associated with the error.
2MCIP
When set, bit indicates that a machine check has been generated. If a second
machine check is detected while this bit is still set, the processor enters a
shutdown state. Software should write this bit to 0 after processing a
machine check exception.
63:3 Reserved.
Register Address: 186H, 390 IA32_PERFEVTSEL0
See Table 2-2. Unique
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Unique
Register Address: 198H, 408 IA32_PERF_STATUS
See Table 2-2. Shared
Register Address: 198H, 408 MSR_PERF_STATUS
Current performance status. See Section 15.1.1, “Software Interface For Initiating Performance State Transitions.” Shared
15:0 Current Performance State Value
30:16 Reserved.
31 XE Operation (R/O).
If set, XE operation is enabled. Default is cleared.
39:32 Reserved.
44:40 Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.
45 Reserved.
46 Non-Integer Bus Ratio (R/O)
Indicates non-integer bus ratio is enabled. Applies processors based on
Enhanced Intel Core microarchitecture.
63:47 Reserved.
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Unique
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
Unique
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-72 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Thermal Interrupt Control (R/W)
See Table 2-2.
Unique
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Unique
Register Address: 19DH, 413 MSR_THERM2_CTL
Thermal Monitor 2 Control Unique
15:0 Reserved.
16 TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-
clock duty cycle).
1 = Thermal Monitor 2 (thermally-initiated frequency transitions).
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no
effect. Neither TM1 nor TM2 are enabled.
63:16 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0 Fast-Strings Enable
See Table 2-2.
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2.
Unique
6:4 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Shared
8 Reserved.
9 Hardware Prefetcher Disable (R/W)
When set, disables the hardware prefetcher operation on streams of data.
When clear (default), enables the prefetch queue.
Disabling of the hardware prefetcher may impact processor performance.
10 FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break event
within the processor.
0 = Indicates compatible FERR# signaling behavior.
This bit must be set to 1 to support XAPIC interrupt model usage.
Shared
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Shared
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-73
MODEL-SPECIFIC REGISTERS (MSRS)
12 Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
Shared
13 TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the die
temperature is at the pre-determined threshold, the Thermal Monitor 2
mechanism is engaged. TM2 will reduce the bus to core ratio and voltage
according to the value last written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change the VID
signals or the bus to core ratio when the processor enters a thermally
managed state.
The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is
set; if the TM2 feature flag is not set, this feature is not supported and BIOS
must not alter the contents of the TM2 bit location.
The processor is operating out of specification if both this bit and the TM1 bit
are set to 0.
Shared
15:14 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
Shared
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Shared
19 Adjacent Cache Line Prefetch Disable (R/W)
When set to 1, the processor fetches the cache line that contains data
currently required by the processor. When set to 0, the processor fetches
cache lines that comprise a cache line pair (128 bytes).
Single processor platforms should not set this bit. Server platforms should set
or clear this bit based on platform performance observed in validation and
testing.
BIOS may contain a setup option that controls the setting of this bit.
Shared
20 Enhanced Intel SpeedStep Technology Select Lock (R/WO)
When set, this bit causes the following bits to become read-only:
• Enhanced Intel SpeedStep Technology Select Lock (this bit).
• Enhanced Intel SpeedStep Technology Enable bit.
The bit must be set before an Enhanced Intel SpeedStep Technology
transition is requested. This bit is cleared on reset.
Shared
21 Reserved.
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Shared
23 xTPR Message Disable (R/W)
See Table 2-2.
Shared
33:24 Reserved.
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-74 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
34 XD Bit Disable (R/W)
When set to 1, the Execute Disable Bit feature (XD Bit) is disabled and the XD
Bit extended feature flag will be clear (CPUID.80000001H: EDX[20]=0).
When set to a 0 (default), the Execute Disable Bit feature (if available) allows
the OS to enable PAE paging and take advantage of data only pages.
BIOS must not alter the contents of this bit location if XD bit is not supported.
Writing this bit to 1 when the XD Bit extended feature flag is set to 0 may
generate a #GP exception.
Unique
36:35 Reserved.
37 DCU Prefetcher Disable (R/W)
When set to 1, the DCU L1 data cache prefetcher is disabled. The default
value after reset is 0. BIOS may write ‘1’ to disable this feature.
The DCU prefetcher is an L1 data cache prefetcher. When the DCU prefetcher
detects multiple loads from the same line done within a time limit, the DCU
prefetcher assumes the next line will be required. The next line is prefetched
in to the L1 data cache from memory or L2.
Unique
38 IDA Disable (R/W)
When set to 1 on processors that support IDA, the Intel Dynamic Acceleration
feature (IDA) is disabled and the IDA_Enable feature flag will be cleared
(CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports
the processor’s support of IDA is enabled.
Note: The power-on default value is used by BIOS to detect hardware support
of IDA. If the power-on default value is 1, IDA is available in the processor. If
the power-on default value is 0, IDA is not available.
Shared
39 IP Prefetcher Disable (R/W)
When set to 1, the IP prefetcher is disabled. The default value after reset is 0.
BIOS may write ‘1’ to disable this feature.
The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher looks for
sequential load history to determine whether to prefetch the next expected
data into the L1 cache from memory or L2.
Unique
63:40 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
Unique
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
See Table 2-2.
Unique
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-75
MODEL-SPECIFIC REGISTERS (MSRS)
Last Exception Record From Linear IP (R/W)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
Unique
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R/W)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
Unique
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
See Table 2-2. Unique
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
See Table 2-2. Unique
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
See Table 2-2. Unique
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
See Table 2-2. Unique
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
See Table 2-2. Unique
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
See Table 2-2. Unique
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
See Table 2-2. Unique
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
See Table 2-2. Unique
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
See Table 2-2. Unique
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
See Table 2-2. Unique
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
See Table 2-2. Unique
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
See Table 2-2. Unique
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
See Table 2-2. Unique
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
See Table 2-2. Unique
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-76 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Unique
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
See Table 2-2. Unique
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
See Table 2-2. Unique
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
See Table 2-2. Unique
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
See Table 2-2. Unique
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
See Table 2-2. Unique
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
See Table 2-2. Unique
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
See Table 2-2. Unique
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
See Table 2-2. Unique
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
See Table 2-2. Unique
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
See Table 2-2. Unique
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
See Table 2-2. Unique
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
See Table 2-2. Unique
Register Address: 277H, 631 IA32_PAT
See Table 2-2. Unique
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2.
Unique
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
Unique
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
Unique
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-77
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
Unique
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Unique
Register Address: 345H, 837 MSR_PERF_CAPABILITIES
R/O. This applies to processors that do not support architectural perfmon version 2. Unique
5:0 LBR Format. See Table 2-2.
6 PEBS Record Format.
7 PEBSSaveArchRegs. See Table 2-2.
63:8 Reserved.
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
Unique
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 38EH, 910 MSR_PERF_GLOBAL_STATUS
See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 38FH, 911 MSR_PERF_GLOBAL_CTRL
See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 390H, 912 MSR_PERF_GLOBAL_OVF_CTRL
See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Unique
0 Enable PEBS on IA32_PMC0. (R/W)
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Unique
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 402H, 1026 IA32_MC0_ADDR
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-78 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Unique
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Unique
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Unique
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Unique
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Unique
Register Address: 40CH, 1036 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Unique
Register Address: 40DH, 1037 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 40EH, 1038 IA32_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Unique
Register Address: 410H, 1040 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.”
Register Address: 411H, 1041 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 412H, 1042 IA32_MC3_ADDR
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-79
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Unique
Register Address: 413H, 1043 IA32_MC3_MISC
Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the
MISCV flag in the IA32_MCi_STATUS register is set.
Unique
Register Address: 414H, 1044 IA32_MC5_CTL
Machine Check Error Reporting Register: Controls signaling of #MC for errors produced by a particular hardware unit
(or group of hardware units).
Unique
Register Address: 415H, 1045 IA32_MC5_STATUS
Machine Check Error Reporting Register: Contains information related to a machine-check error if its VAL (valid) flag is
set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them
causes a general-protection exception.
Unique
Register Address: 416H, 1046 IA32_MC5_ADDR
Machine Check Error Reporting Register: Contains the address of the code or data memory location that produced the
machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set.
Unique
Register Address: 417H, 1047 IA32_MC5_MISC
Machine Check Error Reporting Register: Contains additional information describing the machine-check error if the
MISCV flag in the IA32_MCi_STATUS register is set.
Unique
Register Address: 419H, 1045 IA32_MC6_STATUS
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 16.3.2.2,
“IA32_MCi_STATUS MSRS,” and Chapter 24.
Unique
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2. See Appendix A.1, “Basic VMX Information.”
Unique
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Table 2-2. See Appendix A.3, “VM-Execution Controls.”
Unique
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Unique
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2. See Appendix A.4, “VM-Exit Controls.”
Unique
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Table 2-2. See Appendix A.5, “VM-Entry Controls.”
Unique
Register Address: 485H, 1157 IA32_VMX_MISC
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-80 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 2-2. See Appendix A.6, “Miscellaneous Data.”
Unique
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”
Unique
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”
Unique
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”
Unique
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”
Unique
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2. See Appendix A.9, “VMCS Enumeration.”
Unique
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Unique
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2. See Section 20.6.3.4, “Debug Store (DS) Mechanism.”
Unique
Register Address: 107CCH, 67532 MSR_EMON_L3_CTR_CTL0
GBUSQ Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107CDH, 67533 MSR_EMON_L3_CTR_CTL1
GBUSQ Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107CEH, 67534 MSR_EMON_L3_CTR_CTL2
GSNPQ Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107CFH, 67535 MSR_EMON_L3_CTR_CTL3
GSNPQ Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107D0H, 67536 MSR_EMON_L3_CTR_CTL4
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-81
MODEL-SPECIFIC REGISTERS (MSRS)
FSB Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107D1H, 67537 MSR_EMON_L3_CTR_CTL5
FSB Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107D2H, 67538 MSR_EMON_L3_CTR_CTL6
FSB Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107D3H, 67539 MSR_EMON_L3_CTR_CTL7
FSB Event Control/Counter Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: 107D8H, 67544 MSR_EMON_L3_GL_CTL
L3/FSB Common Control Register (R/W)
Applies to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 18.2.2.
Unique
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
Unique
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
Unique
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
Unique
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
Unique
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W)
See Table 2-2.
Unique
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
Unique
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
Unique
Table 2-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-82 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.3 MSRS IN THE 45 NM AND 32 NM INTEL ATOM®
PROCESSOR FAMILY
Table 2-4 lists model-specific registers (MSRs) for 45 nm and 32 nm Intel Atom processors, architectural MSR
addresses are also included in Table 2-4. These processors have a CPUID Signature DisplayFamily_DisplayModel
value of 06_1CH, 06_26H, 06_27H, 06_35H, or 06_36H; see Table 2-1.
The column “Shared/Unique” applies to logical processors sharing the same core in processors based on the Intel
Atom microarchitecture. “Unique” means each logical processor has a separate MSR, or a bit field in an MSR
governs only a logical processor. “Shared” means the MSR or the bit field in an MSR address governs the operation
of both logical processors in the same core.
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Shared
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.” Shared
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Unique
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and see Table 2-2. Unique
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
Shared
Register Address: 17H, 23 MSR_PLATFORM_ID
Model Specific Platform ID (R) Shared
7:0 Reserved.
12:8 Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
63:13 Reserved.
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Unique
Register Address: 2AH, 42 MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current processor configuration.
Shared
0 Reserved.
1 Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Always 0.
2 Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Always 0.
Vol. 4 2-83
MODEL-SPECIFIC REGISTERS (MSRS)
3AERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled.
Always 0.
4 BERR# Enable for initiator bus requests (R/W)
1 = Enabled; 0 = Disabled.
Always 0.
5 Reserved.
6 Reserved.
7 BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled.
Always 0.
8 Reserved.
9Execute BIST (R/O)
1 = Enabled; 0 = Disabled.
10 AERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
Always 0.
11 Reserved.
12 BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
Always 0.
13 Reserved.
14 1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes.
15 Reserved.
17:16 APIC Cluster ID (R/O)
Always 00B.
19: 18 Reserved.
21: 20 Symmetric Arbitration ID (R/O)
Always 00B.
26:22 Integer Bus Frequency Ratio (R/O)
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
See Table 2-2.
Unique
Register Address: 40H, 64 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 From IP (R/W)
One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.5.
Unique
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
2-84 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41H, 65 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 42H, 66 MSR_LASTBRANCH_2_FROM_IP
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 43H, 67 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 44H, 68 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 45H, 69 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 46H, 70 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 47H, 71 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Unique
Register Address: 60H, 96 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains
pointers to the destination instruction.
Unique
Register Address: 61H, 97 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 62H, 98 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 63H, 99 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 64H, 100 MSR_LASTBRANCH_4_TO_IP
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 65H, 101 MSR_LASTBRANCH_5_TO_IP
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-85
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 66H, 102 MSR_LASTBRANCH_6_TO_IP
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 67H, 103 MSR_LASTBRANCH_7_TO_IP
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Unique
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Shared
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Unique
Register Address: C1H, 193 IA32_PMC0
Performance counter register
See Table 2-2.
Unique
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Unique
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed for processors based on Intel Atom microarchitecture.
Shared
2:0 • 111B: 083 MHz (FSB 333)
• 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
133.33 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with System Bus
Speed when encoding is 011B.
63:3 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Unique
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Unique
Register Address: FEH, 254 IA32_MTRRCAP
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
2-86 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Memory Type Range Register (R)
See Table 2-2.
Shared
Register Address: 11EH, 281 MSR_BBL_CR_CTL3
Control Register 3
Used to configure the L2 Cache.
Shared
0 L2 Hardware Enabled (R/O)
1 = Indicates the L2 is hardware-enabled.
0 = Indicates the L2 is hardware-disabled.
7:1 Reserved.
8 L2 Enabled (R/W)
1 = L2 cache has been initialized.
0 = Disabled (default).
Until this bit is set, the processor will not respond to the WBINVD instruction
or the assertion of the FLUSH# input.
22:9 Reserved.
23 L2 Not Present (R/O)
0 = L2 Present.
1 = L2 Not Present.
63:24 Reserved.
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Unique
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Unique
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Unique
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Unique
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Unique
0RIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) can be
used to restart the program. If cleared, the program cannot be reliably
restarted.
1EIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) is
directly associated with the error.
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-87
MODEL-SPECIFIC REGISTERS (MSRS)
2MCIP
When set, bit indicates that a machine check has been generated. If a second
machine check is detected while this bit is still set, the processor enters a
shutdown state. Software should write this bit to 0 after processing a
machine check exception.
63:3 Reserved.
Register Address: 186H, 390 IA32_PERFEVTSEL0
See Table 2-2. Unique
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Unique
Register Address: 198H, 408 IA32_PERF_STATUS
See Table 2-2. Shared
Register Address: 198H, 408 MSR_PERF_STATUS
Performance Status Shared
15:0 Current Performance State Value.
39:16 Reserved.
44:40 Maximum Bus Ratio (R/O)
Indicates maximum bus ratio configured for the processor.
63:45 Reserved.
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Unique
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
Unique
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2.
Unique
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Unique
Register Address: 19DH, 413 MSR_THERM2_CTL
Thermal Monitor 2 Control Shared
15:0 Reserved.
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
2-88 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
16 TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-
clock duty cycle).
1 = Thermal Monitor 2 (thermally-initiated frequency transitions).
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no
effect. Neither TM1 nor TM2 are enabled.
63:17 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
Unique
0 Fast-Strings Enable
See Table 2-2.
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 0.
Unique
6:4 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Shared
8 Reserved.
9 Reserved.
10 FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break event
within the processor.
0 = Indicates compatible FERR# signaling behavior.
This bit must be set to 1 to support XAPIC interrupt model usage.
Shared
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Shared
12 Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
Shared
13 TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the die
temperature is at the pre-determined threshold, the Thermal Monitor 2
mechanism is engaged. TM2 will reduce the bus to core ratio and voltage
according to the value last written to MSR_THERM2_CTL bits 15:0.
When this bit is cleared (0, default), the processor does not change the VID
signals or the bus to core ratio when the processor enters a thermally
managed state.
The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is
set; if the TM2 feature flag is not set, this feature is not supported and BIOS
must not alter the contents of the TM2 bit location.
The processor is operating out of specification if both this bit and the TM1 bit
are set to 0.
Shared
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-89
MODEL-SPECIFIC REGISTERS (MSRS)
15:14 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
Shared
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Shared
19 Reserved.
20 Enhanced Intel SpeedStep Technology Select Lock (R/WO)
When set, this bit causes the following bits to become read-only:
• Enhanced Intel SpeedStep Technology Select Lock (this bit).
• Enhanced Intel SpeedStep Technology Enable bit.
The bit must be set before an Enhanced Intel SpeedStep Technology transition
is requested. This bit is cleared on reset.
Shared
21 Reserved.
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Unique
23 xTPR Message Disable (R/W)
See Table 2-2.
Shared
33:24 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Unique
63:35 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
Unique
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
See Table 2-2.
Unique
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
Unique
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
Unique
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
See Table 2-2. Shared
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
2-90 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Shared
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
See Table 2-2. Shared
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
See Table 2-2. Shared
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
See Table 2-2. Shared
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
See Table 2-2. Shared
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
See Table 2-2. Shared
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
See Table 2-2. Shared
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
See Table 2-2. Shared
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
See Table 2-2. Shared
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
See Table 2-2. Shared
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
See Table 2-2. Shared
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
See Table 2-2. Shared
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
See Table 2-2. Shared
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
See Table 2-2. Shared
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
See Table 2-2. Shared
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
See Table 2-2. Shared
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
See Table 2-2. Shared
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
See Table 2-2. Shared
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
See Table 2-2. Shared
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-91
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
See Table 2-2. Shared
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
See Table 2-2. Shared
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
See Table 2-2. Shared
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
See Table 2-2. Shared
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
See Table 2-2. Shared
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
See Table 2-2. Shared
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
See Table 2-2. Shared
Register Address: 277H, 631 IA32_PAT
See Table 2-2. Unique
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
Unique
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
Unique
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
Unique
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Shared
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
Unique
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Unique
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
2-92 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Unique
0 Enable PEBS on IA32_PMC0 (R/W)
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Shared
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Shared
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Shared
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Shared
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Shared
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Shared
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Shared
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Shared
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Shared
Register Address: 40DH, 1037 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Shared
Register Address: 40EH, 1038 IA32_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Shared
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Shared
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Shared
Register Address: 412H, 1042 IA32_MC4_ADDR
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-93
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Shared
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2. See Appendix A.1, “Basic VMX Information.”
Unique
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Table 2-2. See Appendix A.3, “VM-Execution Controls.”
Unique
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Unique
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2. See Appendix A.4, “VM-Exit Controls.”
Unique
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Table 2-2. See Appendix A.5, “VM-Entry Controls.”
Unique
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 2-2. See Appendix A.6, “Miscellaneous Data.”
Unique
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”
Unique
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 2-2. See Appendix A.7, “VMX-Fixed Bits in CR0.”
Unique
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”
Unique
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 2-2. See Appendix A.8, “VMX-Fixed Bits in CR4.”
Unique
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2. See Appendix A.9, “VMCS Enumeration.”
Unique
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
2-94 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-5 lists model-specific registers (MSRs) that are specific to Intel Atom
®
processor with a CPUID Signature
DisplayFamily_DisplayModel value of 06_27H.
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Unique
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2. See Section 20.6.3.4, “Debug Store (DS) Mechanism.”
Unique
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
Unique
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
Unique
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
Unique
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
Unique
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W)
See Table 2-2.
Unique
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
Unique
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
Unique
Table 2-5. MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_27H
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 3F8H, 1016 MSR_PKG_C2_RESIDENCY
Package C2 Residency
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
Table 2-4. MSRs in the 45 nm and 32 nm Intel Atom® Processor Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-95
MODEL-SPECIFIC REGISTERS (MSRS)
2.4 MSRS IN INTEL PROCESSORS BASED ON SILVERMONT
MICROARCHITECTURE
Table 2-6 lists model-specific registers (MSRs) common to Intel processors based on the Silvermont microarchitec-
ture. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_37H, 06_4AH, 06_4DH,
06_5AH, or 06_5DH; see Table 2-1. The MSRs listed in Table 2-6 are also common to processors based on the
Airmont microarchitecture and newer microarchitectures for next generation Intel Atom processors.
Table 2-7 lists MSRs common to processors based on the Silvermont and Airmont microarchitectures, but not
newer microarchitectures.
Table 2-8, Table 2-9, and Table 2-10 lists MSRs that are model-specific across processors based on the Silvermont
microarchitecture.
In the Silvermont microarchitecture, the scope column indicates the following: “Core” means each processor core
has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field
is shared by a subset of the processor cores in the physical package. The number of processor cores in this subset
is model specific and may differ between different processors. For all processors based on Silvermont microarchi-
tecture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used
to figure out which processors are in the same module. “Package” means all processor cores in the physical
package share the same MSR or bit interface.
63:0 Package C2 Residency Counter (R/O)
Time that this package is in processor-specific C2 states since last reset.
Counts at 1 Mhz frequency.
Package
Register Address: 3F9H, 1017 MSR_PKG_C4_RESIDENCY
Package C4 Residency
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C4 Residency Counter. (R/O)
Time that this package is in processor-specific C4 states since last reset.
Counts at 1 Mhz frequency.
Package
Register Address: 3FAH, 1018 MSR_PKG_C6_RESIDENCY
Package C6 Residency
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C6 Residency Counter. (R/O)
Time that this package is in processor-specific C6 states since last reset.
Counts at 1 Mhz frequency.
Package
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Module
Register Address: 1H, 1 IA32_P5_MC_TYPE
Table 2-5. MSRs Supported by Intel Atom® Processors (Contd.)with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_27H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-96 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 2.23, “MSRs in Pentium Processors.” Module
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Core
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Core
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Core
Register Address: 2AH, 42 MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration (R/W)
Writes ignored.
Module
63:0 Reserved.
Register Address: 34H, 52 MSR_SMI_COUNT
SMI Counter (R/O) Core
31:0 SMI Count (R/O)
Running count of SMI events since last RESET.
63:32 Reserved.
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Core
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Core
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
See Table 2-2.
Core
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Core
Register Address: E4H, 228 MSR_PMG_IO_CAPTURE_BASE
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
Module
15:0 LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If IO MWAIT
Redirection is enabled, reads to this address will be consumed by the power
management logic and decoded to MWAIT instructions. When IO port
address redirection is enabled, this is the IO port address reported to the
OS/software.
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-97
MODEL-SPECIFIC REGISTERS (MSRS)
18:16 C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to be
included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
100b - C4 is the max C-State to include
110b - C6 is the max C-State to include
111b - C7 is the max C-State to include
63:19 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Core
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Core
Register Address: FEH, 254 IA32_MTRRCAP
Memory Type Range Register (R)
See Table 2-2.
Core
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.
Core
1:0 AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES instruction
sets availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note: AES instruction set is not available if read is unsuccessful. If the
configuration is not 01b, AES instructions can be mis-configured if a
privileged agent unintentionally writes 11b.
63:2 Reserved.
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Core
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Core
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Core
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Core
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Core
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-98 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
0RIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) can
be used to restart the program. If cleared, the program cannot be reliably
restarted.
1EIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) is
directly associated with the error.
2MCIP
When set, bit indicates that a machine check has been generated. If a
second machine check is detected while this bit is still set, the processor
enters a shutdown state. Software should write this bit to 0 after
processing a machine check exception.
63:3 Reserved.
Register Address: 186H, 390 IA32_PERFEVTSEL0
See Table 2-2. Core
7:0 Event Select
15:8 UMask
16 USR
17 OS
18 Edge
19 PC
20 INT
21 Reserved.
22 EN
23 INV
31:24 CMASK
63:32 Reserved.
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Core
Register Address: 198H, 408 IA32_PERF_STATUS
See Table 2-2. Module
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Core
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
Core
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-99
MODEL-SPECIFIC REGISTERS (MSRS)
Thermal Interrupt Control (R/W)
See Table 2-2.
Core
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Core
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Package
15:0 Reserved.
23:16 Temperature Target (R)
The default thermal throttling or PROCHOT# activation temperature in
degrees C. The effective temperature for thermal throttling or PROCHOT#
activation is “Temperature Target” + “Target Offset”.
29:24 Target Offset (R/W)
Specifies an offset in degrees C to adjust the throttling and PROCHOT#
activation temperature from the default target specified in
TEMPERATURE_TARGET (bits 23:16).
63:30 Reserved.
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0
Offcore Response Event Select Register (R/W) Module
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
Offcore Response Event Select Register (R/W) Module
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
See Table 2-2. Core
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
See Table 2-2.
Core
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R/W)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
Core
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R/W)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
Core
Register Address: 1F2H, 498 IA32_SMRR_PHYSBASE
See Table 2-2. Core
Register Address: 1F3H, 499 IA32_SMRR_PHYSMASK
See Table 2-2. Core
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
See Table 2-2. Core
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-100 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
See Table 2-2. Core
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
See Table 2-2. Core
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
See Table 2-2. Core
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
See Table 2-2. Core
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
See Table 2-2. Core
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
See Table 2-2. Core
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
See Table 2-2. Core
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
See Table 2-2. Core
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
See Table 2-2. Core
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
See Table 2-2. Core
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
See Table 2-2. Core
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
See Table 2-2. Core
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
See Table 2-2. Core
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
See Table 2-2. Core
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
See Table 2-2. Core
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
See Table 2-2. Core
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
See Table 2-2. Core
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
See Table 2-2. Core
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-101
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Core
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
See Table 2-2. Core
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
See Table 2-2. Core
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
See Table 2-2. Core
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
See Table 2-2. Core
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
See Table 2-2. Core
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
See Table 2-2. Core
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
See Table 2-2. Core
Register Address: 277H, 631 IA32_PAT
See Table 2-2. Core
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2.
Core
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
Core
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
Core
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
Core
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Core
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
Core
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Core
Register Address: 3FDH, 1021 MSR_CORE_C6_RESIDENCY
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-102 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C6 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C6 states.
Counts at the TSC Frequency.
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Module
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Module
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Module
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Module
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Module
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Module
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Module
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Module
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 40DH, 1037 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 40EH, 1038 IA32_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Core
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-103
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Core
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Package
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Package
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.1, “Basic VMX Information.”
Core
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Table 2-2.
See Appendix A.3, “VM-Execution Controls.”
Core
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Core
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2.
See Appendix A.4, “VM-Exit Controls.”
Core
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Table 2-2.
See Appendix A.5, “VM-Entry Controls.”
Core
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 2-2.
See Appendix A.6, “Miscellaneous Data.”
Core
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-104 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
Core
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 2-2.
See Appendix A.7, “VMX-Fixed Bits in CR0.”
Core
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
Core
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 2-2.
See Appendix A.8, “VMX-Fixed Bits in CR4.”
Core
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2.
See Appendix A.9, “VMCS Enumeration.”
Core
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Core
Register Address: 48CH, 1164 IA32_VMX_EPT_VPID_ENUM
Capability Reporting Register of EPT and VPID (R/O)
See Table 2-2.
Core
Register Address: 48DH, 1165 IA32_VMX_TRUE_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 48EH, 1166 IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-based VM-Execution Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 48FH, 1167 IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-Exit Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 490H, 1168 IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VM-Entry Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 491H, 1169 IA32_VMX_FMFUNC
Capability Reporting Register of VM-Function Controls (R/O)
See Table 2-2.
Core
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-105
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 4C1H, 1217 IA32_A_PMC0
See Table 2-2. Core
Register Address: 4C2H, 1218 IA32_A_PMC1
See Table 2-2. Core
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”
Core
Register Address: 660H, 1632 MSR_CORE_C1_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C1 Residency Counter. (R/O)
Value since last reset that this core is in processor-specific C1 states.
Counts at the TSC frequency.
Register Address: 6E0H, 1760 IA32_TSC_DEADLINE
TSC Target of Local APIC’s TSC Deadline Mode (R/W)
See Table 2-2.
Core
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
Core
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
Core
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
Core
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
Core
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W)
See Table 2-2.
Core
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
Core
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
Core
Register Address: C000_0103H IA32_TSC_AUX
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-106 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-7 lists model-specific registers (MSRs) that are common to Intel Atom
®
processors based on the Silver-
mont and Airmont microarchitectures but not newer microarchitectures.
AUXILIARY TSC Signature (R/W)
See Table 2-2.
Core
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 17H, 23 MSR_PLATFORM_ID
Model Specific Platform ID (R) Module
7:0 Reserved.
13:8 Maximum Qualified Ratio (R)
The maximum allowed bus ratio.
49:13 Reserved.
52:50 See Table 2-2.
63:33 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
See Table 2-2.
Core
0Lock (R/WL)
1 Reserved.
2 Enable VMX outside SMX operation (R/WL)
Register Address: 40H, 64 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 From IP (R/W)
One of eight pairs of last branch record registers on the last branch record stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.5 and record format in Section 18.4.8.1.
Core
Register Address: 41H, 65 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 42H, 66 MSR_LASTBRANCH_2_FROM_IP
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 43H, 67 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 44H, 68 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Table 2-6. MSRs Common to Intel Atom® Processors (Silvermont and Newer Microarchitectures) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-107
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 45H, 69 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 46H, 70 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 47H, 71 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 60H, 96 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of eight pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains
pointers to the destination instruction.
Core
Register Address: 61H, 97 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 62H, 98 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 63H, 99 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 64H, 100 MSR_LASTBRANCH_4_TO_IP
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 65H, 101 MSR_LASTBRANCH_5_TO_IP
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 66H, 102 MSR_LASTBRANCH_6_TO_IP
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 67H, 103 MSR_LASTBRANCH_7_TO_IP
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information: Contains power management and other model specific features enumeration. See
http://biosbits.org.
Package
7:0 Reserved.
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-108 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the maximum frequency that does not require turbo.
Frequency = ratio * Scalable Bus Frequency.
Package
63:16 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
See http://biosbits.org.
Module
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0 (no package C-sate support)
001b: C1 (Behavior is the same as 000b)
100b: C4
110b: C6
111b: C7 (Silvermont only)
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
63:16 Reserved.
Register Address: 11EH, 281 MSR_BBL_CR_CTL3
Control Register 3
Used to configure the L2 Cache.
Module
0 L2 Hardware Enabled (R/O)
1 = If the L2 is hardware-enabled.
0 = Indicates if the L2 is hardware-disabled.
7:1 Reserved.
8 L2 Enabled (R/W)
1 = L2 cache has been initialized.
0 = Disabled (default).
Until this bit is set the processor will not respond to the WBINVD instruction
or the assertion of the FLUSH# input.
22:9 Reserved.
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-109
MODEL-SPECIFIC REGISTERS (MSRS)
23 L2 Not Present (R/O)
0 = L2 Present.
1 = L2 Not Present.
63:24 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0 Fast-Strings Enable
See Table 2-2.
Core
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 0.
Module
6:4 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Core
10:8 Reserved.
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Core
12 Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
Core
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
Module
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Core
21:19 Reserved.
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Core
23 xTPR Message Disable (R/W)
See Table 2-2.
Module
33:24 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Core
37:35 Reserved.
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-110 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
38 Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost Technology, the
turbo mode feature is disabled and the IDA_Enable feature flag will be
cleared (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports
the processor’s support of turbo mode is enabled.
Note: The power-on default value is used by BIOS to detect hardware
support of turbo mode. If the power-on default value is 1, turbo mode is
available in the processor. If the power-on default value is 0, turbo mode is
not available.
Module
63:39 Reserved.
Register Address: 1C8H, 456 MSR_LBR_SELECT
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
Core
0CPL_EQ_0
1 CPL_NEQ_0
2JCC
3 NEAR_REL_CALL
4NEAR_IND_CALL
5 NEAR_RET
6NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Core
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Core
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core
0 Enable PEBS for precise event on IA32_PMC0 (R/W)
Register Address: 3FAH, 1018 MSR_PKG_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C6 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C6 states.
Counts at the TSC Frequency.
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-111
MODEL-SPECIFIC REGISTERS (MSRS)
2.4.1 MSRs with Model-Specific Behavior in the Silvermont Microarchitecture
Table 2-8 lists MSRs that are specific to the Intel Atom
®
processor E3000 Series (CPUID Signature
DisplayFamily_DisplayModel value of 06_37H) and Intel Atom processors (CPUID Signature
DisplayFamily_DisplayModel value of 06_4AH, 06_5AH, or 06_5DH).
Register Address: 664H, 1636 MSR_MC6_RESIDENCY_COUNTER
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Module
63:0 Time that this module is in module-specific C6 states since last reset. Counts
at 1 Mhz frequency.
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed for processors based on Silvermont microarchitecture.
Module
2:0 • 100B: 080.0 MHz
• 000B: 083.3 MHz
• 001B: 100.0 MHz
• 010B: 133.3 MHz
• 011B: 116.7 MHz
63:3 Reserved.
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
Package
3:0 Power Units
Power related information (in milliWatts) is based on the multiplier, 2^PU;
where PU is an unsigned integer represented by bits 3:0. Default value is
0101b, indicating power unit is in 32 milliWatts increment.
7:4 Reserved.
12:8 Energy Status Units
Energy related information (in microJoules) is based on the multiplier, 2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value is
00101b, indicating energy unit is in 32 microJoules increment.
15:13 Reserved.
19:16 Time Unit
The value is 0000b, indicating time unit is in one second.
63:20 Reserved.
Register Address: 610H, 1552 MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W) Package
Table 2-7. MSRs Common to the Silvermont and Airmont Microarchitectures (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-112 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-9 lists model-specific registers (MSRs) that are specific to the Intel Atom
®
processor E3000 Series (CPUID
Signature DisplayFamily_DisplayModel value of 06_37H).
14:0 Package Power Limit #1 (R/W)
See Section 15.10.3, “Package RAPL Domain,” and MSR_RAPL_POWER_UNIT
in Table 2-8.
15 Enable Power Limit #1 (R/W)
See Section 15.10.3, “Package RAPL Domain.”
16 Package Clamping Limitation #1 (R/W)
See Section 15.10.3, “Package RAPL Domain.”
23:17 Time Window for Power Limit #1 (R/W)
In unit of second. If 0 is specified in bits [23:17], defaults to 1 second
window.
63:24 Reserved.
Register Address: 611H, 1553 MSR_PKG_ENERGY_STATUS
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain,” and MSR_RAPL_POWER_UNIT in Table 2-8.
Package
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains,” and MSR_RAPL_POWER_UNIT in Table 2-8.
Package
Table 2-9. Specific MSRs Supported by the Intel Atom® Processor E3000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_37H
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 668H, 1640 MSR_CC6_DEMOTION_POLICY_CONFIG
Core C6 Demotion Policy Config MSR Package
63:0 Controls per-core C6 demotion policy. Writing a value of 0 disables core
level HW demotion policy.
Register Address: 669H, 1641 MSR_MC6_DEMOTION_POLICY_CONFIG
Module C6 Demotion Policy Config MSR Package
63:0 Controls module (i.e., two cores sharing the second-level cache) C6
demotion policy. Writing a value of 0 disables module level HW demotion
policy.
Register Address: 664H, 1636 MSR_MC6_RESIDENCY_COUNTER
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Module
63:0 Time that this module is in module-specific C6 states since last reset.
Counts at 1 Mhz frequency.
Table 2-8. Specific MSRs Supported by Intel Atom® Processors with a CPUID Signature DisplayFamily_DisplayModel
Value of 06_37H, 06_4AH, 06_5AH, or 06_5DH (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-113
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-10 lists model-specific registers (MSRs) that are specific to Intel Atom
®
processor C2000 Series (CPUID
Signature DisplayFamily_DisplayModel value of 06_4DH).
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4DH
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 1A4H, 420 MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0 L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional lines of
code or data into the L2 cache.
Core
1 Reserved.
2 DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next cache
line into L1 data cache.
Core
63:3 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode (R/W) Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
39:32 Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
Package
47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
Package
55:48 Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
Package
63:56 Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
Package
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
Package
3:0 Power Units
Power related information (in milliWatts) is based on the multiplier, 2^PU;
where PU is an unsigned integer represented by bits 3:0. Default value is
0101b, indicating power unit is in 32 milliWatts increment.
7:4 Reserved.
2-114 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.4.2 MSRs in Intel Atom® Processors Based on Airmont Microarchitecture
Intel Atom processor X7-Z8000 and X5-Z8000 series are based on the Airmont microarchitecture. These proces-
sors support MSRs listed in Table 2-6, Table 2-7, Table 2-8, and Table 2-11. These processors have a CPUID
Signature DisplayFamily_DisplayModel value of 06_4CH; see Table 2-1.
12:8 Energy Status Units.
Energy related information (in microJoules) is based on the multiplier,
2^ESU; where ESU is an unsigned integer represented by bits 12:8.
Default value is 00101b, indicating energy unit is in 32 microJoules
increment.
15:13 Reserved.
19:16 Time Unit
The value is 0000b, indicating time unit is in one second.
63:20 Reserved.
Register Address: 610H, 1552 MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 66EH, 1646 MSR_PKG_POWER_INFO
PKG RAPL Parameter (R/0) Package
14:0 Thermal Spec Power (R/0)
The unsigned integer value is the equivalent of the thermal specification
power of the package domain. The unit of this field is specified by the
“Power Units” field of MSR_RAPL_POWER_UNIT.
63:15 Reserved.
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the intended scalable bus clock speed for processors based on Airmont microarchitecture.
Module
3:0 • 0000B: 083.3 MHz
• 0001B: 100.0 MHz
• 0010B: 133.3 MHz
• 0011B: 116.7 MHz
• 0100B: 080.0 MHz
• 0101B: 093.3 MHz
• 0110B: 090.0 MHz
• 0111B: 088.9 MHz
• 1000B: 087.5 MHz
63:5 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
Table 2-10. Specific MSRs Supported by Intel Atom® Processor C2000 Series with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4DH (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-115
MODEL-SPECIFIC REGISTERS (MSRS)
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
See http://biosbits.org.
Module
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: No limit
001b: C1
010b: C2
110b: C6
111b: C7
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
63:16 Reserved.
Register Address: E4H, 228 MSR_PMG_IO_CAPTURE_BASE
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
Module
15:0 LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If IO
MWAIT Redirection is enabled, reads to this address will be consumed by
the power management logic and decoded to MWAIT instructions. When IO
port address redirection is enabled, this is the IO port address reported to
the OS/software.
18:16 C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to be
included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - Deep Power Down Technology is the max C-State.
010b - C7 is the max C-State to include.
63:19 Reserved.
Register Address: 638H, 1592 MSR_PP0_POWER_LIMIT
PP0 RAPL Power Limit Control (R/W) Package
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-116 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.5 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT
MICROARCHITECTURE
Intel Atom processors based on the Goldmont microarchitecture support MSRs listed in Table 2-6 and Table 2-12.
These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_5CH; see Table 2-1.
In the Goldmont microarchitecture, the scope column indicates the following: “Core” means each processor core
has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field
is shared by a subset of the processor cores in the physical package. The number of processor cores in this subset
is model specific and may differ between different processors. For all processors based on Goldmont microarchitec-
ture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used to
figure out which processors are in the same module. “Package” means all processor cores in the physical package
share the same MSR or bit interface.
14:0 PP0 Power Limit #1 (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains,” and
MSR_RAPL_POWER_UNIT in Table 2-8.
15 Enable Power Limit #1 (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
16 Reserved.
23:17 Time Window for Power Limit #1 (R/W)
Specifies the time duration over which the average power must remain
below PP0_POWER_LIMIT #1(14:0). Supported Encodings:
0x0: 1 second time duration.
0x1: 5 second time duration (Default).
0x2: 10 second time duration.
0x3: 15 second time duration.
0x4: 20 second time duration.
0x5: 25 second time duration.
0x6: 30 second time duration.
0x7: 35 second time duration.
0x8: 40 second time duration.
0x9: 45 second time duration.
0xA: 50 second time duration.
0xB-0x7F - reserved.
63:24 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 17H, 23 MSR_PLATFORM_ID
Model Specific Platform ID (R) Module
49:0 Reserved.
52:50 See Table 2-2.
Table 2-11. MSRs in Intel Atom® Processors Based on Airmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-117
MODEL-SPECIFIC REGISTERS (MSRS)
63:33 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Core
0Lock (R/WL)
1 Enable VMX inside SMX operation (R/WL)
2 Enable VMX outside SMX operation (R/WL)
14:8 SENTER local functions enables (R/WL)
15 SENTER global functions enable (R/WL)
18 SGX global functions enable (R/WL)
63:19 Reserved.
Register Address: 3BH, 59 IA32_TSC_ADJUST
Per-Core TSC ADJUST (R/W)
See Table 2-2.
Core
Register Address: C3H, 195 IA32_PMC2
Performance Counter Register
See Table 2-2.
Core
Register Address: C4H, 196 IA32_PMC3
Performance Counter Register
See Table 2-2.
Core
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the maximum frequency that does not require turbo.
Frequency = ratio * 100 MHz.
Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode is programmable.
When set to 0, indicates TDP Limit for Turbo mode is not programmable.
Package
30 Programmable TJ OFFSET (R/O)
When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is
valid and writable to specify a temperature offset.
Package
39:31 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-118 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
See http://biosbits.org.
Core
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
0000b: No limit
0001b: C1
0010b: C3
0011b: C6
0100b: C7
0101b: C7S
0110b: C8
0111b: C9
1000b: C10
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
63:16 Reserved.
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability enhancement. Accessible only while in SMM.
Core
57:0 Reserved.
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is supported and
the MSR_SMM_FEATURE_CONTROL is supported.
59 Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported and the
MSR_SMM_DELAYED is supported.
63:60 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-119
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 188H, 392 IA32_PERFEVTSEL2
See Table 2-2. Core
Register Address: 189H, 393 IA32_PERFEVTSEL3
See Table 2-2. Core
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0 Fast-Strings Enable
See Table 2-2.
Core
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.
Package
6:4 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Core
10:8 Reserved.
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Core
12 Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
Core
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
Package
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Core
21:19 Reserved.
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Core
23 xTPR Message Disable (R/W)
See Table 2-2.
Package
33:24 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Core
37:35 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-120 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
38 Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost Technology,
the turbo mode feature is disabled and the IDA_Enable feature flag will be
clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
reports the processor’s support of turbo mode is enabled.
Note: The power-on default value is used by BIOS to detect hardware
support of turbo mode. If the power-on default value is 1, turbo mode is
available in the processor. If the power-on default value is 0, turbo mode
is not available.
Package
63:39 Reserved.
Register Address: 1A4H, 420 MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0 L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional lines of
code or data into the L2 cache.
Core
1 Reserved.
2 DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next cache
line into L1 data cache.
Core
63:3 Reserved.
Register Address: 1AAH, 426 MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control
Various model specific features enumeration. See http://biosbits.org.
Package
0 EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced Intel Speedstep
Technology request from processor cores. When 1, disables hardware
coordination of Enhanced Intel Speedstep Technology requests.
21:1 Reserved.
22 Thermal Interrupt Coordination Enable (R/W)
If set, then thermal interrupt on one core is routed to all cores.
63:23 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode by Core Groups (R/W)
Specifies Maximum Ratio Limit for each Core Group. Max ratio for groups with more cores must decrease
monotonically.
For groups with less than 4 cores, the max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must be
22 or less. For groups with more than 5 cores, the max ratio must be 16 or less.
Package
7:0 Maximum Ratio Limit for Active Cores in Group 0
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 0 threshold.
Package
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-121
MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum Ratio Limit for Active Cores in Group 1
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 1 threshold, and greater than the Group 0 threshold.
Package
23:16 Maximum Ratio Limit for Active Cores in Group 2
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 2 threshold, and greater than the Group 1 threshold.
Package
31:24 Maximum Ratio Limit for Active Cores in Group 3
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 3 threshold, and greater than the Group 2 threshold.
Package
39:32 Maximum Ratio Limit for Active Cores in Group 4
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 4 threshold, and greater than the Group 3 threshold.
Package
47:40 Maximum Ratio Limit for Active Cores in Group 5
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 5 threshold, and greater than the Group 4 threshold.
Package
55:48 Maximum Ratio Limit for Active Cores in Group 6
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 6 threshold, and greater than the Group 5 threshold.
Package
63:56 Maximum Ratio Limit for Active Cores in Group 7
Maximum turbo ratio limit when the number of active cores is less than or
equal to the Group 7 threshold, and greater than the Group 6 threshold.
Package
Register Address: 1AEH, 430 MSR_TURBO_GROUP_CORECNT
Group Size of Active Cores for Turbo Mode Operation (R/W)
Writes of 0 threshold is ignored.
Package
7:0 Group 0 Core Count Threshold
Maximum number of active cores to operate under the Group 0 Max Turbo
Ratio limit.
Package
15:8 Group 1 Core Count Threshold
Maximum number of active cores to operate under the Group 1 Max Turbo
Ratio limit. Must be greater than the Group 0 Core Count.
Package
23:16 Group 2 Core Count Threshold
Maximum number of active cores to operate under the Group 2 Max Turbo
Ratio limit. Must be greater than the Group 1 Core Count.
Package
31:24 Group 3 Core Count Threshold
Maximum number of active cores to operate under the Group 3 Max Turbo
Ratio limit. Must be greater than the Group 2 Core Count.
Package
39:32 Group 4 Core Count Threshold
Maximum number of active cores to operate under the Group 4 Max Turbo
Ratio limit. Must be greater than the Group 3 Core Count.
Package
47:40 Group 5 Core Count Threshold
Maximum number of active cores to operate under the Group 5 Max Turbo
Ratio limit. Must be greater than the Group 4 Core Count.
Package
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-122 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
55:48 Group 6 Core Count Threshold
Maximum number of active cores to operate under the Group 6 Max Turbo
Ratio limit. Must be greater than the Group 5 Core Count.
Package
63:56 Group 7 Core Count Threshold
Maximum number of active cores to operate under the Group 7 Max Turbo
Ratio limit. Must be greater than the Group 6 Core Count, and not less than
the total number of processor cores in the package. E.g., specify 255.
Package
Register Address: 1C8H, 456 MSR_LBR_SELECT
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
Core
0CPL_EQ_0
1 CPL_NEQ_0
2JCC
3 NEAR_REL_CALL
4NEAR_IND_CALL
5 NEAR_RET
6NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
9 EN_CALL_STACK
63:10 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 1FCH, 508 MSR_POWER_CTL
Power Control Register
See http://biosbits.org.
Core
0 Reserved.
1 C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced
Intel SpeedStep Technology operating point when all execution cores
enter MWAIT (C1).
Package
63:2 Reserved.
Register Address: 210H, 528 IA32_MTRR_PHYSBASE8
See Table 2-2. Core
Register Address: 211H, 529 IA32_MTRR_PHYSMASK8
See Table 2-2. Core
Register Address: 212H, 530 IA32_MTRR_PHYSBASE9
See Table 2-2. Core
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-123
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: IA32_MTRR_PHYSMASK9
213H, 531 See Table 2-2. Core
Register Address: IA32_MC0_CTL2
280H, 640 See Table 2-2. Module
Register Address: IA32_MC1_CTL2
281H, 641 See Table 2-2. Module
Register Address: IA32_MC2_CTL2
282H, 642 See Table 2-2. Core
Register Address: 283H, 643 IA32_MC3_CTL2
See Table 2-2. Module
Register Address: 284H, 644 IA32_MC4_CTL2
See Table 2-2. Package
Register Address: 285H, 645 IA32_MC5_CTL2
See Table 2-2. Package
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 300H, 768 MSR_SGXOWNEREPOCH0
Lower 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.
Package
63:0 Lower 64 bits of an 128-bit external entropy value for key derivation of
an enclave.
Register Address: 301H, 769 MSR_SGXOWNEREPOCH1
Upper 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.
Package
63:0 Upper 64 bits of an 128-bit external entropy value for key derivation of
an enclave.
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” Core
0Ovf_PMC0
1Ovf_PMC1
2Ovf_PMC2
3Ovf_PMC3
31:4 Reserved.
32 Ovf_FixedCtr0
33 Ovf_FixedCtr1
34 Ovf_FixedCtr2
54:35 Reserved.
55 Trace_ToPA_PMI
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-124 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
57:56 Reserved.
58 LBR_Frz
59 CTR_Frz
60 ASCI
61 Ovf_Uncore
62 Ovf_BufDSSAVE
63 CondChgd
Register Address: 390H, 912 IA32_PERF_GLOBAL_STATUS_RESET
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” Core
0 Set 1 to clear Ovf_PMC0.
1 Set 1 to clear Ovf_PMC1.
2 Set 1 to clear Ovf_PMC2.
3 Set 1 to clear Ovf_PMC3.
31:4 Reserved.
32 Set 1 to clear Ovf_FixedCtr0.
33 Set 1 to clear Ovf_FixedCtr1.
34 Set 1 to clear Ovf_FixedCtr2.
54:35 Reserved.
55 Set 1 to clear Trace_ToPA_PMI.
57:56 Reserved.
58 Set 1 to clear LBR_Frz.
59 Set 1 to clear CTR_Frz.
60 Set 1 to clear ASCI.
61 Set 1 to clear Ovf_Uncore.
62 Set 1 to clear Ovf_BufDSSAVE.
63 Set 1 to clear CondChgd.
Register Address: 391H, 913 IA32_PERF_GLOBAL_STATUS_SET
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.” Core
0 Set 1 to cause Ovf_PMC0 = 1.
1 Set 1 to cause Ovf_PMC1 = 1.
2 Set 1 to cause Ovf_PMC2 = 1.
3 Set 1 to cause Ovf_PMC3 = 1.
31:4 Reserved.
32 Set 1 to cause Ovf_FixedCtr0 = 1.
33 Set 1 to cause Ovf_FixedCtr1 = 1.
34 Set 1 to cause Ovf_FixedCtr2 = 1.
54:35 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-125
MODEL-SPECIFIC REGISTERS (MSRS)
55 Set 1 to cause Trace_ToPA_PMI = 1.
57:56 Reserved.
58 Set 1 to cause LBR_Frz = 1.
59 Set 1 to cause CTR_Frz = 1.
60 Set 1 to cause ASCI = 1.
61 Set 1 to cause Ovf_Uncore.
62 Set 1 to cause Ovf_BufDSSAVE.
63 Reserved.
Register Address: 392H, 914 IA32_PERF_GLOBAL_INUSE
See Table 2-2. Core
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Table 2-2 and Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core
0 Enable PEBS trigger and recording for the programmed event (precise or
otherwise) on IA32_PMC0. (R/W)
Register Address: 3F8H, 1016 MSR_PKG_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C3 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C3 states.
Count at the same frequency as the TSC.
Register Address: 3F9H, 1017 MSR_PKG_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C6 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C6 states.
Count at the same frequency as the TSC.
Register Address: 3FCH, 1020 MSR_CORE_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C3 states.
Count at the same frequency as the TSC.
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Module
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-126 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 4C3H, 1219 IA32_A_PMC2
See Table 2-2. Core
Register Address: 4C4H, 1220 IA32_A_PMC3
See Table 2-2. Core
Register Address: 4E0H, 1248 MSR_SMM_FEATURE_CONTROL
Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only while in SMM.
Package
0Lock (SMM-RWO)
When set to ‘1’ locks this register from further changes.
1 Reserved.
2 SMM_Code_Chk_En (SMM-RW)
This control bit is available only if MSR_SMM_MCA_CAP[58] == 1. When
set to ‘0’ (default) none of the logical processors are prevented from
executing SMM code outside the ranges defined by the SMRR.
When set to ‘1’ any logical processor in the package that attempts to
execute SMM code not within the ranges defined by the SMRR will assert
an unrecoverable MCE.
63:3 Reserved.
Register Address: 4E2H, 1250 MSR_SMM_DELAYED
SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors in the package. Available only while in SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
Package
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its state in a long flow of internal
operation which delays servicing an interrupt. The corresponding bit will
be set at the start of long events such as: Microcode Update Load, C6,
WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each long event. The reset
value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0]
can be updated.
63:N Reserved.
Register Address: 4E3H, 1251 MSR_SMM_BLOCKED
SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in the package. Available only while in SMM.
Package
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-127
MODEL-SPECIFIC REGISTERS (MSRS)
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a processor core of its blocked state to service an SMI.
The corresponding bit will be set if the logical processor is in one of the
following states: Wait For SIPI or SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0]
can be updated.
63:N Reserved.
Register Address: 500H, 1280 IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support for ACM (R/O) Core
0Lock
See Section 39.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
15:1 Reserved.
23:16 SGX_SVN_SINIT
See Section 39.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
63:24 Reserved.
Register Address: 560H, 1376 IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W)
See Table 2-2.
Core
Register Address: 561H, 1377 IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W)
See Table 2-2.
Core
Register Address: 570H, 1392 IA32_RTIT_CTL
Trace Control Register (R/W) Core
0TraceEn
1CYCEn
2OS
3User
6:4 Reserved, must be zero.
7CR3Filter
8ToPA
Writing 0 will #GP if also setting TraceEn.
9MTCEn
10 TSCEn
11 DisRETC
12 Reserved, must be zero.
13 BranchEn
17:14 MTCFreq
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-128 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
18 Reserved, must be zero.
22:19 CycThresh
23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG
63:40 Reserved, must be zero.
Register Address: 571H, 1393 IA32_RTIT_STATUS
Tracing Status Register (R/W) Core
0FilterEn
Writes ignored.
1 ContextEn
Writes ignored.
2 TriggerEn
Writes ignored.
3 Reserved
4Error (R/W)
5Stopped
31:6 Reserved, must be zero.
48:32 PacketByteCnt
63:49 Reserved, must be zero.
Register Address: 572H, 1394 IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W) Core
4:0 Reserved
63:5 CR3[63:5] value to match.
Register Address: 580H, 1408 IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W) Core
63:0 See Table 2-2.
Register Address: 581H, 1409 IA32_RTIT_ADDR0_B
Region 0 End Address (R/W) Core
63:0 See Table 2-2.
Register Address: 582H, 1410 IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W) Core
63:0 See Table 2-2.
Register Address: 583H, 1411 IA32_RTIT_ADDR1_B
Region 1 End Address (R/W) Core
63:0 See Table 2-2.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-129
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
Package
3:0 Power Units
Power related information (in Watts) is in unit of 1W/2^PU; where PU is an
unsigned integer represented by bits 3:0. Default value is 1000b,
indicating power unit is in 3.9 milliWatts increment.
7:4 Reserved.
12:8 Energy Status Units
Energy related information (in Joules) is in unit of 1Joule/ (2^ESU); where
ESU is an unsigned integer represented by bits 12:8. Default value is
01110b, indicating energy unit is in 61 microJoules.
15:13 Reserved.
19:16 Time Unit
Time related information (in seconds) is in unit of 1S/2^TU; where TU is an
unsigned integer represented by bits 19:16. Default value is 1010b,
indicating power unit is in 0.977 millisecond.
63:20 Reserved.
Register Address: 60AH, 1546 MSR_PKGC3_IRTL
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C3 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. See Table 2-20 for supported time unit encodings.
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by the
processor for package C-sate management.
63:16 Reserved.
Register Address: 60BH, 1547 MSR_PKGC_IRTL1
Package C6/C7S Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or
C7S state.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C6 or C7S state.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-130 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. See Table 2-20 for supported time unit encodings.
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by the
processor for package C-sate management.
63:16 Reserved.
Register Address: 60CH, 1548 MSR_PKGC_IRTL2
Package C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C7
state.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C7 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. See Table 2-20 for supported time unit encodings.
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by the
processor for package C-sate management.
63:16 Reserved.
Register Address: 60DH, 1549 MSR_PKG_C2_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
Package
63:0 Package C2 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C2 states.
Count at the same frequency as the TSC.
Register Address: 610H, 1552 MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 611H, 1553 MSR_PKG_ENERGY_STATUS
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 613H, 1555 MSR_PKG_PERF_STATUS
PKG Perf Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 614H, 1556 MSR_PKG_POWER_INFO
PKG RAPL Parameters (R/W) Package
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-131
MODEL-SPECIFIC REGISTERS (MSRS)
14:0 Thermal Spec Power (R/W)
See Section 15.10.3, “Package RAPL Domain.”
15 Reserved.
30:16 Minimum Power (R/W)
See Section 15.10.3, “Package RAPL Domain.”
31 Reserved.
46:32 Maximum Power (R/W)
See Section 15.10.3, “Package RAPL Domain.”
47 Reserved.
54:48 Maximum Time Window (R/W)
Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where “Y” is the unsigned
integer value represented by bits 52:48, “Z” is an unsigned integer
represented by bits 54:53. “Time_Unit” is specified by the “Time Units”
field of MSR_RAPL_POWER_UNIT.
63:55 Reserved.
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 632H, 1586 MSR_PKG_C10_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
Package
63:0 Package C10 Residency Counter (R/O)
Value since last reset that the entire SOC is in an S0i3 state. Count at the
same frequency as the TSC.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 641H, 1601 MSR_PP1_ENERGY_STATUS
PP1 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 64CH, 1612 MSR_TURBO_ACTIVATION_RATIO
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-132 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
ConfigTDP Control (R/W) Package
7:0 MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8 Reserved.
31 TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is locked until a reset.
63:32 Reserved.
Register Address: 64FH, 1615 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
Package
0PROCHOT Status (R0)
When set, processor core frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
2 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system request due
to package-level power limiting PL1.
3 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system request due
to package-level power limiting PL2.
8:4 Reserved.
9 Core Power Limiting Status (R0)
When set, frequency is reduced below the operating system request due
to domain-level power limiting.
10 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from the Voltage Regulator.
11 Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system request due
to multi-core turbo limits.
12 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system request due
to electrical design point constraints (e.g., maximum electrical current
consumption).
13 Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system request due
to Turbo transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
14 Maximum Efficiency Frequency Status (R0)
When set, frequency is reduced below the maximum efficiency frequency.
15 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-133
MODEL-SPECIFIC REGISTERS (MSRS)
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting Status bit
has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24:20 Reserved.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30 Maximum Efficiency Frequency Log
When set, indicates that the Maximum Efficiency Frequency Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:31 Reserved.
Register Address: 680H, 1664 MSR_LASTBRANCH_0_FROM_IP
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-134 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 0 From IP (R/W)
One of 32 pairs of last branch record registers on the last branch record stack. The From_IP part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.6 and record format in Section 18.4.8.1.
Core
0:47 From Linear Address (R/W)
62:48 Signed extension of bits 47:0.
63 Mispred
Register Address: 681H, 1665 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 682H, 1666 MSR_LASTBRANCH_2_FROM_IP
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 683H, 1667 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 684H, 1668 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 685H, 1669 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 686H, 1670 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 687H, 1671 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 688H, 1672 MSR_LASTBRANCH_8_FROM_IP
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 689H, 1673 MSR_LASTBRANCH_9_FROM_IP
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 68AH, 1674 MSR_LASTBRANCH_10_FROM_IP
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 68BH, 1675 MSR_LASTBRANCH_11_FROM_IP
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-135
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 68CH, 1676 MSR_LASTBRANCH_12_FROM_IP
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 68DH, 1677 MSR_LASTBRANCH_13_FROM_IP
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 68EH, 1678 MSR_LASTBRANCH_14_FROM_IP
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 68FH, 1679 MSR_LASTBRANCH_15_FROM_IP
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 690H, 1680 MSR_LASTBRANCH_16_FROM_IP
Last Branch Record 16 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 691H, 1681 MSR_LASTBRANCH_17_FROM_IP
Last Branch Record 17 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 692H, 1682 MSR_LASTBRANCH_18_FROM_IP
Last Branch Record 18 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 693H, 1683 MSR_LASTBRANCH_19_FROM_IP
Last Branch Record 19From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 694H, 1684 MSR_LASTBRANCH_20_FROM_IP
Last Branch Record 20 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 695H, 1685 MSR_LASTBRANCH_21_FROM_IP
Last Branch Record 21 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 696H, 1686 MSR_LASTBRANCH_22_FROM_IP
Last Branch Record 22 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 697H, 1687 MSR_LASTBRANCH_23_FROM_IP
Last Branch Record 23 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 698H, 1688 MSR_LASTBRANCH_24_FROM_IP
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-136 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 24 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 699H, 1689 MSR_LASTBRANCH_25_FROM_IP
Last Branch Record 25 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 69AH, 1690 MSR_LASTBRANCH_26_FROM_IP
Last Branch Record 26 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 69BH, 1691 MSR_LASTBRANCH_27_FROM_IP
Last Branch Record 27 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 69CH, 1692 MSR_LASTBRANCH_28_FROM_IP
Last Branch Record 28 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 69DH, 1693 MSR_LASTBRANCH_29_FROM_IP
Last Branch Record 29 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 69EH, 1694 MSR_LASTBRANCH_30_FROM_IP
Last Branch Record 30 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 69FH, 1695 MSR_LASTBRANCH_31_FROM_IP
Last Branch Record 31 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Core
Register Address: 6C0H, 1728 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of 32 pairs of last branch record registers on the last branch record stack. The To_IP part of the stack contains
pointers to the Destination instruction and elapsed cycles from last LBR update. See Section 18.6.
Core
0:47 Target Linear Address (R/W)
63:48 Elapsed cycles from last update to the LBR.
Register Address: 6C1H, 1729 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C2H, 1730 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C3H, 1731 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C4H, 1732 MSR_LASTBRANCH_4_TO_IP
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-137
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C5H, 1733 MSR_LASTBRANCH_5_TO_IP
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C6H, 1734 MSR_LASTBRANCH_6_TO_IP
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C7H, 1735 MSR_LASTBRANCH_7_TO_IP
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C8H, 1736 MSR_LASTBRANCH_8_TO_IP
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6C9H, 1737 MSR_LASTBRANCH_9_TO_IP
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6CAH, 1738 MSR_LASTBRANCH_10_TO_IP
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6CBH, 1739 MSR_LASTBRANCH_11_TO_IP
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6CCH, 1740 MSR_LASTBRANCH_12_TO_IP
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6CDH, 1741 MSR_LASTBRANCH_13_TO_IP
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6CEH, 1742 MSR_LASTBRANCH_14_TO_IP
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6CFH, 1743 MSR_LASTBRANCH_15_TO_IP
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D0H, 1744 MSR_LASTBRANCH_16_TO_IP
Last Branch Record 16 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D1H, 1745 MSR_LASTBRANCH_17_TO_IP
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-138 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D2H, 1746 MSR_LASTBRANCH_18_TO_IP
Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D3H, 1747 MSR_LASTBRANCH_19_TO_IP
Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D4H, 1748 MSR_LASTBRANCH_20_TO_IP
Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D5H, 1749 MSR_LASTBRANCH_21_TO_IP
Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D6H, 1750 MSR_LASTBRANCH_22_TO_IP
Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D7H, 1751 MSR_LASTBRANCH_23_TO_IP
Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D8H, 1752 MSR_LASTBRANCH_24_TO_IP
Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6D9H, 1753 MSR_LASTBRANCH_25_TO_IP
Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6DAH, 1754 MSR_LASTBRANCH_26_TO_IP
Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6DBH, 1755 MSR_LASTBRANCH_27_TO_IP
Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6DCH, 1756 MSR_LASTBRANCH_28_TO_IP
Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6DDH, 1757 MSR_LASTBRANCH_29_TO_IP
Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6DEH, 1758 MSR_LASTBRANCH_30_TO_IP
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-139
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 6DFH, 1759 MSR_LASTBRANCH_31_TO_IP
Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Core
Register Address: 802H, 2050 IA32_X2APIC_APICID
x2APIC ID register (R/O) Core
Register Address: 803H, 2051 IA32_X2APIC_VERSION
x2APIC Version register (R/O) Core
Register Address: 808H, 2056 IA32_X2APIC_TPR
x2APIC Task Priority register (R/W) Core
Register Address: 80AH, 2058 IA32_X2APIC_PPR
x2APIC Processor Priority register (R/O) Core
Register Address: 80BH, 2059 IA32_X2APIC_EOI
x2APIC EOI register (W/O) Core
Register Address: 80DH, 2061 IA32_X2APIC_LDR
x2APIC Logical Destination register (R/O) Core
Register Address: 80FH, 2063 IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector register (R/W) Core
Register Address: 810H, 2064 IA32_X2APIC_ISR0
x2APIC In-Service register bits [31:0] (R/O) Core
Register Address: 811H, 2065 IA32_X2APIC_ISR1
x2APIC In-Service register bits [63:32] (R/O) Core
Register Address: 812H, 2066 IA32_X2APIC_ISR2
x2APIC In-Service register bits [95:64] (R/O) Core
Register Address: 813H, 2067 IA32_X2APIC_ISR3
x2APIC In-Service register bits [127:96] (R/O) Core
Register Address: 814H, 2068 IA32_X2APIC_ISR4
x2APIC In-Service register bits [159:128] (R/O) Core
Register Address: 815H, 2069 IA32_X2APIC_ISR5
x2APIC In-Service register bits [191:160] (R/O) Core
Register Address: 816H, 2070 IA32_X2APIC_ISR6
x2APIC In-Service register bits [223:192] (R/O) Core
Register Address: 817H, 2071 IA32_X2APIC_ISR7
x2APIC In-Service register bits [255:224] (R/O) Core
Register Address: 818H, 2072 IA32_X2APIC_TMR0
x2APIC Trigger Mode register bits [31:0] (R/O) Core
Register Address: 819H, 2073 IA32_X2APIC_TMR1
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-140 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC Trigger Mode register bits [63:32] (R/O) Core
Register Address: 81AH, 2074 IA32_X2APIC_TMR2
x2APIC Trigger Mode register bits [95:64] (R/O) Core
Register Address: 81BH, 2075 IA32_X2APIC_TMR3
x2APIC Trigger Mode register bits [127:96] (R/O) Core
Register Address: 81CH, 2076 IA32_X2APIC_TMR4
x2APIC Trigger Mode register bits [159:128] (R/O) Core
Register Address: 81DH, 2077 IA32_X2APIC_TMR5
x2APIC Trigger Mode register bits [191:160] (R/O) Core
Register Address: 81EH, 2078 IA32_X2APIC_TMR6
x2APIC Trigger Mode register bits [223:192] (R/O) Core
Register Address: 81FH, 2079 IA32_X2APIC_TMR7
x2APIC Trigger Mode register bits [255:224] (R/O) Core
Register Address: 820H, 2080 IA32_X2APIC_IRR0
x2APIC Interrupt Request register bits [31:0] (R/O) Core
Register Address: 821H, 2081 IA32_X2APIC_IRR1
x2APIC Interrupt Request register bits [63:32] (R/O) Core
Register Address: 822H, 2082 IA32_X2APIC_IRR2
x2APIC Interrupt Request register bits [95:64] (R/O) Core
Register Address: 823H, 2083 IA32_X2APIC_IRR3
x2APIC Interrupt Request register bits [127:96] (R/O) Core
Register Address: 824H, 2084 IA32_X2APIC_IRR4
x2APIC Interrupt Request register bits [159:128] (R/O) Core
Register Address: 825H, 2085 IA32_X2APIC_IRR5
x2APIC Interrupt Request register bits [191:160] (R/O) Core
Register Address: 826H, 2086 IA32_X2APIC_IRR6
x2APIC Interrupt Request register bits [223:192] (R/O) Core
Register Address: 827H, 2087 IA32_X2APIC_IRR7
x2APIC Interrupt Request register bits [255:224] (R/O) Core
Register Address: 828H, 2088 IA32_X2APIC_ESR
x2APIC Error Status register (R/W) Core
Register Address: 82FH, 2095 IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check Interrupt register (R/W) Core
Register Address: 830H, 2096 IA32_X2APIC_ICR
x2APIC Interrupt Command register (R/W) Core
Register Address: 832H, 2098 IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt register (R/W) Core
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-141
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 833H, 2099 IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt register (R/W) Core
Register Address: 834H, 2100 IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor register (R/W) Core
Register Address: 835H, 2101 IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 register (R/W) Core
Register Address: 836H, 2102 IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 register (R/W) Core
Register Address: 837H, 2103 IA32_X2APIC_LVT_ERROR
x2APIC LVT Error register (R/W) Core
Register Address: 838H, 2104 IA32_X2APIC_INIT_COUNT
x2APIC Initial Count register (R/W) Core
Register Address: 839H, 2105 IA32_X2APIC_CUR_COUNT
x2APIC Current Count register (R/O) Core
Register Address: 83EH, 2110 IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration register (R/W) Core
Register Address: 83FH, 2111 IA32_X2APIC_SELF_IPI
x2APIC Self IPI register (W/O) Core
Register Address: C8FH, 3215 IA32_PQR_ASSOC
Resource Association Register (R/W) Core
31:0 Reserved.
33:32 CLOS (R/W)
63: 34 Reserved.
Register Address: D10H, 3344 IA32_L2_QOS_MASK_0
L2 Class Of Service Mask - CLOS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
Module
0:7 CBM: Bit vector of available L2 ways for CLOS 0 enforcement.
63:8 Reserved.
Register Address: D11H, 3345 IA32_L2_QOS_MASK_1
L2 Class Of Service Mask - CLOS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
Module
0:7 CBM: Bit vector of available L2 ways for CLOS 0 enforcement.
63:8 Reserved.
Register Address: D12H, 3346 IA32_L2_QOS_MASK_2
L2 Class Of Service Mask - CLOS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
Module
0:7 CBM: Bit vector of available L2 ways for CLOS 0 enforcement.
63:8 Reserved.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-142 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.6 MSRS IN INTEL ATOM® PROCESSORS BASED ON GOLDMONT PLUS
MICROARCHITECTURE
Intel Atom processors based on the Goldmont Plus microarchitecture support MSRs listed in Table 2-6, Table 2-12,
and Table 2-13. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_7AH; see Table
2-1. For an MSR listed in Table 2-13 that also appears in the model-specific tables of prior generations, Table 2-13
supersede prior generation tables.
In the Goldmont Plus microarchitecture, the scope column indicates the following: “Core” means each processor
core has a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit
field is shared by a subset of the processor cores in the physical package. The number of processor cores in this
subset is model specific and may differ between different processors. For all processors based on Goldmont Plus
microarchitecture, the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration
can be used to figure out which processors are in the same module. “Package” means all processor cores in the
physical package share the same MSR or bit interface.
Register Address: D13H, 3347 IA32_L2_QOS_MASK_3
L2 Class Of Service Mask - CLOS 3 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
Package
0:19 CBM: Bit vector of available L2 ways for CLOS 3 enforcement.
63:20 Reserved.
Register Address: D90H, 3472 IA32_BNDCFGS
See Table 2-2. Core
Register Address: DA0H, 3488 IA32_XSS
See Table 2-2. Core
See Table 2-6, and Table 2-12 for MSR definitions applicable to processors with a CPUID Signature DisplayFamily_DisplayModel value
of 06_5CH.
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
See Table 2-2.
Core
0Lock (R/WL)
1 Enable VMX inside SMX operation (R/WL)
2 Enable VMX outside SMX operation (R/WL)
14:8 SENTER local functions enables (R/WL)
15 SENTER global functions enable (R/WL)
17 SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime reconfiguration of SGX Launch
Control via IA32_SGXLEPUBKEYHASHn MSR.
Valid if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
Table 2-12. MSRs in Intel Atom® Processors Based on Goldmont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-143
MODEL-SPECIFIC REGISTERS (MSRS)
18 SGX global functions enable (R/WL)
63:19 Reserved.
Register Address: 8CH, 140 IA32_SGXLEPUBKEYHASH0
See Table 2-2. Core
Register Address: 8DH, 141 IA32_SGXLEPUBKEYHASH1
See Table 2-2. Core
Register Address: 8EH, 142 IA32_SGXLEPUBKEYHASH2
See Table 2-2. Core
Register Address: 8FH, 143 IA32_SGXLEPUBKEYHASH3
See Table 2-2. Core
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
(R/W) See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core
0 Enable PEBS trigger and recording for the programmed event (precise or
otherwise) on IA32_PMC0.
1 Enable PEBS trigger and recording for the programmed event (precise or
otherwise) on IA32_PMC1.
2 Enable PEBS trigger and recording for the programmed event (precise or
otherwise) on IA32_PMC2.
3 Enable PEBS trigger and recording for the programmed event (precise or
otherwise) on IA32_PMC3.
31:4 Reserved.
32 Enable PEBS trigger and recording for IA32_FIXED_CTR0.
33 Enable PEBS trigger and recording for IA32_FIXED_CTR1.
34 Enable PEBS trigger and recording for IA32_FIXED_CTR2.
63:35 Reserved.
Register Address: 570H, 1392 IA32_RTIT_CTL
Trace Control Register (R/W) Core
0TraceEn
1CYCEn
2OS
3User
4PwrEvtEn
5FUPonPTW
6FabricEn
7CR3Filter
8ToPA
Writing 0 will #GP if also setting TraceEn.
9MTCEn
10 TSCEn
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-144 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
11 DisRETC
12 PTWEn
13 BranchEn
17:14 MTCFreq
18 Reserved, must be zero.
22:19 CycThresh
23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG
63:40 Reserved, must be zero.
Register Address: 680H, 1664 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 From IP (R/W)
One of the three MSRs that make up the first entry of the 32-entry LBR stack. The From_IP part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus
Microarchitecture.”
Core
Register Address: 681H−69FH, 1665−
1695
MSR_LASTBRANCH_i_FROM_IP
Last Branch Record i From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP; i = 1-31.
Core
Register Address: 6C0H, 1728 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of the three MSRs that make up the first entry of the 32-entry LBR stack. The To_IP part of the stack contains
pointers to the Destination instruction. See also:
• Section 18.7, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based on Goldmont Plus
Microarchitecture.”
Core
Register Address: 6C1H−6DFH, 1729−
1759
MSR_LASTBRANCH_i_TO_IP
Last Branch Record i To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP; i = 1-31.
Core
Register Address: DC0H, 3520 MSR_LASTBRANCH_INFO_0
Last Branch Record 0 Additional Information (R/W)
One of the three MSRs that make up the first entry of the 32-entry LBR stack. This part of the stack contains flag and
elapsed cycle information. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1, “LBR Stack.”
Core
Register Address: DC1H, 3521 MSR_LASTBRANCH_INFO_1
Last Branch Record 1 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-145
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DC2H, 3522 MSR_LASTBRANCH_INFO_2
Last Branch Record 2 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC3H, 3523 MSR_LASTBRANCH_INFO_3
Last Branch Record 3 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC4H, 3524 MSR_LASTBRANCH_INFO_4
Last Branch Record 4 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC5H, 3525 MSR_LASTBRANCH_INFO_5
Last Branch Record 5 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC6H, 3526 MSR_LASTBRANCH_INFO_6
Last Branch Record 6 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC7H, 3527 MSR_LASTBRANCH_INFO_7
Last Branch Record 7 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC8H, 3528 MSR_LASTBRANCH_INFO_8
Last Branch Record 8 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DC9H, 3529 MSR_LASTBRANCH_INFO_9
Last Branch Record 9 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DCAH, 3530 MSR_LASTBRANCH_INFO_10
Last Branch Record 10 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DCBH, 3531 MSR_LASTBRANCH_INFO_11
Last Branch Record 11 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DCCH, 3532 MSR_LASTBRANCH_INFO_12
Last Branch Record 12 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DCDH, 3533 MSR_LASTBRANCH_INFO_13
Last Branch Record 13 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DCEH, 3534 MSR_LASTBRANCH_INFO_14
Last Branch Record 14 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-146 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DCFH, 3535 MSR_LASTBRANCH_INFO_15
Last Branch Record 15 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD0H, 3536 MSR_LASTBRANCH_INFO_16
Last Branch Record 16 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD1H, 3537 MSR_LASTBRANCH_INFO_17
Last Branch Record 17 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD2H, 3538 MSR_LASTBRANCH_INFO_18
Last Branch Record 18 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD3H, 3539 MSR_LASTBRANCH_INFO_19
Last Branch Record 19 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD4H, 3520 MSR_LASTBRANCH_INFO_20
Last Branch Record 20 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD5H, 3521 MSR_LASTBRANCH_INFO_21
Last Branch Record 21 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD6H, 3522 MSR_LASTBRANCH_INFO_22
Last Branch Record 22 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD7H, 3523 MSR_LASTBRANCH_INFO_23
Last Branch Record 23 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD8H, 3524 MSR_LASTBRANCH_INFO_24
Last Branch Record 24 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DD9H, 3525 MSR_LASTBRANCH_INFO_25
Last Branch Record 25 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DDAH, 3526 MSR_LASTBRANCH_INFO_26
Last Branch Record 26 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DDBH, 3527 MSR_LASTBRANCH_INFO_27
Last Branch Record 27 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-147
MODEL-SPECIFIC REGISTERS (MSRS)
2.7 MSRS IN INTEL ATOM® PROCESSORS BASED ON TREMONT
MICROARCHITECTURE
Processors based on the Tremont microarchitecture support MSRs listed in Table 2-6, Table 2-12, Table 2-13, and
Table 2-14. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_86H, 06_96H, or
06_9CH; see Table 2-1. For an MSR listed in Table 2-14 that also appears in the model-specific tables of prior
generations, Table 2-14 supersede prior generation tables.
In the Tremont microarchitecture, the scope column indicates the following: “Core” means each processor core has
a separate MSR, or a bit field not shared with another processor core. “Module” means the MSR or the bit field is
shared by a subset of the processor cores in the physical package. The number of processor cores in this subset is
model specific and may differ between different processors. For all processors based on Tremont microarchitecture,
the L2 cache is also shared between cores in a module and thus CPUID leaf 04H enumeration can be used to figure
out which processors are in the same module. “Package” means all processor cores in the physical package share
the same MSR or bit interface.
Register Address: DDCH, 3528 MSR_LASTBRANCH_INFO_28
Last Branch Record 28 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DDDH, 3529 MSR_LASTBRANCH_INFO_29
Last Branch Record 29 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DDEH, 3530 MSR_LASTBRANCH_INFO_30
Last Branch Record 30 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
Register Address: DDFH, 3531 MSR_LASTBRANCH_INFO_31
Last Branch Record 31 Additional Information (R/W)
See description of MSR_LASTBRANCH_INFO_0.
Core
See Table 2-6, Table 2-12, and Table 2-13 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7AH.
Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 33H, 51 MSR_MEMORY_CTRL
Memory Control Register Core
28:0 Reserved.
29 SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30 Reserved.
31 Reserved.
Register Address: CFH, 207 IA32_CORE_CAPABILITIES
Table 2-13. MSRs in Intel Atom® Processors Based on Goldmont Plus Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-148 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
IA32 Core Capabilities Register
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
Core
4:0 Reserved.
5 SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL (MSR
address 33H).
63:6 Reserved.
Register Address: 2A0H, 672 MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W) Core
2:0 MEMTYPE: PRMRR BASE Memory Type.
3 CONFIGURED: PRMRR BASE Configured.
11:4 Reserved.
51:12 BASE: PRMRR Base Address.
63:52 Reserved.
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
(R/W) See Table 2-2. See Section 20.6.2.4, “Processor Event Based Sampling (PEBS).” Core
n:0 Enable PEBS trigger and recording for the programmed event (precise or
otherwise) on IA32_PMCx. The maximum value n can be determined from
CPUID.0AH:EAX[15:8].
31:n+1 Reserved.
32+m:32 Enable PEBS trigger and recording for IA32_FIXED_CTRx. The maximum
value m can be determined from CPUID.0AH:EDX[4:0].
59:33+m Reserved.
60 Pend a PerfMon Interrupt (PMI) after each PEBS event.
62:61 Specifies PEBS output destination. Encodings:
00B: DS Save Area.
01B: Intel PT trace output. Supported if
IA32_PERF_CAPABILITIES.PEBS_OUTPUT_PT_AVAIL[16] and
CPUID.07H.0.EBX[25] are set.
10B: Reserved.
11B: Reserved.
63 Reserved.
Register Address: 1309H−130BH,
4873
−4875
MSR_RELOAD_FIXED_CTRx
Reload value for IA32_FIXED_CTRx (R/W)
47:0 Value loaded into IA32_FIXED_CTRx when a PEBS record is generated
while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT = 01B in
IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
63:48 Reserved.
Register Address: 14C1H−14C4H,
5313−5316
MSR_RELOAD_PMCx
Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-149
MODEL-SPECIFIC REGISTERS (MSRS)
2.8 MSRS IN PROCESSORS BASED ON NEHALEM MICROARCHITECTURE
Table 2-15 lists model-specific registers (MSRs) that are common for Nehalem microarchitecture. These include the
Intel Core i7 and i5 processor family. These processors have a CPUID Signature DisplayFamily_DisplayModel value
of 06_1AH, 06_1EH, 06_1FH, or 06_2EH; see Table 2-1. Additional MSRs specific to processors with a CPUID
Signature DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH are listed in Table 2-16. Some MSRs
listed in these tables are used by BIOS. More information about these MSR can be found at http://biosbits.org.
The column “Scope” represents the package/core/thread scope of individual bit field of an MSR. “Thread” means
this bit field must be programmed on each logical processor independently. “Core” means the bit field must be
programmed on each processor core independently, logical processors in the same core will be affected by change
of this bit on the other logical processor in the same core. “Package” means the bit field must be programmed once
for each physical package. Change of a bit filed with a package scope will affect all logical processors in that phys-
ical package.
Reload value for IA32_PMCx (R/W) Core
47:0 Value loaded into IA32_PMCx when a PEBS record is generated while
PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in IA32_PEBS_ENABLE,
and PMCx is overflowed.
63:48 Reserved.
See Table 2-6, Table 2-12, Table 2-13, and Table 2-14 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_86H.
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Thread
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.” Thread
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Thread
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Thread
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
Package
Register Address: 17H, 23 MSR_PLATFORM_ID
Model Specific Platform ID (R) Package
49:0 Reserved.
52:50 See Table 2-2.
63:53 Reserved.
Register Address: 1BH, 27 IA32_APIC_BASE
Table 2-14. MSRs in Intel Atom® Processors Based on Tremont Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-150 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Thread
Register Address: 34H, 52 MSR_SMI_COUNT
SMI Counter (R/O) Thread
31:0 SMI Count (R/O)
Running count of SMI events since last RESET.
63:32 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
See Table 2-2.
Thread
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Core
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Thread
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
See Table 2-2.
Thread
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Thread
Register Address: C3H, 195 IA32_PMC2
Performance Counter Register
See Table 2-2.
Thread
Register Address: C4H, 196 IA32_PMC3
Performance Counter Register
See Table 2-2.
Thread
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs at. The invariant
TSC frequency can be computed by multiplying this ratio by 133.33 MHz.
Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
Package
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-151
MODEL-SPECIFIC REGISTERS (MSRS)
29 Programmable TDC-TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDC and TDP Limits for Turbo mode are
programmable. When set to 0, indicates TDC and TDP Limits for Turbo
mode are not programmable.
Package
39:30 Reserved.
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 133.33MHz.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States. See http://biosbits.org.
Core
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0 (no package C-sate support)
001b: C1 (Behavior is the same as 000b)
010b: C3
011b: C6
100b: C7
101b and 110b: Reserved
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
23:16 Reserved.
24 Interrupt filtering enable (R/W)
When set, processor cores in a deep C-State will wake only when the event
message is destined for that core. When 0, all processor cores in a deep C-
State will wake for an event message.
25 C3 state auto demotion enable (R/W)
When set, the processor will conditionally demote C6/C7 requests to C3
based on uncore auto-demote information.
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-152 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
26 C1 state auto demotion enable (R/W)
When set, the processor will conditionally demote C3/C6/C7 requests to C1
based on uncore auto-demote information.
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State Undemotion Enable (R/W)
63:31 Reserved.
Register Address: E4H, 228 MSR_PMG_IO_CAPTURE_BASE
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
Core
15:0 LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If IO
MWAIT Redirection is enabled, reads to this address will be consumed by
the power management logic and decoded to MWAIT instructions. When IO
port address redirection is enabled, this is the IO port address reported to
the OS/software.
18:16 C-state Range (R/W)
Specifies the encoding value of the maximum C-State code name to be
included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - C6 is the max C-State to include.
010b - C7 is the max C-State to include.
63:19 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Thread
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Thread
Register Address: FEH, 254 IA32_MTRRCAP
See Table 2-2. Thread
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Thread
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Thread
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Thread
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Thread
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-153
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Thread
0RIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) can
be used to restart the program. If cleared, the program cannot be reliably
restarted.
1EIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) is
directly associated with the error.
2MCIP
When set, bit indicates that a machine check has been generated. If a
second machine check is detected while this bit is still set, the processor
enters a shutdown state. Software should write this bit to 0 after
processing a machine check exception.
63:3 Reserved.
Register Address: 186H, 390 IA32_PERFEVTSEL0
See Table 2-2. Thread
7:0 Event Select
15:8 UMask
16 USR
17 OS
18 Edge
19 PC
20 INT
21 AnyThread
22 EN
23 INV
31:24 CMASK
63:32 Reserved.
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Thread
Register Address: 188H, 392 IA32_PERFEVTSEL2
See Table 2-2. Thread
Register Address: 189H, 393 IA32_PERFEVTSEL3
See Table 2-2. Thread
Register Address: 198H, 408 IA32_PERF_STATUS
See Table 2-2. Core
15:0 Current Performance State Value.
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-154 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:16 Reserved.
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Thread
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
Thread
0 Reserved.
3:1 On demand Clock Modulation Duty Cycle (R/W)
4 On demand Clock Modulation Enable (R/W)
63:5 Reserved.
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2.
Core
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Core
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0Fast-Strings Enable
See Table 2-2.
Thread
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2. Default value is 1.
Thread
6:4 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Thread
10:8 Reserved.
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Thread
12 Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
Thread
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
Package
18 ENABLE MONITOR FSM. (R/W) See Table 2-2. Thread
21:19 Reserved.
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-155
MODEL-SPECIFIC REGISTERS (MSRS)
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Thread
23 xTPR Message Disable (R/W)
See Table 2-2.
Thread
33:24 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Thread
37:35 Reserved.
38 Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost Technology,
the turbo mode feature is disabled and the IDA_Enable feature flag will be
clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
reports the processor’s support of turbo mode is enabled.
Note: The power-on default value is used by BIOS to detect hardware
support of turbo mode. If the power-on default value is 1, turbo mode is
available in the processor. If the power-on default value is 0, turbo mode is
not available.
Package
63:39 Reserved.
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Thread
15:0 Reserved.
23:16 Temperature Target (R)
The minimum temperature at which PROCHOT# will be asserted. The value
is degrees C.
63:24 Reserved.
Register Address: 1A4H, 420 MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0 L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional lines of
code or data into the L2 cache.
Core
1 L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which fetches the cache
line that comprises a cache line pair (128 bytes).
Core
2 DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next cache
line into L1 data cache.
Core
3 DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which uses sequential load
history (based on instruction pointer of previous loads) to determine
whether to prefetch additional lines.
Core
63:4 Reserved.
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-156 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Offcore Response Event Select Register (R/W) Thread
Register Address: 1AAH, 426 MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control
Various model specific features enumeration. See http://biosbits.org.
0 EIST Hardware Coordination Disable (R/W)
When 0, enables hardware coordination of Enhanced Intel Speedstep
Technology request from processor cores. When 1, disables hardware
coordination of Enhanced Intel Speedstep Technology requests.
Package
1 Energy/Performance Bias Enable (R/W)
This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible
to software with Ring 0 privileges. This bit’s status (1 or 0) is also reflected
by CPUID.(EAX=06h):ECX[3].
Thread
63:2 Reserved.
Register Address: 1ACH, 428 MSR_TURBO_POWER_CURRENT_LIMIT
See http://biosbits.org.
14:0 TDP Limit (R/W)
TDP limit in 1/8 Watt granularity.
Package
15 TDP Limit Override Enable (R/W)
A value = 0 indicates override is not active; a value = 1 indicates override is
active.
Package
30:16 TDC Limit (R/W)
TDC limit in 1/8 Amp granularity.
Package
31 TDC Limit Override Enable (R/W)
A value = 0 indicates override is not active; a value = 1 indicates override is
active.
Package
63:32 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
63:32 Reserved.
Register Address: 1C8H, 456 MSR_LBR_SELECT
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-157
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
Core
0CPL_EQ_0
1 CPL_NEQ_0
2JCC
3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET
6NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
Thread
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
See Table 2-2.
Thread
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
Thread
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
Thread
Register Address: 1F2H, 498 IA32_SMRR_PHYSBASE
See Table 2-2. Core
Register Address: 1F3H, 499 IA32_SMRR_PHYSMASK
See Table 2-2. Core
Register Address: 1FCH, 508 MSR_POWER_CTL
Power Control Register
See http://biosbits.org.
Core
0 Reserved.
1 C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced
Intel SpeedStep Technology operating point when all execution cores enter
MWAIT (C1).
Package
63:2 Reserved.
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-158 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
See Table 2-2. Thread
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
See Table 2-2. Thread
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
See Table 2-2. Thread
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
See Table 2-2. Thread
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
See Table 2-2. Thread
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
See Table 2-2. Thread
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
See Table 2-2. Thread
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
See Table 2-2. Thread
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
See Table 2-2. Thread
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
See Table 2-2. Thread
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
See Table 2-2. Thread
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
See Table 2-2. Thread
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
See Table 2-2. Thread
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
See Table 2-2. Thread
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
See Table 2-2. Thread
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
See Table 2-2. Thread
Register Address: 210H, 528 IA32_MTRR_PHYSBASE8
See Table 2-2. Thread
Register Address: 211H, 529 IA32_MTRR_PHYSMASK8
See Table 2-2. Thread
Register Address: 212H, 530 IA32_MTRR_PHYSBASE9
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-159
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Thread
Register Address: 213H, 531 IA32_MTRR_PHYSMASK9
See Table 2-2. Thread
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
See Table 2-2. Thread
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
See Table 2-2. Thread
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
See Table 2-2. Thread
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
See Table 2-2. Thread
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
See Table 2-2. Thread
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
See Table 2-2. Thread
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
See Table 2-2. Thread
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
See Table 2-2. Thread
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
See Table 2-2. Thread
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
See Table 2-2. Thread
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
See Table 2-2. Thread
Register Address: 277H, 631 IA32_PAT
See Table 2-2. Thread
Register Address: 280H, 640 IA32_MC0_CTL2
See Table 2-2. Package
Register Address: 281H, 641 IA32_MC1_CTL2
See Table 2-2. Package
Register Address: 282H, 642 IA32_MC2_CTL2
See Table 2-2. Core
Register Address: 283H, 643 IA32_MC3_CTL2
See Table 2-2. Core
Register Address: 284H, 644 IA32_MC4_CTL2
See Table 2-2. Core
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-160 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 285H, 645 IA32_MC5_CTL2
See Table 2-2. Core
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 287H, 647 IA32_MC7_CTL2
See Table 2-2. Package
Register Address: 288H, 648 IA32_MC8_CTL2
See Table 2-2. Package
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2.
Thread
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
Thread
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
Thread
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
Thread
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Thread
5:0 LBR Format
See Table 2-2.
6 PEBS Record Format
7 PEBSSaveArchRegs
See Table 2-2.
11:8 PEBS_REC_FORMAT
See Table 2-2.
12 SMM_FREEZE
See Table 2-2.
63:13 Reserved.
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
Thread
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Thread
Register Address: 38EH, 910 MSR_PERF_GLOBAL_STATUS
Provides single-bit status used by software to query the overflow condition of each performance counter. (R/O) Thread
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-161
MODEL-SPECIFIC REGISTERS (MSRS)
61 UNC_Ovf
Uncore overflowed if 1.
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Thread
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2. See Section 20.6.2.2, “Global Counter Control Facilities.” Allows software to clear counter overflow
conditions on any combination of fixed-function PMCs (IA32_FIXED_CTRx) or general-purpose PMCs via a single
WRMSR.
Thread
Register Address: 390H, 912 MSR_PERF_GLOBAL_OVF_CTRL
(R/W) Thread
61 CLR_UNC_Ovf
Set 1 to clear UNC_Ovf.
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).” Thread
0 Enable PEBS on IA32_PMC0 (R/W)
1 Enable PEBS on IA32_PMC1 (R/W)
2 Enable PEBS on IA32_PMC2 (R/W)
3 Enable PEBS on IA32_PMC3 (R/W)
31:4 Reserved.
32 Enable Load Latency on IA32_PMC0 (R/W)
33 Enable Load Latency on IA32_PMC1 (R/W)
34 Enable Load Latency on IA32_PMC2 (R/W)
35 Enable Load Latency on IA32_PMC3 (R/W)
63:36 Reserved.
Register Address: 3F6H, 1014 MSR_PEBS_LD_LAT
See Section 20.3.1.1.2, “Load Latency Performance Monitoring Facility.” Thread
15:0 Minimum threshold latency value of tagged load operation that will be
counted. (R/W)
63:36 Reserved.
Register Address: 3F8H, 1016 MSR_PKG_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C3 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C3 states.
Count at the same frequency as the TSC.
Register Address: 3F9H, 1017 MSR_PKG_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-162 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:0 Package C6 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C6 states.
Count at the same frequency as the TSC.
Register Address: 3FAH, 1018 MSR_PKG_C7_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C7 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C7 states.
Count at the same frequency as the TSC.
Register Address: 3FCH, 1020 MSR_CORE_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C3 states. Count
at the same frequency as the TSC.
Register Address: 3FDH, 1021 MSR_CORE_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C6 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C6 states. Count
at the same frequency as the TSC.
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Package
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Package
Register Address: 403H, 1027 IA32_MC0_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Package
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Package
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-163
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 407H, 1031 IA32_MC1_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Core
Register Address: 40BH, 1035 IA32_MC2_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Core
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Core
Register Address: 40DH, 1037 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 40EH, 1038 IA32_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Core
Register Address: 40FH, 1039 IA32_MC3_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Core
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Core
Register Address: 413H, 1043 IA32_MC4_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Core
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-164 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 417H, 1047 IA32_MC5_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Core
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 420H, 1056 IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 421H, 1057 IA32_MC8_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 422H, 1058 IA32_MC8_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 423H, 1059 IA32_MC8_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2 and Appendix A.1, “Basic VMX Information.”
Thread
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-based VM-execution Controls (R/O)
See Table 2-2 and Appendix A.3, “VM-Execution Controls.”
Thread
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Thread
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-165
MODEL-SPECIFIC REGISTERS (MSRS)
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2 and Appendix A.4, “VM-Exit Controls.”
Thread
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Table 2-2 and Appendix A.5, “VM-Entry Controls.”
Thread
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 2-2 and Appendix A.6, “Miscellaneous Data.”
Thread
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”
Thread
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”
Thread
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”
Thread
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”
Thread
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2 and Appendix A.9, “VMCS Enumeration.”
Thread
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Thread
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”
Thread
Register Address: 680H, 1664 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on the last branch record stack. The From_IP part of the stack
contains pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• See Section 18.9.1 and record format in Section 18.4.8.1.
Thread
Register Address: 681H, 1665 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 682H, 1666 MSR_LASTBRANCH_2_FROM_IP
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-166 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 683H, 1667 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 684H, 1668 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 685H, 1669 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 686H, 1670 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 687H, 1671 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 688H, 1672 MSR_LASTBRANCH_8_FROM_IP
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 689H, 1673 MSR_LASTBRANCH_9_FROM_IP
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68AH, 1674 MSR_LASTBRANCH_10_FROM_IP
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68BH, 1675 MSR_LASTBRANCH_11_FROM_IP
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68CH, 1676 MSR_LASTBRANCH_12_FROM_IP
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68DH, 1677 MSR_LASTBRANCH_13_FROM_IP
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68EH, 1678 MSR_LASTBRANCH_14_FROM_IP
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68FH, 1679 MSR_LASTBRANCH_15_FROM_IP
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-167
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 6C0H, 1728 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the destination instruction.
Thread
Register Address: 6C1H, 1729 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C2H, 1730 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C3H, 1731 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C4H, 1732 MSR_LASTBRANCH_4_TO_IP
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C5H, 1733 MSR_LASTBRANCH_5_TO_IP
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C6H, 1734 MSR_LASTBRANCH_6_TO_IP
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C7H, 1735 MSR_LASTBRANCH_7_TO_IP
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C8H, 1736 MSR_LASTBRANCH_8_TO_IP
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C9H, 1737 MSR_LASTBRANCH_9_TO_IP
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CAH, 1738 MSR_LASTBRANCH_10_TO_IP
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CBH, 1739 MSR_LASTBRANCH_11_TO_IP
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-168 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6CCH, 1740 MSR_LASTBRANCH_12_TO_IP
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CDH, 1741 MSR_LASTBRANCH_13_TO_IP
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CEH, 1742 MSR_LASTBRANCH_14_TO_IP
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CFH, 1743 MSR_LASTBRANCH_15_TO_IP
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 802H, 2050 IA32_X2APIC_APICID
x2APIC ID Register (R/O) Thread
Register Address: 803H, 2051 IA32_X2APIC_VERSION
x2APIC Version Register (R/O) Thread
Register Address: 808H, 2056 IA32_X2APIC_TPR
x2APIC Task Priority Register (R/W) Thread
Register Address: 80AH, 2058 IA32_X2APIC_PPR
x2APIC Processor Priority Register (R/O) Thread
Register Address: 80BH, 2059 IA32_X2APIC_EOI
x2APIC EOI Register (W/O) Thread
Register Address: 80DH, 2061 IA32_X2APIC_LDR
x2APIC Logical Destination Register (R/O) Thread
Register Address: 80FH, 2063 IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector Register (R/W) Thread
Register Address: 810H, 2064 IA32_X2APIC_ISR0
x2APIC In-Service Register Bits [31:0] (R/O) Thread
Register Address: 811H, 2065 IA32_X2APIC_ISR1
x2APIC In-Service Register Bits [63:32] (R/O) Thread
Register Address: 812H, 2066 IA32_X2APIC_ISR2
x2APIC In-Service Register Bits [95:64] (R/O) Thread
Register Address: 813H, 2067 IA32_X2APIC_ISR3
x2APIC In-Service Register Bits [127:96] (R/O) Thread
Register Address: 814H, 2068 IA32_X2APIC_ISR4
x2APIC In-Service Register Bits [159:128] (R/O) Thread
Register Address: 815H, 2069 IA32_X2APIC_ISR5
x2APIC In-Service Register Bits [191:160] (R/O) Thread
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-169
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 816H, 2070 IA32_X2APIC_ISR6
x2APIC In-Service Register Bits [223:192] (R/O) Thread
Register Address: 817H, 2071 IA32_X2APIC_ISR7
x2APIC In-Service Register Bits [255:224] (R/O) Thread
Register Address: 818H, 2072 IA32_X2APIC_TMR0
x2APIC Trigger Mode Register Bits [31:0] (R/O) Thread
Register Address: 819H, 2073 IA32_X2APIC_TMR1
x2APIC Trigger Mode Register Bits [63:32] (R/O) Thread
Register Address: 81AH, 2074 IA32_X2APIC_TMR2
x2APIC Trigger Mode Register Bits [95:64] (R/O) Thread
Register Address: 81BH, 2075 IA32_X2APIC_TMR3
x2APIC Trigger Mode Register Bits [127:96] (R/O) Thread
Register Address: 81CH, 2076 IA32_X2APIC_TMR4
x2APIC Trigger Mode Register Bits [159:128] (R/O) Thread
Register Address: 81DH, 2077 IA32_X2APIC_TMR5
x2APIC Trigger Mode Register Bits [191:160] (R/O) Thread
Register Address: 81EH, 2078 IA32_X2APIC_TMR6
x2APIC Trigger Mode Register Bits [223:192] (R/O) Thread
Register Address: 81FH, 2079 IA32_X2APIC_TMR7
x2APIC Trigger Mode Register Bits [255:224] (R/O) Thread
Register Address: 820H, 2080 IA32_X2APIC_IRR0
x2APIC Interrupt Request Register Bits [31:0] (R/O) Thread
Register Address: 821H, 2081 IA32_X2APIC_IRR1
x2APIC Interrupt Request Register Bits [63:32] (R/O) Thread
Register Address: 822H, 2082 IA32_X2APIC_IRR2
x2APIC Interrupt Request Register Bits [95:64] (R/O) Thread
Register Address: 823H, 2083 IA32_X2APIC_IRR3
x2APIC Interrupt Request Register Bits [127:96] (R/O) Thread
Register Address: 824H, 2084 IA32_X2APIC_IRR4
x2APIC Interrupt Request Register Bits [159:128] (R/O) Thread
Register Address: 825H, 2085 IA32_X2APIC_IRR5
x2APIC Interrupt Request Register Bits [191:160] (R/O) Thread
Register Address: 826H, 2086 IA32_X2APIC_IRR6
x2APIC Interrupt Request Register Bits [223:192] (R/O) Thread
Register Address: 827H, 2087 IA32_X2APIC_IRR7
x2APIC Interrupt Request Register Bits [255:224] (R/O) Thread
Register Address: 828H, 2088 IA32_X2APIC_ESR
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-170 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC Error Status Register (R/W) Thread
Register Address: 82FH, 2095 IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check Interrupt Register (R/W) Thread
Register Address: 830H, 2096 IA32_X2APIC_ICR
x2APIC Interrupt Command Register (R/W) Thread
Register Address: 832H, 2098 IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt Register (R/W) Thread
Register Address: 833H, 2099 IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt Register (R/W) Thread
Register Address: 834H, 2100 IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor Register (R/W) Thread
Register Address: 835H, 2101 IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 Register (R/W) Thread
Register Address: 836H, 2102 IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 Register (R/W) Thread
Register Address: 837H, 2103 IA32_X2APIC_LVT_ERROR
x2APIC LVT Error Register (R/W) Thread
Register Address: 838H, 2104 IA32_X2APIC_INIT_COUNT
x2APIC Initial Count Register (R/W) Thread
Register Address: 839H, 2105 IA32_X2APIC_CUR_COUNT
x2APIC Current Count Register (R/O) Thread
Register Address: 83EH, 2110 IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration Register (R/W) Thread
Register Address: 83FH, 2111 IA32_X2APIC_SELF_IPI
x2APIC Self IPI Register (W/O) Thread
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
Thread
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
Thread
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
Thread
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
Thread
Register Address: C000_0100H IA32_FS_BASE
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-171
MODEL-SPECIFIC REGISTERS (MSRS)
2.8.1 Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
The Intel Xeon Processor 5500 and 3400 series supports additional model-specific registers listed in Table 2-16.
These MSRs also apply to the Intel Core i7 and i5 processor family with a CPUID Signature
DisplayFamily_DisplayModel value of 06_1AH, 06_1EH, or 06_1FH; see Table 2-1.
Map of BASE Address of FS (R/W)
See Table 2-2.
Thread
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
Thread
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
Thread
Register Address: C000_0103H IA32_TSC_AUX
AUXILIARY TSC Signature (R/W)
See Table 2-2 and Section 18.17.2, “IA32_TSC_AUX Register and RDTSCP Support.”
Thread
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Actual maximum turbo frequency is multiplied by 133.33MHz.
(Not available in model 06_2EH.)
Package
7:0 Maximum Turbo Ratio Limit 1C (R/O)
Maximum Turbo mode ratio limit with 1 core active.
15:8 Maximum Turbo Ratio Limit 2C (R/O)
Maximum Turbo mode ratio limit with 2 cores active.
23:16 Maximum Turbo Ratio Limit 3C (R/O)
Maximum Turbo mode ratio limit with 3 cores active.
31:24 Maximum Turbo Ratio Limit 4C (R/O)
Maximum Turbo mode ratio limit with 4 cores active.
63:32 Reserved.
Register Address: 301H, 769 MSR_GQ_SNOOP_MESF
MSR_GQ_SNOOP_MESF Package
0From M to S (R/W)
1From E to S (R/W)
2From S to S (R/W)
3From F to S (R/W)
4From M to I (R/W)
Table 2-15. MSRs in Processors Based on Nehalem Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-172 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
5From E to I (R/W)
6From S to I (R/W)
7From F to I (R/W)
63:8 Reserved.
Register Address: 391H, 913 MSR_UNCORE_PERF_GLOBAL_CTRL
See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.” Package
Register Address: 392H, 914 MSR_UNCORE_PERF_GLOBAL_STATUS
See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.” Package
Register Address: 393H, 915 MSR_UNCORE_PERF_GLOBAL_OVF_CTRL
See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.” Package
Register Address: 394H, 916 MSR_UNCORE_FIXED_CTR0
See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.” Package
Register Address: 395H, 917 MSR_UNCORE_FIXED_CTR_CTRL
See Section 20.3.1.2.1, “Uncore Performance Monitoring Management Facility.” Package
Register Address: 396H, 918 MSR_UNCORE_ADDR_OPCODE_MATCH
See Section 20.3.1.2.3, “Uncore Address/Opcode Match MSR.” Package
Register Address: 3B0H, 960 MSR_UNCORE_PMC0
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B1H, 961 MSR_UNCORE_PMC1
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B2H, 962 MSR_UNCORE_PMC2
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B3H, 963 MSR_UNCORE_PMC3
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B4H, 964 MSR_UNCORE_PMC4
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B5H, 965 MSR_UNCORE_PMC5
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B6H, 966 MSR_UNCORE_PMC6
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3B7H, 967 MSR_UNCORE_PMC7
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C0H, 944 MSR_UNCORE_PERFEVTSEL0
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C1H, 945 MSR_UNCORE_PERFEVTSEL1
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C2H, 946 MSR_UNCORE_PERFEVTSEL2
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-173
MODEL-SPECIFIC REGISTERS (MSRS)
2.8.2 Additional MSRs in the Intel® Xeon® Processor 7500 Series
The Intel Xeon Processor 7500 series supports MSRs listed in Table 2-15 (except MSR address 1ADH) and addi-
tional model-specific registers listed in Table 2-17. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2EH.
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C3H, 947 MSR_UNCORE_PERFEVTSEL3
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C4H, 948 MSR_UNCORE_PERFEVTSEL4
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C5H, 949 MSR_UNCORE_PERFEVTSEL5
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C6H, 950 MSR_UNCORE_PERFEVTSEL6
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Register Address: 3C7H, 951 MSR_UNCORE_PERFEVTSEL7
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Reserved. Attempt to read/write will cause #UD. Package
Register Address: 289H, 649 IA32_MC9_CTL2
See Table 2-2. Package
Register Address: 28AH, 650 IA32_MC10_CTL2
See Table 2-2. Package
Register Address: 28BH, 651 IA32_MC11_CTL2
See Table 2-2. Package
Register Address: 28CH, 652 IA32_MC12_CTL2
See Table 2-2. Package
Register Address: 28DH, 653 IA32_MC13_CTL2
See Table 2-2. Package
Register Address: 28EH, 654 IA32_MC14_CTL2
See Table 2-2. Package
Register Address: 28FH, 655 IA32_MC15_CTL2
See Table 2-2. Package
Register Address: 290H, 656 IA32_MC16_CTL2
See Table 2-2. Package
Table 2-16. Additional MSRs in the Intel® Xeon® Processor 5500 and 3400 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-174 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 291H, 657 IA32_MC17_CTL2
See Table 2-2. Package
Register Address: 292H, 658 IA32_MC18_CTL2
See Table 2-2. Package
Register Address: 293H, 659 IA32_MC19_CTL2
See Table 2-2. Package
Register Address: 294H, 660 IA32_MC20_CTL2
See Table 2-2. Package
Register Address: 295H, 661 IA32_MC21_CTL2
See Table 2-2. Package
Register Address: 394H, 816 MSR_W_PMON_FIXED_CTR
Uncore W-box perfmon fixed counter. Package
Register Address: 395H, 817 MSR_W_PMON_FIXED_CTR_CTL
Uncore U-box perfmon fixed counter control MSR. Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 425H, 1061 IA32_MC9_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 426H, 1062 IA32_MC9_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 42BH, 1067 IA32_MC10_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 42CH, 1068 IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 42DH, 1069 IA32_MC11_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 42EH, 1070 IA32_MC11_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 42FH, 1071 IA32_MC11_MISC
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-175
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 430H, 1072 IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 431H, 1073 IA32_MC12_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 432H, 1074 IA32_MC12_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 433H, 1075 IA32_MC12_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 434H, 1076 IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 435H, 1077 IA32_MC13_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 436H, 1078 IA32_MC13_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 437H, 1079 IA32_MC13_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 438H, 1080 IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 439H, 1081 IA32_MC14_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 43AH, 1082 IA32_MC14_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 43BH, 1083 IA32_MC14_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 43CH, 1084 IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 43DH, 1085 IA32_MC15_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 43EH, 1086 IA32_MC15_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 43FH, 1087 IA32_MC15_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 440H, 1088 IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 441H, 1089 IA32_MC16_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-176 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 442H, 1090 IA32_MC16_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 443H, 1091 IA32_MC16_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 445H, 1093 IA32_MC17_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 449H, 1097 IA32_MC18_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 44FH, 1103 IA32_MC19_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 450H, 1104 IA32_MC20_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 451H, 1105 IA32_MC20_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 452H, 1106 IA32_MC20_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 453H, 1107 IA32_MC20_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 454H, 1108 IA32_MC21_CTL
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-177
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 455H, 1109 IA32_MC21_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 456H, 1110 IA32_MC21_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 457H, 1111 IA32_MC21_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: C00H, 3072 MSR_U_PMON_GLOBAL_CTRL
Uncore U-box perfmon global control MSR. Package
Register Address: C01H, 3073 MSR_U_PMON_GLOBAL_STATUS
Uncore U-box perfmon global status MSR. Package
Register Address: C02H, 3074 MSR_U_PMON_GLOBAL_OVF_CTRL
Uncore U-box perfmon global overflow control MSR. Package
Register Address: C10H, 3088 MSR_U_PMON_EVNT_SEL
Uncore U-box perfmon event select MSR. Package
Register Address: C11H, 3089 MSR_U_PMON_CTR
Uncore U-box perfmon counter MSR. Package
Register Address: C20H, 3104 MSR_B0_PMON_BOX_CTRL
Uncore B-box 0 perfmon local box control MSR. Package
Register Address: C21H, 3105 MSR_B0_PMON_BOX_STATUS
Uncore B-box 0 perfmon local box status MSR. Package
Register Address: C22H, 3106 MSR_B0_PMON_BOX_OVF_CTRL
Uncore B-box 0 perfmon local box overflow control MSR. Package
Register Address: C30H, 3120 MSR_B0_PMON_EVNT_SEL0
Uncore B-box 0 perfmon event select MSR. Package
Register Address: C31H, 3121 MSR_B0_PMON_CTR0
Uncore B-box 0 perfmon counter MSR. Package
Register Address: C32H, 3122 MSR_B0_PMON_EVNT_SEL1
Uncore B-box 0 perfmon event select MSR. Package
Register Address: C33H, 3123 MSR_B0_PMON_CTR1
Uncore B-box 0 perfmon counter MSR. Package
Register Address: C34H, 3124 MSR_B0_PMON_EVNT_SEL2
Uncore B-box 0 perfmon event select MSR. Package
Register Address: C35H, 3125 MSR_B0_PMON_CTR2
Uncore B-box 0 perfmon counter MSR. Package
Register Address: C36H, 3126 MSR_B0_PMON_EVNT_SEL3
Uncore B-box 0 perfmon event select MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-178 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C37H, 3127 MSR_B0_PMON_CTR3
Uncore B-box 0 perfmon counter MSR. Package
Register Address: C40H, 3136 MSR_S0_PMON_BOX_CTRL
Uncore S-box 0 perfmon local box control MSR. Package
Register Address: C41H, 3137 MSR_S0_PMON_BOX_STATUS
Uncore S-box 0 perfmon local box status MSR. Package
Register Address: C42H, 3138 MSR_S0_PMON_BOX_OVF_CTRL
Uncore S-box 0 perfmon local box overflow control MSR. Package
Register Address: C50H, 3152 MSR_S0_PMON_EVNT_SEL0
Uncore S-box 0 perfmon event select MSR. Package
Register Address: C51H, 3153 MSR_S0_PMON_CTR0
Uncore S-box 0 perfmon counter MSR. Package
Register Address: C52H, 3154 MSR_S0_PMON_EVNT_SEL1
Uncore S-box 0 perfmon event select MSR. Package
Register Address: C53H, 3155 MSR_S0_PMON_CTR1
Uncore S-box 0 perfmon counter MSR. Package
Register Address: C54H, 3156 MSR_S0_PMON_EVNT_SEL2
Uncore S-box 0 perfmon event select MSR. Package
Register Address: C55H, 3157 MSR_S0_PMON_CTR2
Uncore S-box 0 perfmon counter MSR. Package
Register Address: C56H, 3158 MSR_S0_PMON_EVNT_SEL3
Uncore S-box 0 perfmon event select MSR. Package
Register Address: C57H, 3159 MSR_S0_PMON_CTR3
Uncore S-box 0 perfmon counter MSR. Package
Register Address: C60H, 3168 MSR_B1_PMON_BOX_CTRL
Uncore B-box 1 perfmon local box control MSR. Package
Register Address: C61H, 3169 MSR_B1_PMON_BOX_STATUS
Uncore B-box 1 perfmon local box status MSR. Package
Register Address: C62H, 3170 MSR_B1_PMON_BOX_OVF_CTRL
Uncore B-box 1 perfmon local box overflow control MSR. Package
Register Address: C70H, 3184 MSR_B1_PMON_EVNT_SEL0
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C71H, 3185 MSR_B1_PMON_CTR0
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C72H, 3186 MSR_B1_PMON_EVNT_SEL1
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C73H, 3187 MSR_B1_PMON_CTR1
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-179
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C74H, 3188 MSR_B1_PMON_EVNT_SEL2
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C75H, 3189 MSR_B1_PMON_CTR2
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C76H, 3190 MSR_B1_PMON_EVNT_SEL3
Uncore B-box 1vperfmon event select MSR. Package
Register Address: C77H, 3191 MSR_B1_PMON_CTR3
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C80H, 3120 MSR_W_PMON_BOX_CTRL
Uncore W-box perfmon local box control MSR. Package
Register Address: C81H, 3121 MSR_W_PMON_BOX_STATUS
Uncore W-box perfmon local box status MSR. Package
Register Address: C82H, 3122 MSR_W_PMON_BOX_OVF_CTRL
Uncore W-box perfmon local box overflow control MSR. Package
Register Address: C90H, 3136 MSR_W_PMON_EVNT_SEL0
Uncore W-box perfmon event select MSR. Package
Register Address: C91H, 3137 MSR_W_PMON_CTR0
Uncore W-box perfmon counter MSR. Package
Register Address: C92H, 3138 MSR_W_PMON_EVNT_SEL1
Uncore W-box perfmon event select MSR. Package
Register Address: C93H, 3139 MSR_W_PMON_CTR1
Uncore W-box perfmon counter MSR. Package
Register Address: C94H, 3140 MSR_W_PMON_EVNT_SEL2
Uncore W-box perfmon event select MSR. Package
Register Address: C95H, 3141 MSR_W_PMON_CTR2
Uncore W-box perfmon counter MSR. Package
Register Address: C96H, 3142 MSR_W_PMON_EVNT_SEL3
Uncore W-box perfmon event select MSR. Package
Register Address: C97H, 3143 MSR_W_PMON_CTR3
Uncore W-box perfmon counter MSR. Package
Register Address: CA0H, 3232 MSR_M0_PMON_BOX_CTRL
Uncore M-box 0 perfmon local box control MSR. Package
Register Address: CA1H, 3233 MSR_M0_PMON_BOX_STATUS
Uncore M-box 0 perfmon local box status MSR. Package
Register Address: CA2H, 3234 MSR_M0_PMON_BOX_OVF_CTRL
Uncore M-box 0 perfmon local box overflow control MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-180 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: CA4H, 3236 MSR_M0_PMON_TIMESTAMP
Uncore M-box 0 perfmon time stamp unit select MSR. Package
Register Address: CA5H, 3237 MSR_M0_PMON_DSP
Uncore M-box 0 perfmon DSP unit select MSR. Package
Register Address: CA6H, 3238 MSR_M0_PMON_ISS
Uncore M-box 0 perfmon ISS unit select MSR. Package
Register Address: CA7H, 3239 MSR_M0_PMON_MAP
Uncore M-box 0 perfmon MAP unit select MSR. Package
Register Address: CA8H, 3240 MSR_M0_PMON_MSC_THR
Uncore M-box 0 perfmon MIC THR select MSR. Package
Register Address: CA9H, 3241 MSR_M0_PMON_PGT
Uncore M-box 0 perfmon PGT unit select MSR. Package
Register Address: CAAH, 3242 MSR_M0_PMON_PLD
Uncore M-box 0 perfmon PLD unit select MSR. Package
Register Address: CABH, 3243 MSR_M0_PMON_ZDP
Uncore M-box 0 perfmon ZDP unit select MSR. Package
Register Address: CB0H, 3248 MSR_M0_PMON_EVNT_SEL0
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CB1H, 3249 MSR_M0_PMON_CTR0
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CB2H, 3250 MSR_M0_PMON_EVNT_SEL1
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CB3H, 3251 MSR_M0_PMON_CTR1
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CB4H, 3252 MSR_M0_PMON_EVNT_SEL2
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CB5H, 3253 MSR_M0_PMON_CTR2
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CB6H, 3254 MSR_M0_PMON_EVNT_SEL3
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CB7H, 3255 MSR_M0_PMON_CTR3
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CB8H, 3256 MSR_M0_PMON_EVNT_SEL4
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CB9H, 3257 MSR_M0_PMON_CTR4
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CBAH, 3258 MSR_M0_PMON_EVNT_SEL5
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-181
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore M-box 0 perfmon event select MSR. Package
Register Address: CBBH, 3259 MSR_M0_PMON_CTR5
Uncore M-box 0 perfmon counter MSR. Package
Register Address: CC0H, 3264 MSR_S1_PMON_BOX_CTRL
Uncore S-box 1 perfmon local box control MSR. Package
Register Address: CC1H, 3265 MSR_S1_PMON_BOX_STATUS
Uncore S-box 1 perfmon local box status MSR. Package
Register Address: CC2H, 3266 MSR_S1_PMON_BOX_OVF_CTRL
Uncore S-box 1 perfmon local box overflow control MSR. Package
Register Address: CD0H, 3280 MSR_S1_PMON_EVNT_SEL0
Uncore S-box 1 perfmon event select MSR. Package
Register Address: CD1H, 3281 MSR_S1_PMON_CTR0
Uncore S-box 1 perfmon counter MSR. Package
Register Address: CD2H, 3282 MSR_S1_PMON_EVNT_SEL1
Uncore S-box 1 perfmon event select MSR. Package
Register Address: CD3H, 3283 MSR_S1_PMON_CTR1
Uncore S-box 1 perfmon counter MSR. Package
Register Address: CD4H, 3284 MSR_S1_PMON_EVNT_SEL2
Uncore S-box 1 perfmon event select MSR. Package
Register Address: CD5H, 3285 MSR_S1_PMON_CTR2
Uncore S-box 1 perfmon counter MSR. Package
Register Address: CD6H, 3286 MSR_S1_PMON_EVNT_SEL3
Uncore S-box 1 perfmon event select MSR. Package
Register Address: CD7H, 3287 MSR_S1_PMON_CTR3
Uncore S-box 1 perfmon counter MSR. Package
Register Address: CE0H, 3296 MSR_M1_PMON_BOX_CTRL
Uncore M-box 1 perfmon local box control MSR. Package
Register Address: CE1H, 3297 MSR_M1_PMON_BOX_STATUS
Uncore M-box 1 perfmon local box status MSR. Package
Register Address: CE2H, 3298 MSR_M1_PMON_BOX_OVF_CTRL
Uncore M-box 1 perfmon local box overflow control MSR. Package
Register Address: CE4H, 3300 MSR_M1_PMON_TIMESTAMP
Uncore M-box 1 perfmon time stamp unit select MSR. Package
Register Address: CE5H, 3301 MSR_M1_PMON_DSP
Uncore M-box 1 perfmon DSP unit select MSR. Package
Register Address: CE6H, 3302 MSR_M1_PMON_ISS
Uncore M-box 1 perfmon ISS unit select MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-182 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: CE7H, 3303 MSR_M1_PMON_MAP
Uncore M-box 1 perfmon MAP unit select MSR. Package
Register Address: CE8H, 3304 MSR_M1_PMON_MSC_THR
Uncore M-box 1 perfmon MIC THR select MSR. Package
Register Address: CE9H, 3305 MSR_M1_PMON_PGT
Uncore M-box 1 perfmon PGT unit select MSR. Package
Register Address: CEAH, 3306 MSR_M1_PMON_PLD
Uncore M-box 1 perfmon PLD unit select MSR. Package
Register Address: CEBH, 3307 MSR_M1_PMON_ZDP
Uncore M-box 1 perfmon ZDP unit select MSR. Package
Register Address: CF0H, 3312 MSR_M1_PMON_EVNT_SEL0
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CF1H, 3313 MSR_M1_PMON_CTR0
Uncore M-box 1 perfmon counter MSR. Package
Register Address: CF2H, 3314 MSR_M1_PMON_EVNT_SEL1
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CF3H, 3315 MSR_M1_PMON_CTR1
Uncore M-box 1 perfmon counter MSR. Package
Register Address: CF4H, 3316 MSR_M1_PMON_EVNT_SEL2
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CF5H, 3317 MSR_M1_PMON_CTR2
Uncore M-box 1 perfmon counter MSR. Package
Register Address: CF6H, 3318 MSR_M1_PMON_EVNT_SEL3
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CF7H, 3319 MSR_M1_PMON_CTR3
Uncore M-box 1 perfmon counter MSR. Package
Register Address: CF8H, 3320 MSR_M1_PMON_EVNT_SEL4
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CF9H, 3321 MSR_M1_PMON_CTR4
Uncore M-box 1 perfmon counter MSR. Package
Register Address: CFAH, 3322 MSR_M1_PMON_EVNT_SEL5
Uncore M-box 1 perfmon event select MSR. Package
Register Address: CFBH, 3323 MSR_M1_PMON_CTR5
Uncore M-box 1 perfmon counter MSR. Package
Register Address: D00H, 3328 MSR_C0_PMON_BOX_CTRL
Uncore C-box 0 perfmon local box control MSR. Package
Register Address: D01H, 3329 MSR_C0_PMON_BOX_STATUS
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-183
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 0 perfmon local box status MSR. Package
Register Address: D02H, 3330 MSR_C0_PMON_BOX_OVF_CTRL
Uncore C-box 0 perfmon local box overflow control MSR. Package
Register Address: D10H, 3344 MSR_C0_PMON_EVNT_SEL0
Uncore C-box 0 perfmon event select MSR. Package
Register Address: D11H, 3345 MSR_C0_PMON_CTR0
Uncore C-box 0 perfmon counter MSR. Package
Register Address: D12H, 3346 MSR_C0_PMON_EVNT_SEL1
Uncore C-box 0 perfmon event select MSR. Package
Register Address: D13H, 3347 MSR_C0_PMON_CTR1
Uncore C-box 0 perfmon counter MSR. Package
Register Address: D14H, 3348 MSR_C0_PMON_EVNT_SEL2
Uncore C-box 0 perfmon event select MSR. Package
Register Address: D15H, 3349 MSR_C0_PMON_CTR2
Uncore C-box 0 perfmon counter MSR. Package
Register Address: D16H, 3350 MSR_C0_PMON_EVNT_SEL3
Uncore C-box 0 perfmon event select MSR. Package
Register Address: D17H, 3351 MSR_C0_PMON_CTR3
Uncore C-box 0 perfmon counter MSR. Package
Register Address: D18H, 3352 MSR_C0_PMON_EVNT_SEL4
Uncore C-box 0 perfmon event select MSR. Package
Register Address: D19H, 3353 MSR_C0_PMON_CTR4
Uncore C-box 0 perfmon counter MSR. Package
Register Address: D1AH, 3354 MSR_C0_PMON_EVNT_SEL5
Uncore C-box 0 perfmon event select MSR. Package
Register Address: D1BH, 3355 MSR_C0_PMON_CTR5
Uncore C-box 0 perfmon counter MSR. Package
Register Address: D20H, 3360 MSR_C4_PMON_BOX_CTRL
Uncore C-box 4 perfmon local box control MSR. Package
Register Address: D21H, 3361 MSR_C4_PMON_BOX_STATUS
Uncore C-box 4 perfmon local box status MSR. Package
Register Address: D22H, 3362 MSR_C4_PMON_BOX_OVF_CTRL
Uncore C-box 4 perfmon local box overflow control MSR. Package
Register Address: D30H, 3376 MSR_C4_PMON_EVNT_SEL0
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D31H, 3377 MSR_C4_PMON_CTR0
Uncore C-box 4 perfmon counter MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-184 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D32H, 3378 MSR_C4_PMON_EVNT_SEL1
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D33H, 3379 MSR_C4_PMON_CTR1
Uncore C-box 4 perfmon counter MSR. Package
Register Address: D34H, 3380 MSR_C4_PMON_EVNT_SEL2
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D35H, 3381 MSR_C4_PMON_CTR2
Uncore C-box 4 perfmon counter MSR. Package
Register Address: D36H, 3382 MSR_C4_PMON_EVNT_SEL3
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D37H, 3383 MSR_C4_PMON_CTR3
Uncore C-box 4 perfmon counter MSR. Package
Register Address: D38H, 3384 MSR_C4_PMON_EVNT_SEL4
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D39H, 3385 MSR_C4_PMON_CTR4
Uncore C-box 4 perfmon counter MSR. Package
Register Address: D3AH, 3386 MSR_C4_PMON_EVNT_SEL5
Uncore C-box 4 perfmon event select MSR. Package
Register Address: D3BH, 3387 MSR_C4_PMON_CTR5
Uncore C-box 4 perfmon counter MSR. Package
Register Address: D40H, 3392 MSR_C2_PMON_BOX_CTRL
Uncore C-box 2 perfmon local box control MSR. Package
Register Address: D41H, 3393 MSR_C2_PMON_BOX_STATUS
Uncore C-box 2 perfmon local box status MSR. Package
Register Address: D42H, 3394 MSR_C2_PMON_BOX_OVF_CTRL
Uncore C-box 2 perfmon local box overflow control MSR. Package
Register Address: D50H, 3408 MSR_C2_PMON_EVNT_SEL0
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D51H, 3409 MSR_C2_PMON_CTR0
Uncore C-box 2 perfmon counter MSR. Package
Register Address: D52H, 3410 MSR_C2_PMON_EVNT_SEL1
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D53H, 3411 MSR_C2_PMON_CTR1
Uncore C-box 2 perfmon counter MSR. Package
Register Address: D54H, 3412 MSR_C2_PMON_EVNT_SEL2
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D55H, 3413 MSR_C2_PMON_CTR2
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-185
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 2 perfmon counter MSR. Package
Register Address: D56H, 3414 MSR_C2_PMON_EVNT_SEL3
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D57H, 3415 MSR_C2_PMON_CTR3
Uncore C-box 2 perfmon counter MSR. Package
Register Address: D58H, 3416 MSR_C2_PMON_EVNT_SEL4
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D59H, 3417 MSR_C2_PMON_CTR4
Uncore C-box 2 perfmon counter MSR. Package
Register Address: D5AH, 3418 MSR_C2_PMON_EVNT_SEL5
Uncore C-box 2 perfmon event select MSR. Package
Register Address: D5BH, 3419 MSR_C2_PMON_CTR5
Uncore C-box 2 perfmon counter MSR. Package
Register Address: D60H, 3424 MSR_C6_PMON_BOX_CTRL
Uncore C-box 6 perfmon local box control MSR. Package
Register Address: D61H, 3425 MSR_C6_PMON_BOX_STATUS
Uncore C-box 6 perfmon local box status MSR. Package
Register Address: D62H, 3426 MSR_C6_PMON_BOX_OVF_CTRL
Uncore C-box 6 perfmon local box overflow control MSR. Package
Register Address: D70H, 3440 MSR_C6_PMON_EVNT_SEL0
Uncore C-box 6 perfmon event select MSR. Package
Register Address: D71H, 3441 MSR_C6_PMON_CTR0
Uncore C-box 6 perfmon counter MSR. Package
Register Address: D72H, 3442 MSR_C6_PMON_EVNT_SEL1
Uncore C-box 6 perfmon event select MSR. Package
Register Address: D73H, 3443 MSR_C6_PMON_CTR1
Uncore C-box 6 perfmon counter MSR. Package
Register Address: D74H, 3444 MSR_C6_PMON_EVNT_SEL2
Uncore C-box 6 perfmon event select MSR. Package
Register Address: D75H, 3445 MSR_C6_PMON_CTR2
Uncore C-box 6 perfmon counter MSR. Package
Register Address: D76H, 3446 MSR_C6_PMON_EVNT_SEL3
Uncore C-box 6 perfmon event select MSR. Package
Register Address: D77H, 3447 MSR_C6_PMON_CTR3
Uncore C-box 6 perfmon counter MSR. Package
Register Address: D78H, 3448 MSR_C6_PMON_EVNT_SEL4
Uncore C-box 6 perfmon event select MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-186 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D79H, 3449 MSR_C6_PMON_CTR4
Uncore C-box 6 perfmon counter MSR. Package
Register Address: D7AH, 3450 MSR_C6_PMON_EVNT_SEL5
Uncore C-box 6 perfmon event select MSR. Package
Register Address: D7BH, 3451 MSR_C6_PMON_CTR5
Uncore C-box 6 perfmon counter MSR. Package
Register Address: D80H, 3456 MSR_C1_PMON_BOX_CTRL
Uncore C-box 1 perfmon local box control MSR. Package
Register Address: D81H, 3457 MSR_C1_PMON_BOX_STATUS
Uncore C-box 1 perfmon local box status MSR. Package
Register Address: D82H, 3458 MSR_C1_PMON_BOX_OVF_CTRL
Uncore C-box 1 perfmon local box overflow control MSR. Package
Register Address: D90H, 3472 MSR_C1_PMON_EVNT_SEL0
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D91H, 3473 MSR_C1_PMON_CTR0
Uncore C-box 1 perfmon counter MSR. Package
Register Address: D92H, 3474 MSR_C1_PMON_EVNT_SEL1
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D93H, 3475 MSR_C1_PMON_CTR1
Uncore C-box 1 perfmon counter MSR. Package
Register Address: D94H, 3476 MSR_C1_PMON_EVNT_SEL2
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D95H, 3477 MSR_C1_PMON_CTR2
Uncore C-box 1 perfmon counter MSR. Package
Register Address: D96H, 3478 MSR_C1_PMON_EVNT_SEL3
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D97H, 3479 MSR_C1_PMON_CTR3
Uncore C-box 1 perfmon counter MSR. Package
Register Address: D98H, 3480 MSR_C1_PMON_EVNT_SEL4
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D99H, 3481 MSR_C1_PMON_CTR4
Uncore C-box 1 perfmon counter MSR. Package
Register Address: D9AH, 3482 MSR_C1_PMON_EVNT_SEL5
Uncore C-box 1 perfmon event select MSR. Package
Register Address: D9BH, 3483 MSR_C1_PMON_CTR5
Uncore C-box 1 perfmon counter MSR. Package
Register Address: DA0H, 3488 MSR_C5_PMON_BOX_CTRL
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-187
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 5 perfmon local box control MSR. Package
Register Address: DA1H, 3489 MSR_C5_PMON_BOX_STATUS
Uncore C-box 5 perfmon local box status MSR. Package
Register Address: DA2H, 3490 MSR_C5_PMON_BOX_OVF_CTRL
Uncore C-box 5 perfmon local box overflow control MSR. Package
Register Address: DB0H, 3504 MSR_C5_PMON_EVNT_SEL0
Uncore C-box 5 perfmon event select MSR. Package
Register Address: DB1H, 3505 MSR_C5_PMON_CTR0
Uncore C-box 5 perfmon counter MSR. Package
Register Address: DB2H, 3506 MSR_C5_PMON_EVNT_SEL1
Uncore C-box 5 perfmon event select MSR. Package
Register Address: DB3H, 3507 MSR_C5_PMON_CTR1
Uncore C-box 5 perfmon counter MSR. Package
Register Address: DB4H, 3508 MSR_C5_PMON_EVNT_SEL2
Uncore C-box 5 perfmon event select MSR. Package
Register Address: DB5H, 3509 MSR_C5_PMON_CTR2
Uncore C-box 5 perfmon counter MSR. Package
Register Address: DB6H, 3510 MSR_C5_PMON_EVNT_SEL3
Uncore C-box 5 perfmon event select MSR. Package
Register Address: DB7H, 3511 MSR_C5_PMON_CTR3
Uncore C-box 5 perfmon counter MSR. Package
Register Address: DB8H, 3512 MSR_C5_PMON_EVNT_SEL4
Uncore C-box 5 perfmon event select MSR. Package
Register Address: DB9H, 3513 MSR_C5_PMON_CTR4
Uncore C-box 5 perfmon counter MSR. Package
Register Address: DBAH, 3514 MSR_C5_PMON_EVNT_SEL5
Uncore C-box 5 perfmon event select MSR. Package
Register Address: DBBH, 3515 MSR_C5_PMON_CTR5
Uncore C-box 5 perfmon counter MSR. Package
Register Address: DC0H, 3520 MSR_C3_PMON_BOX_CTRL
Uncore C-box 3 perfmon local box control MSR. Package
Register Address: DC1H, 3521 MSR_C3_PMON_BOX_STATUS
Uncore C-box 3 perfmon local box status MSR. Package
Register Address: DC2H, 3522 MSR_C3_PMON_BOX_OVF_CTRL
Uncore C-box 3 perfmon local box overflow control MSR. Package
Register Address: DD0H, 3536 MSR_C3_PMON_EVNT_SEL0
Uncore C-box 3 perfmon event select MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-188 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DD1H, 3537 MSR_C3_PMON_CTR0
Uncore C-box 3 perfmon counter MSR. Package
Register Address: DD2H, 3538 MSR_C3_PMON_EVNT_SEL1
Uncore C-box 3 perfmon event select MSR. Package
Register Address: DD3H, 3539 MSR_C3_PMON_CTR1
Uncore C-box 3 perfmon counter MSR. Package
Register Address: DD4H, 3540 MSR_C3_PMON_EVNT_SEL2
Uncore C-box 3 perfmon event select MSR. Package
Register Address: DD5H, 3541 MSR_C3_PMON_CTR2
Uncore C-box 3 perfmon counter MSR. Package
Register Address: DD6H, 3542 MSR_C3_PMON_EVNT_SEL3
Uncore C-box 3 perfmon event select MSR. Package
Register Address: DD7H, 3543 MSR_C3_PMON_CTR3
Uncore C-box 3 perfmon counter MSR. Package
Register Address: DD8H, 3544 MSR_C3_PMON_EVNT_SEL4
Uncore C-box 3 perfmon event select MSR. Package
Register Address: DD9H, 3545 MSR_C3_PMON_CTR4
Uncore C-box 3 perfmon counter MSR. Package
Register Address: DDAH, 3546 MSR_C3_PMON_EVNT_SEL5
Uncore C-box 3 perfmon event select MSR. Package
Register Address: DDBH, 3547 MSR_C3_PMON_CTR5
Uncore C-box 3 perfmon counter MSR. Package
Register Address: DE0H, 3552 MSR_C7_PMON_BOX_CTRL
Uncore C-box 7 perfmon local box control MSR. Package
Register Address: DE1H, 3553 MSR_C7_PMON_BOX_STATUS
Uncore C-box 7 perfmon local box status MSR. Package
Register Address: DE2H, 3554 MSR_C7_PMON_BOX_OVF_CTRL
Uncore C-box 7 perfmon local box overflow control MSR. Package
Register Address: DF0H, 3568 MSR_C7_PMON_EVNT_SEL0
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DF1H, 3569 MSR_C7_PMON_CTR0
Uncore C-box 7 perfmon counter MSR. Package
Register Address: DF2H, 3570 MSR_C7_PMON_EVNT_SEL1
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DF3H, 3571 MSR_C7_PMON_CTR1
Uncore C-box 7 perfmon counter MSR. Package
Register Address: DF4H, 3572 MSR_C7_PMON_EVNT_SEL2
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-189
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DF5H, 3573 MSR_C7_PMON_CTR2
Uncore C-box 7 perfmon counter MSR. Package
Register Address: DF6H, 3574 MSR_C7_PMON_EVNT_SEL3
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DF7H, 3575 MSR_C7_PMON_CTR3
Uncore C-box 7 perfmon counter MSR. Package
Register Address: DF8H, 3576 MSR_C7_PMON_EVNT_SEL4
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DF9H, 3577 MSR_C7_PMON_CTR4
Uncore C-box 7 perfmon counter MSR. Package
Register Address: DFAH, 3578 MSR_C7_PMON_EVNT_SEL5
Uncore C-box 7 perfmon event select MSR. Package
Register Address: DFBH, 3579 MSR_C7_PMON_CTR5
Uncore C-box 7 perfmon counter MSR. Package
Register Address: E00H, 3584 MSR_R0_PMON_BOX_CTRL
Uncore R-box 0 perfmon local box control MSR. Package
Register Address: E01H, 3585 MSR_R0_PMON_BOX_STATUS
Uncore R-box 0 perfmon local box status MSR. Package
Register Address: E02H, 3586 MSR_R0_PMON_BOX_OVF_CTRL
Uncore R-box 0 perfmon local box overflow control MSR. Package
Register Address: E04H, 3588 MSR_R0_PMON_IPERF0_P0
Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR. Package
Register Address: E05H, 3589 MSR_R0_PMON_IPERF0_P1
Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR. Package
Register Address: E06H, 3590 MSR_R0_PMON_IPERF0_P2
Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR. Package
Register Address: E07H, 3591 MSR_R0_PMON_IPERF0_P3
Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR. Package
Register Address: E08H, 3592 MSR_R0_PMON_IPERF0_P4
Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR. Package
Register Address: E09H, 3593 MSR_R0_PMON_IPERF0_P5
Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR. Package
Register Address: E0AH, 3594 MSR_R0_PMON_IPERF0_P6
Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR. Package
Register Address: E0BH, 3595 MSR_R0_PMON_IPERF0_P7
Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-190 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E0CH, 3596 MSR_R0_PMON_QLX_P0
Uncore R-box 0 perfmon QLX unit Port 0 select MSR. Package
Register Address: E0DH, 3597 MSR_R0_PMON_QLX_P1
Uncore R-box 0 perfmon QLX unit Port 1 select MSR. Package
Register Address: E0EH, 3598 MSR_R0_PMON_QLX_P2
Uncore R-box 0 perfmon QLX unit Port 2 select MSR. Package
Register Address: E0FH, 3599 MSR_R0_PMON_QLX_P3
Uncore R-box 0 perfmon QLX unit Port 3 select MSR. Package
Register Address: E10H, 3600 MSR_R0_PMON_EVNT_SEL0
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E11H, 3601 MSR_R0_PMON_CTR0
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E12H, 3602 MSR_R0_PMON_EVNT_SEL1
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E13H, 3603 MSR_R0_PMON_CTR1
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E14H, 3604 MSR_R0_PMON_EVNT_SEL2
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E15H, 3605 MSR_R0_PMON_CTR2
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E16H, 3606 MSR_R0_PMON_EVNT_SEL3
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E17H, 3607 MSR_R0_PMON_CTR3
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E18H, 3608 MSR_R0_PMON_EVNT_SEL4
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E19H, 3609 MSR_R0_PMON_CTR4
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E1AH, 3610 MSR_R0_PMON_EVNT_SEL5
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E1BH, 3611 MSR_R0_PMON_CTR5
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E1CH, 3612 MSR_R0_PMON_EVNT_SEL6
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E1DH, 3613 MSR_R0_PMON_CTR6
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E1EH, 3614 MSR_R0_PMON_EVNT_SEL7
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-191
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore R-box 0 perfmon event select MSR. Package
Register Address: E1FH, 3615 MSR_R0_PMON_CTR7
Uncore R-box 0 perfmon counter MSR. Package
Register Address: E20H, 3616 MSR_R1_PMON_BOX_CTRL
Uncore R-box 1 perfmon local box control MSR. Package
Register Address: E21H, 3617 MSR_R1_PMON_BOX_STATUS
Uncore R-box 1 perfmon local box status MSR. Package
Register Address: E22H, 3618 MSR_R1_PMON_BOX_OVF_CTRL
Uncore R-box 1 perfmon local box overflow control MSR. Package
Register Address: E24H, 3620 MSR_R1_PMON_IPERF1_P8
Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR. Package
Register Address: E25H, 3621 MSR_R1_PMON_IPERF1_P9
Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR. Package
Register Address: E26H, 3622 MSR_R1_PMON_IPERF1_P10
Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR. Package
Register Address: E27H, 3623 MSR_R1_PMON_IPERF1_P11
Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR. Package
Register Address: E28H, 3624 MSR_R1_PMON_IPERF1_P12
Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR. Package
Register Address: E29H, 3625 MSR_R1_PMON_IPERF1_P13
Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR. Package
Register Address: E2AH, 3626 MSR_R1_PMON_IPERF1_P14
Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR. Package
Register Address: E2BH, 3627 MSR_R1_PMON_IPERF1_P15
Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR. Package
Register Address: E2CH, 3628 MSR_R1_PMON_QLX_P4
Uncore R-box 1 perfmon QLX unit Port 4 select MSR. Package
Register Address: E2DH, 3629 MSR_R1_PMON_QLX_P5
Uncore R-box 1 perfmon QLX unit Port 5 select MSR. Package
Register Address: E2EH, 3630 MSR_R1_PMON_QLX_P6
Uncore R-box 1 perfmon QLX unit Port 6 select MSR. Package
Register Address: E2FH, 3631 MSR_R1_PMON_QLX_P7
Uncore R-box 1 perfmon QLX unit Port 7 select MSR. Package
Register Address: E30H, 3632 MSR_R1_PMON_EVNT_SEL8
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E31H, 3633 MSR_R1_PMON_CTR8
Uncore R-box 1 perfmon counter MSR. Package
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-192 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E32H, 3634 MSR_R1_PMON_EVNT_SEL9
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E33H, 3635 MSR_R1_PMON_CTR9
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E34H, 3636 MSR_R1_PMON_EVNT_SEL10
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E35H, 3637 MSR_R1_PMON_CTR10
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E36H, 3638 MSR_R1_PMON_EVNT_SEL11
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E37H, 3639 MSR_R1_PMON_CTR11
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E38H, 3640 MSR_R1_PMON_EVNT_SEL12
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E39H, 3641 MSR_R1_PMON_CTR12
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E3AH, 3642 MSR_R1_PMON_EVNT_SEL13
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E3BH, 3643 MSR_R1_PMON_CTR13
Uncore R-box 1perfmon counter MSR. Package
Register Address: E3CH, 3644 MSR_R1_PMON_EVNT_SEL14
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E3DH, 3645 MSR_R1_PMON_CTR14
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E3EH, 3646 MSR_R1_PMON_EVNT_SEL15
Uncore R-box 1 perfmon event select MSR. Package
Register Address: E3FH, 3647 MSR_R1_PMON_CTR15
Uncore R-box 1 perfmon counter MSR. Package
Register Address: E45H, 3653 MSR_B0_PMON_MATCH
Uncore B-box 0 perfmon local box match MSR. Package
Register Address: E46H, 3654 MSR_B0_PMON_MASK
Uncore B-box 0 perfmon local box mask MSR. Package
Register Address: E49H, 3657 MSR_S0_PMON_MATCH
Uncore S-box 0 perfmon local box match MSR. Package
Register Address: E4AH, 3658 MSR_S0_PMON_MASK
Uncore S-box 0 perfmon local box mask MSR. Package
Register Address: E4DH, 3661 MSR_B1_PMON_MATCH
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-193
MODEL-SPECIFIC REGISTERS (MSRS)
2.9 MSRS IN THE INTEL® XEON® PROCESSOR 5600 SERIES BASED ON
WESTMERE MICROARCHITECTURE
The Intel
®
Xeon
®
Processor 5600 Series is based on Westmere microarchitecture and supports the MSR interfaces
listed in Table 2-15, Table 2-16, plus additional MSRs listed in Table 2-18. These MSRs apply to the Intel Core i7, i5,
and i3 processor family with a CPUID Signature DisplayFamily_DisplayModel value of 06_25H or 06_2CH; see Table
2-1.
Uncore B-box 1 perfmon local box match MSR. Package
Register Address: E4EH, 3662 MSR_B1_PMON_MASK
Uncore B-box 1 perfmon local box mask MSR. Package
Register Address: E54H, 3668 MSR_M0_PMON_MM_CONFIG
Uncore M-box 0 perfmon local box address match/mask config MSR. Package
Register Address: E55H, 3669 MSR_M0_PMON_ADDR_MATCH
Uncore M-box 0 perfmon local box address match MSR. Package
Register Address: E56H, 3670 MSR_M0_PMON_ADDR_MASK
Uncore M-box 0 perfmon local box address mask MSR. Package
Register Address: E59H, 3673 MSR_S1_PMON_MATCH
Uncore S-box 1 perfmon local box match MSR. Package
Register Address: E5AH, 3674 MSR_S1_PMON_MASK
Uncore S-box 1 perfmon local box mask MSR. Package
Register Address: E5CH, 3676 MSR_M1_PMON_MM_CONFIG
Uncore M-box 1 perfmon local box address match/mask config MSR. Package
Register Address: E5DH, 3677 MSR_M1_PMON_ADDR_MATCH
Uncore M-box 1 perfmon local box address match MSR. Package
Register Address: E5EH, 3678 MSR_M1_PMON_ADDR_MASK
Uncore M-box 1 perfmon local box address mask MSR. Package
Register Address: 3B5H, 965 MSR_UNCORE_PMC5
See Section 20.3.1.2.2, “Uncore Performance Event Configuration Facility.” Package
Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.
Core
Table 2-17. Additional MSRs in the Intel® Xeon® Processor 7500 Series (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-194 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.10 MSRS IN THE INTEL® XEON® PROCESSOR E7 FAMILY BASED ON WESTMERE
MICROARCHITECTURE
The Intel
®
Xeon
®
Processor E7 Family is based on the Westmere microarchitecture and supports the MSR inter-
faces listed in Table 2-15 (except MSR address 1ADH), Table 2-16, plus additional MSRs listed in Table 2-19. These
processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_2FH.
1:0 AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES instruction
set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If the
configuration is not 01b, AES instructions can be mis-configured if a
privileged agent unintentionally writes 11b.
63:2 Reserved.
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
Offcore Response Event Select Register (R/W) Thread
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
39:32 Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
Package
47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
Package
63:48 Reserved.
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
See Table 2-2. Package
Table 2-18. Additional MSRs Supported by Intel® Processors Based on Westmere Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-195
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.
Core
1:0 AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES instruction set
availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If the
configuration is not 01b, AES instructions can be mis-configured if a
privileged agent unintentionally writes 11b.
63:2 Reserved.
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
Offcore Response Event Select Register (R/W) Thread
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Reserved. Attempt to read/write will cause #UD. Package
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
See Table 2-2. Package
Register Address: F40H, 3904 MSR_C8_PMON_BOX_CTRL
Uncore C-box 8 perfmon local box control MSR. Package
Register Address: F41H, 3905 MSR_C8_PMON_BOX_STATUS
Uncore C-box 8 perfmon local box status MSR. Package
Register Address: F42H, 3906 MSR_C8_PMON_BOX_OVF_CTRL
Uncore C-box 8 perfmon local box overflow control MSR. Package
Register Address: F50H, 3920 MSR_C8_PMON_EVNT_SEL0
Uncore C-box 8 perfmon event select MSR. Package
Register Address: F51H, 3921 MSR_C8_PMON_CTR0
Uncore C-box 8 perfmon counter MSR. Package
Register Address: F52H, 3922 MSR_C8_PMON_EVNT_SEL1
Uncore C-box 8 perfmon event select MSR. Package
Register Address: F53H, 3923 MSR_C8_PMON_CTR1
Uncore C-box 8 perfmon counter MSR. Package
Register Address: F54H, 3924 MSR_C8_PMON_EVNT_SEL2
Uncore C-box 8 perfmon event select MSR. Package
Register Address: F55H, 3925 MSR_C8_PMON_CTR2
Uncore C-box 8 perfmon counter MSR. Package
Register Address: F56H, 3926 MSR_C8_PMON_EVNT_SEL3
Uncore C-box 8 perfmon event select MSR. Package
2-196 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: F57H, 3927 MSR_C8_PMON_CTR3
Uncore C-box 8 perfmon counter MSR. Package
Register Address: F58H, 3928 MSR_C8_PMON_EVNT_SEL4
Uncore C-box 8 perfmon event select MSR. Package
Register Address: F59H, 3929 MSR_C8_PMON_CTR4
Uncore C-box 8 perfmon counter MSR. Package
Register Address: F5AH, 3930 MSR_C8_PMON_EVNT_SEL5
Uncore C-box 8 perfmon event select MSR. Package
Register Address: F5BH, 3931 MSR_C8_PMON_CTR5
Uncore C-box 8 perfmon counter MSR. Package
Register Address: FC0H, 4032 MSR_C9_PMON_BOX_CTRL
Uncore C-box 9 perfmon local box control MSR. Package
Register Address: FC1H, 4033 MSR_C9_PMON_BOX_STATUS
Uncore C-box 9 perfmon local box status MSR. Package
Register Address: FC2H, 4034 MSR_C9_PMON_BOX_OVF_CTRL
Uncore C-box 9 perfmon local box overflow control MSR. Package
Register Address: FD0H, 4048 MSR_C9_PMON_EVNT_SEL0
Uncore C-box 9 perfmon event select MSR. Package
Register Address: FD1H, 4049 MSR_C9_PMON_CTR0
Uncore C-box 9 perfmon counter MSR. Package
Register Address: FD2H, 4050 MSR_C9_PMON_EVNT_SEL1
Uncore C-box 9 perfmon event select MSR. Package
Register Address: FD3H, 4051 MSR_C9_PMON_CTR1
Uncore C-box 9 perfmon counter MSR. Package
Register Address: FD4H, 4052 MSR_C9_PMON_EVNT_SEL2
Uncore C-box 9 perfmon event select MSR. Package
Register Address: FD5H, 4053 MSR_C9_PMON_CTR2
Uncore C-box 9 perfmon counter MSR. Package
Register Address: FD6H, 4054 MSR_C9_PMON_EVNT_SEL3
Uncore C-box 9 perfmon event select MSR. Package
Register Address: FD7H, 4055 MSR_C9_PMON_CTR3
Uncore C-box 9 perfmon counter MSR. Package
Register Address: FD8H, 4056 MSR_C9_PMON_EVNT_SEL4
Uncore C-box 9 perfmon event select MSR. Package
Register Address: FD9H, 4057 MSR_C9_PMON_CTR4
Uncore C-box 9 perfmon counter MSR. Package
Register Address: FDAH, 4058 MSR_C9_PMON_EVNT_SEL5
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-197
MODEL-SPECIFIC REGISTERS (MSRS)
2.11 MSRS IN THE INTEL® PROCESSOR FAMILY BASED ON SANDY BRIDGE
MICROARCHITECTURE
Table 2-20 lists model-specific registers (MSRs) that are common to the Intel
®
processor family based on Sandy
Bridge microarchitecture. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_2AH
or 06_2DH; see Table 2-1. Additional MSRs specific to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_2AH are listed in Table 2-21.
Uncore C-box 9 perfmon event select MSR. Package
Register Address: FDBH, 4059 MSR_C9_PMON_CTR5
Uncore C-box 9 perfmon counter MSR. Package
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Thread
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.” Thread
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Thread
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and see Table 2-2. Thread
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
Package
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Thread
Register Address: 34H, 52 MSR_SMI_COUNT
SMI Counter (R/O) Thread
31:0 SMI Count (R/O)
Count SMIs.
63:32 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Thread
0Lock (R/WL)
1 Enable VMX Inside SMX Operation (R/WL)
2 Enable VMX Outside SMX Operation (R/WL)
Table 2-19. Additional MSRs Supported by the Intel® Xeon® Processor E7 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-198 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
14:8 SENTER Local Functions Enables (R/WL)
15 SENTER Global Functions Enable (R/WL)
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Core
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Thread
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
See Table 2-2.
Thread
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Thread
Register Address: C3H, 195 IA32_PMC2
Performance Counter Register
See Table 2-2.
Thread
Register Address: C4H, 196 IA32_PMC3
Performance Counter Register
See Table 2-2.
Thread
Register Address: C5H, 197 IA32_PMC4
Performance Counter Register (if core not shared by threads) Core
Register Address: C6H, 198 IA32_PMC5
Performance Counter Register (if core not shared by threads) Core
Register Address: C7H, 199 IA32_PMC6
Performance Counter Register (if core not shared by threads) Core
Register Address: C8H, 200 IA32_PMC7
Performance Counter Register (if core not shared by threads) Core
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs at. Frequency =
ratio * 100 MHz.
Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
Package
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-199
MODEL-SPECIFIC REGISTERS (MSRS)
29 Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode is programmable.
When set to 0, indicates TDP Limit for Turbo mode is not programmable.
Package
39:30 Reserved.
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
See http://biosbits.org.
Core
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit
Note: This field cannot be used to limit package C-state to C3.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
24:16 Reserved.
25 C3 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote C6/C7 requests to C3
based on uncore auto-demote information.
26 C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote C3/C6/C7 requests to C1
based on uncore auto-demote information.
27 Enable C3 Undemotion (R/W)
When set, enables undemotion from demoted C3.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-200 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
28 Enable C1 Undemotion (R/W)
When set, enables undemotion from demoted C1.
63:29 Reserved.
Register Address: E4H, 228 MSR_PMG_IO_CAPTURE_BASE
Power Management IO Redirection in C-state (R/W)
See http://biosbits.org.
Core
15:0 LVL_2 Base Address (R/W)
Specifies the base address visible to software for IO redirection. If IO
MWAIT Redirection is enabled, reads to this address will be consumed by
the power management logic and decoded to MWAIT instructions. When IO
port address redirection is enabled, this is the IO port address reported to
the OS/software.
18:16 C-State Range (R/W)
Specifies the encoding value of the maximum C-State code name to be
included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL[bit10]:
000b - C3 is the max C-State to include.
001b - C6 is the max C-State to include.
010b - C7 is the max C-State to include.
63:19 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Thread
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Thread
Register Address: FEH, 254 IA32_MTRRCAP
See Table 2-2. Thread
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.
Core
1:0 AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES instruction
set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, AES instruction set is not available if read is unsuccessful. If the
configuration is not 01b, AES instructions can be mis-configured if a
privileged agent unintentionally writes 11b.
63:2 Reserved.
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Thread
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-201
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Thread
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Thread
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Thread
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Thread
0RIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) can
be used to restart the program. If cleared, the program cannot be reliably
restarted.
1EIPV
When set, bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) is
directly associated with the error.
2MCIP
When set, bit indicates that a machine check has been generated. If a
second machine check is detected while this bit is still set, the processor
enters a shutdown state. Software should write this bit to 0 after
processing a machine check exception.
63:3 Reserved.
Register Address: 186H, 390 IA32_PERFEVTSEL0
See Table 2-2. Thread
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Thread
Register Address: 188H, 392 IA32_PERFEVTSEL2
See Table 2-2. Thread
Register Address: 189H, 393 IA32_PERFEVTSEL3
See Table 2-2. Thread
Register Address: 18AH, 394 IA32_PERFEVTSEL4
See Table 2-2. If CPUID.0AH:EAX[15:8] > 4. Core
Register Address: 18BH, 395 IA32_PERFEVTSEL5
See Table 2-2. If CPUID.0AH:EAX[15:8] > 5. Core
Register Address: 18CH, 396 IA32_PERFEVTSEL6
See Table 2-2. If CPUID.0AH:EAX[15:8] > 6. Core
Register Address: 18DH, 397 IA32_PERFEVTSEL7
See Table 2-2. If CPUID.0AH:EAX[15:8] > 7. Core
Register Address: 198H, 408 IA32_PERF_STATUS
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-202 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Package
15:0 Current Performance State Value
63:16 Reserved.
Register Address: 198H, 408 MSR_PERF_STATUS
Performance Status Package
47:32 Core Voltage (R/O)
P-state core voltage can be computed by
MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Thread
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.
Thread
3:0 On demand Clock Modulation Duty Cycle (R/W)
In 6.25% increment.
4 On demand Clock Modulation Enable (R/W)
63:5 Reserved.
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2.
Core
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Core
0 Thermal Status (R/O)
See Table 2-2.
1 Thermal Status Log (R/WC0)
See Table 2-2.
2 PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4 Critical Temperature Status (R/O)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal Threshold #1 Status (R/O)
See Table 2-2.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-203
MODEL-SPECIFIC REGISTERS (MSRS)
7 Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (R/O)
See Table 2-2.
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (R/O)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
15:12 Reserved.
22:16 Digital Readout (R/O)
See Table 2-2.
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O)
See Table 2-2.
31 Reading Valid (R/O)
See Table 2-2.
63:32 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
0Fast-Strings Enable
See Table 2-2.
Thread
6:1 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Thread
10:8 Reserved
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Thread
12 Processor Event Based Sampling Unavailable (R/O)
See Table 2-2.
Thread
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
See Table 2-2.
Package
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Thread
21:19 Reserved.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-204 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Thread
23 xTPR Message Disable (R/W)
See Table 2-2.
Thread
33:24 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Thread
37:35 Reserved.
38 Turbo Mode Disable (R/W)
When set to 1 on processors that support Intel Turbo Boost Technology,
the turbo mode feature is disabled and the IDA_Enable feature flag will be
clear (CPUID.06H: EAX[1]=0).
When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
reports the processor’s support of turbo mode is enabled.
Note: The power-on default value is used by BIOS to detect hardware
support of turbo mode. If the power-on default value is 1, turbo mode is
available in the processor. If the power-on default value is 0, turbo mode is
not available.
Package
63:39 Reserved.
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Unique
15:0 Reserved.
23:16 Temperature Target (R)
The minimum temperature at which PROCHOT# will be asserted. The value
is degrees C.
63:24 Reserved.
Register Address: 1A4H, 420 MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0 L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher, which fetches additional lines of
code or data into the L2 cache.
Core
1 L2 Adjacent Cache Line Prefetcher Disable (R/W)
If 1, disables the adjacent cache line prefetcher, which fetches the cache
line that comprises a cache line pair (128 bytes).
Core
2 DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher, which fetches the next cache
line into L1 data cache.
Core
3 DCU IP Prefetcher Disable (R/W)
If 1, disables the L1 data cache IP prefetcher, which uses sequential load
history (based on instruction pointer of previous loads) to determine
whether to prefetch additional lines.
Core
63:4 Reserved.
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-205
MODEL-SPECIFIC REGISTERS (MSRS)
Offcore Response Event Select Register (R/W) Thread
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
Offcore Response Event Select Register (R/W) Thread
Register Address: 1AAH, 426 MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control
Various model specific features enumeration. See http://biosbits.org.
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
See Table 2-2. Package
Register Address: 1B1H, 433 IA32_PACKAGE_THERM_STATUS
See Table 2-2. Package
Register Address: 1B2H, 434 IA32_PACKAGE_THERM_INTERRUPT
See Table 2-2. Package
Register Address: 1C8H, 456 MSR_LBR_SELECT
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
Thread
0CPL_EQ_0
1 CPL_NEQ_0
2JCC
3 NEAR_REL_CALL
4NEAR_IND_CALL
5 NEAR_RET
6NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 680H).
Thread
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
See Table 2-2.
Thread
0 LBR: Last Branch Record
1BTF
5:2 Reserved.
6 TR: Branch Trace
7 BTS: Log Branch Trace Message to BTS buffer
8BTINT
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-206 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
9BTS_OFF_OS
10 BTS_OFF_USER
11 FREEZE_LBR_ON_PMI
12 FREEZE_PERFMON_ON_PMI
13 ENABLE_UNCORE_PMI
14 FREEZE_WHILE_SMM
63:15 Reserved.
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R/W)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
Thread
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R/W)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
Thread
Register Address: 1F2H, 498 IA32_SMRR_PHYSBASE
See Table 2-2. Core
Register Address: 1F3H, 499 IA32_SMRR_PHYSMASK
See Table 2-2. Core
Register Address: 1FCH, 508 MSR_POWER_CTL
See http://biosbits.org. Core
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
See Table 2-2. Thread
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
See Table 2-2. Thread
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
See Table 2-2. Thread
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
See Table 2-2. Thread
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
See Table 2-2. Thread
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
See Table 2-2. Thread
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
See Table 2-2. Thread
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
See Table 2-2. Thread
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-207
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Thread
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
See Table 2-2. Thread
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
See Table 2-2. Thread
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
See Table 2-2. Thread
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
See Table 2-2. Thread
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
See Table 2-2. Thread
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
See Table 2-2. Thread
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
See Table 2-2. Thread
Register Address: 210H, 528 IA32_MTRR_PHYSBASE8
See Table 2-2. Thread
Register Address: 211H, 529 IA32_MTRR_PHYSMASK8
See Table 2-2. Thread
Register Address: 212H, 530 IA32_MTRR_PHYSBASE9
See Table 2-2. Thread
Register Address: 213H, 531 IA32_MTRR_PHYSMASK9
See Table 2-2. Thread
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
See Table 2-2. Thread
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
See Table 2-2. Thread
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
See Table 2-2. Thread
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
See Table 2-2. Thread
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
See Table 2-2. Thread
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
See Table 2-2. Thread
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
See Table 2-2. Thread
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-208 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
See Table 2-2. Thread
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
See Table 2-2. Thread
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
See Table 2-2. Thread
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
See Table 2-2. Thread
Register Address: 277H, 631 IA32_PAT
See Table 2-2. Thread
Register Address: 280H, 640 IA32_MC0_CTL2
See Table 2-2. Core
Register Address: 281H, 641 IA32_MC1_CTL2
See Table 2-2. Core
Register Address: 282H, 642 IA32_MC2_CTL2
See Table 2-2. Core
Register Address: 283H, 643 IA32_MC3_CTL2
See Table 2-2. Core
Register Address: 284H, 644 IA32_MC4_CTL2
Always 0 (CMCI not supported). Package
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2.
Thread
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
Thread
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
Thread
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
Thread
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
See Table 2-2 and Section 18.4.1, “IA32_DEBUGCTL MSR.” Thread
5:0 LBR Format
See Table 2-2.
6 PEBS Record Format.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-209
MODEL-SPECIFIC REGISTERS (MSRS)
7 PEBSSaveArchRegs
See Table 2-2.
11:8 PEBS_REC_FORMAT
See Table 2-2.
12 SMM_FREEZE
See Table 2-2.
63:13 Reserved.
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
Thread
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.”
0Ovf_PMC0 Thread
1Ovf_PMC1 Thread
2Ovf_PMC2 Thread
3Ovf_PMC3 Thread
4 Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4) Core
5 Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5) Core
6 Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6) Core
7 Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7) Core
31:8 Reserved.
32 Ovf_FixedCtr0 Thread
33 Ovf_FixedCtr1 Thread
34 Ovf_FixedCtr2 Thread
60:35 Reserved.
61 Ovf_Uncore Thread
62 Ovf_BufDSSAVE Thread
63 CondChgd Thread
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.” Thread
0 Set 1 to enable PMC0 to count. Thread
1 Set 1 to enable PMC1 to count. Thread
2 Set 1 to enable PMC2 to count. Thread
3 Set 1 to enable PMC3 to count. Thread
4 Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4). Core
5 Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5). Core
6 Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6). Core
7 Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7). Core
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-210 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
31:8 Reserved.
32 Set 1 to enable FixedCtr0 to count. Thread
33 Set 1 to enable FixedCtr1 to count. Thread
34 Set 1 to enable FixedCtr2 to count. Thread
63:35 Reserved.
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.”
0 Set 1 to clear Ovf_PMC0. Thread
1 Set 1 to clear Ovf_PMC1. Thread
2 Set 1 to clear Ovf_PMC2. Thread
3 Set 1 to clear Ovf_PMC3. Thread
4 Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). Core
5 Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). Core
6 Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). Core
7 Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). Core
31:8 Reserved.
32 Set 1 to clear Ovf_FixedCtr0. Thread
33 Set 1 to clear Ovf_FixedCtr1. Thread
34 Set 1 to clear Ovf_FixedCtr2. Thread
60:35 Reserved.
61 Set 1 to clear Ovf_Uncore. Thread
62 Set 1 to clear Ovf_BufDSSAVE. Thread
63 Set 1 to clear CondChgd. Thread
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).” Thread
0 Enable PEBS on IA32_PMC0. (R/W)
1 Enable PEBS on IA32_PMC1. (R/W)
2 Enable PEBS on IA32_PMC2. (R/W)
3 Enable PEBS on IA32_PMC3. (R/W)
31:4 Reserved.
32 Enable Load Latency on IA32_PMC0. (R/W)
33 Enable Load Latency on IA32_PMC1. (R/W)
34 Enable Load Latency on IA32_PMC2. (R/W)
35 Enable Load Latency on IA32_PMC3. (R/W)
62:36 Reserved.
63 Enable Precise Store (R/W)
Register Address: 3F6H, 1014 MSR_PEBS_LD_LAT
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-211
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 20.3.1.1.2, “Load Latency Performance Monitoring Facility.” Thread
15:0 Minimum threshold latency value of tagged load operation that will be
counted. (R/W)
63:36 Reserved.
Register Address: 3F8H, 1016 MSR_PKG_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C3 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C3 states.
Count at the same frequency as the TSC.
Register Address: 3F9H, 1017 MSR_PKG_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C6 Residency Counter. (R/O)
Value since last reset that this package is in processor-specific C6 states.
Count at the same frequency as the TSC.
Register Address: 3FAH, 1018 MSR_PKG_C7_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C7 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C7 states.
Count at the same frequency as the TSC.
Register Address: 3FCH, 1020 MSR_CORE_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C3 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C3 states. Count
at the same frequency as the TSC.
Register Address: 3FDH, 1021 MSR_CORE_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C6 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C6 states. Count
at the same frequency as the TSC.
Register Address: 3FEH, 1022 MSR_CORE_C7_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Core
63:0 CORE C7 Residency Counter (R/O)
Value since last reset that this core is in processor-specific C7 states. Count
at the same frequency as the TSC.
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-212 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Core
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 403H, 1027 IA32_MC0_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Core
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Core
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Core
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 407H, 1031 IA32_MC1_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Core
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Core
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 40BH, 1035 IA32_MC2_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Core
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Core
Register Address: 40DH, 1037 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Core
Register Address: 40EH, 1038 IA32_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 40FH, 1039 IA32_MC3_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Core
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
0 PCU Hardware Error (R/W)
When set, enables signaling of PCU hardware detected errors.
1 PCU Controller Error (R/W)
When set, enables signaling of PCU controller detected errors.
2 PCU Firmware Error (R/W)
When set, enables signaling of PCU firmware detected errors.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-213
MODEL-SPECIFIC REGISTERS (MSRS)
63:2 Reserved.
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Core
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2 and Appendix A.1, “Basic VMX Information.”
Thread
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Table 2-2 and Appendix A.3, “VM-Execution Controls.”
Thread
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Thread
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-Exit Controls (R/O)
See Table 2-2 and Appendix A.4, “VM-Exit Controls.”
Thread
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Table 2-2 and Appendix A.5, “VM-Entry Controls.”
Thread
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 2-2 and Appendix A.6, “Miscellaneous Data.”
Thread
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”
Thread
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 2-2 and Appendix A.7, “VMX-Fixed Bits in CR0.”
Thread
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”
Thread
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 2-2 and Appendix A.8, “VMX-Fixed Bits in CR4.”
Thread
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2 and Appendix A.9, “VMCS Enumeration.”
Thread
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.”
Thread
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-214 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 48CH, 1164 IA32_VMX_EPT_VPID_ENUM
Capability Reporting Register of EPT and VPID (R/O)
See Table 2-2
Thread
Register Address: 48DH, 1165 IA32_VMX_TRUE_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)
See Table 2-2
Thread
Register Address: 48EH, 1166 IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)
See Table 2-2
Thread
Register Address: 48FH, 1167 IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-Exit Flex Controls (R/O)
See Table 2-2
Thread
Register Address: 490H, 1168 IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VM-Entry Flex Controls (R/O)
See Table 2-2
Thread
Register Address: 4C1H, 1217 IA32_A_PMC0
See Table 2-2. Thread
Register Address: 4C2H, 1218 IA32_A_PMC1
See Table 2-2. Thread
Register Address: 4C3H, 1219 IA32_A_PMC2
See Table 2-2. Thread
Register Address: 4C4H, 1220 IA32_A_PMC3
See Table 2-2. Thread
Register Address: 4C5H, 1221 IA32_A_PMC4
See Table 2-2. Core
Register Address: 4C6H, 1222 IA32_A_PMC5
See Table 2-2. Core
Register Address: 4C7H, 1223 IA32_A_PMC6
See Table 2-2. Core
Register Address: 4C8H, 1224 IA32_A_PMC7
See Table 2-2. Core
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”
Thread
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers used in RAPL Interfaces (R/O)
See Section 15.10.1, “RAPL Interfaces.”
Package
Register Address: 60AH, 1546 MSR_PKGC3_IRTL
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-215
MODEL-SPECIFIC REGISTERS (MSRS)
Package C3 Interrupt Response Limit (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C3 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by the
processor for package C-sate management.
63:16 Reserved.
Register Address: 60BH, 1547 MSR_PKGC6_IRTL
Package C6 Interrupt Response Limit (R/W)
This MSR defines the budget allocated for the package to exit from a C6 to a C0 state, where an interrupt request can
be delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state
the core is in.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C6 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by the
processor for package C-sate management.
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-216 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:16 Reserved.
Register Address: 60DH, 1549 MSR_PKG_C2_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
63:0 Package C2 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C2 states.
Count at the same frequency as the TSC.
Register Address: 610H, 1552 MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 611H, 1553 MSR_PKG_ENERGY_STATUS
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 614H, 1556 MSR_PKG_POWER_INFO
PKG RAPL Parameters (R/W)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 638H, 1592 MSR_PP0_POWER_LIMIT
PP0 RAPL Power Limit Control (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 680H, 1664 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 From IP (R/W)
One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1 and record format in Section 18.4.8.1.
Thread
Register Address: 681H, 1665 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 682H, 1666 MSR_LASTBRANCH_2_FROM_IP
Last Branch Record 2 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 683H, 1667 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 684H, 1668 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 685H, 1669 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-217
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 686H, 1670 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 687H, 1671 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 688H, 1672 MSR_LASTBRANCH_8_FROM_IP
Last Branch Record 8 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 689H, 1673 MSR_LASTBRANCH_9_FROM_IP
Last Branch Record 9 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68AH, 1674 MSR_LASTBRANCH_10_FROM_IP
Last Branch Record 10 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68BH, 1675 MSR_LASTBRANCH_11_FROM_IP
Last Branch Record 11 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68CH, 1676 MSR_LASTBRANCH_12_FROM_IP
Last Branch Record 12 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68DH, 1677 MSR_LASTBRANCH_13_FROM_IP
Last Branch Record 13 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68EH, 1678 MSR_LASTBRANCH_14_FROM_IP
Last Branch Record 14 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 68FH, 1679 MSR_LASTBRANCH_15_FROM_IP
Last Branch Record 15 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 6C0H, 1728 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 To IP (R/W)
One of sixteen pairs of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the destination instruction.
Thread
Register Address: 6C1H, 1729 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C2H, 1730 MSR_LASTBRANCH_2_TO_IP
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-218 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 2 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C3H, 1731 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C4H, 1732 MSR_LASTBRANCH_4_TO_IP
Last Branch Record 4 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C5H, 1733 MSR_LASTBRANCH_5_TO_IP
Last Branch Record 5 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C6H, 1734 MSR_LASTBRANCH_6_TO_IP
Last Branch Record 6 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C7H, 1735 MSR_LASTBRANCH_7_TO_IP
Last Branch Record 7 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C8H, 1736 MSR_LASTBRANCH_8_TO_IP
Last Branch Record 8 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6C9H, 1737 MSR_LASTBRANCH_9_TO_IP
Last Branch Record 9 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CAH, 1738 MSR_LASTBRANCH_10_TO_IP
Last Branch Record 10 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CBH, 1739 MSR_LASTBRANCH_11_TO_IP
Last Branch Record 11 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CCH, 1740 MSR_LASTBRANCH_12_TO_IP
Last Branch Record 12 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CDH, 1741 MSR_LASTBRANCH_13_TO_IP
Last Branch Record 13 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CEH, 1742 MSR_LASTBRANCH_14_TO_IP
Last Branch Record 14 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6CFH, 1743 MSR_LASTBRANCH_15_TO_IP
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-219
MODEL-SPECIFIC REGISTERS (MSRS)
2.11.1 MSRs in the 2nd Generation Intel® Core™ Processor Family Based on Sandy Bridge
Microarchitecture
Table 2-21 and Table 2-22 list model-specific registers (MSRs) that are specific to the 2nd generation Intel
®
Core™
processor family based on the Sandy Bridge microarchitecture. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2AH; see Table 2-1.
Last Branch Record 15 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6E0H, 1760 IA32_TSC_DEADLINE
See Table 2-2. Thread
Register Address: 802H−83FH, 2050−
2111
X2APIC MSRs
See Table 2-2. Thread
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
Thread
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
Thread
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
Thread
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
Thread
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W)
See Table 2-2.
Thread
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
Thread
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
Thread
Register Address: C000_0103H IA32_TSC_AUX
AUXILIARY TSC Signature (R/W)
See Table 2-2 and Section 18.17.2, “IA32_TSC_AUX Register and RDTSCP Support.”
Thread
Table 2-20. MSRs Supported by Intel® Processors Based on Sandy Bridge Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-220 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0.
R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
63:32 Reserved.
Register Address: 60CH, 1548 MSR_PKGC7_IRTL
Package C7 Interrupt Response Limit (R/W)
This MSR defines the budget allocated for the package to exit from a C7 to a C0 state, where interrupt request can be
delivered to the core and serviced. Additional core-exit latency may be applicable depending on the actual C-state the
core is in.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C7 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. The following time unit encodings are supported:
000b: 1 ns
001b: 32 ns
010b: 1024 ns
011b: 32768 ns
100b: 1048576 ns
101b: 33554432 ns
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by
the processor for package C-sate management.
63:16 Reserved.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 63AH, 1594 MSR_PP0_POLICY
Vol. 4 2-221
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-22 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_2AH.
PP0 Balance Policy (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 640H, 1600 MSR_PP1_POWER_LIMIT
PP1 RAPL Power Limit Control (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 641H, 1601 MSR_PP1_ENERGY_STATUS
PP1 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 642H, 1602 MSR_PP1_POLICY
PP1 Balance Policy (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
See Table 2-20, Table 2-21, and Table 2-22 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_2AH.
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 391H, 913 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4 Slice 4 select.
18:5 Reserved.
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved.
Register Address: 392H, 914 MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status Package
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved.
3 A CBox counter overflowed (on any slice).
63:4 Reserved.
Table 2-21. MSRs Supported by the 2nd Generation Intel® Core™ Processors (Sandy Bridge Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-222 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 394H, 916 MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W) Package
19:0 Reserved.
20 Enable overflow propagation.
21 Reserved.
22 Enable counting.
63:23 Reserved.
Register Address: 395H, 917 MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter Package
47:0 Current count.
63:48 Reserved.
Register Address: 396H, 918 MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O) Package
3:0 Report the number of C-Box units with performance counters, including
processor cores and processor graphics.
63:4 Reserved.
Register Address: 3B0H, 946 MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0 Package
Register Address: 3B1H, 947 MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1 Package
Register Address: 3B2H, 944 MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR Package
Register Address: 3B3H, 945 MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb unit, Counter 1 Event Select MSR Package
Register Address: 700H, 1792 MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR Package
Register Address: 701H, 1793 MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR Package
Register Address: 702H, 1794 MSR_UNC_CBO_0_PERFEVTSEL2
Uncore C-Box 0, Counter 2 Event Select MSR Package
Register Address: 703H, 1795 MSR_UNC_CBO_0_PERFEVTSEL3
Uncore C-Box 0, Counter 3 Event Select MSR Package
Register Address: 705H, 1797 MSR_UNC_CBO_0_UNIT_STATUS
Uncore C-Box 0, Unit Status for Counter 0-3 Package
Register Address: 706H, 1798 MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0 Package
Register Address: 707H, 1799 MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1 Package
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-223
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 708H, 1800 MSR_UNC_CBO_0_PERFCTR2
Uncore C-Box 0, Performance Counter 2 Package
Register Address: 709H, 1801 MSR_UNC_CBO_0_PERFCTR3
Uncore C-Box 0, Performance Counter 3 Package
Register Address: 710H, 1808 MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR Package
Register Address: 711H, 1809 MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR Package
Register Address: 712H, 1810 MSR_UNC_CBO_1_PERFEVTSEL2
Uncore C-Box 1, Counter 2 Event Select MSR Package
Register Address: 713H, 1811 MSR_UNC_CBO_1_PERFEVTSEL3
Uncore C-Box 1, Counter 3 Event Select MSR Package
Register Address: 715H, 1813 MSR_UNC_CBO_1_UNIT_STATUS
Uncore C-Box 1, Unit Status for Counter 0-3 Package
Register Address: 716H, 1814 MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0 Package
Register Address: 717H, 1815 MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1 Package
Register Address: 718H, 1816 MSR_UNC_CBO_1_PERFCTR2
Uncore C-Box 1, Performance Counter 2 Package
Register Address: 719H, 1817 MSR_UNC_CBO_1_PERFCTR3
Uncore C-Box 1, Performance Counter 3 Package
Register Address: 720H, 1824 MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR Package
Register Address: 721H, 1825 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR Package
Register Address: 722H, 1826 MSR_UNC_CBO_2_PERFEVTSEL2
Uncore C-Box 2, Counter 2 Event Select MSR Package
Register Address: 723H, 1827 MSR_UNC_CBO_2_PERFEVTSEL3
Uncore C-Box 2, Counter 3 Event Select MSR Package
Register Address: 725H, 1829 MSR_UNC_CBO_2_UNIT_STATUS
Uncore C-Box 2, Unit Status for Counter 0-3 Package
Register Address: 726H, 1830 MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0 Package
Register Address: 727H, 1831 MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1 Package
Register Address: 728H, 1832 MSR_UNC_CBO_3_PERFCTR2
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-224 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 3, Performance Counter 2 Package
Register Address: 729H, 1833 MSR_UNC_CBO_3_PERFCTR3
Uncore C-Box 3, Performance Counter 3 Package
Register Address: 730H, 1840 MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR Package
Register Address: 731H, 1841 MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR Package
Register Address: 732H, 1842 MSR_UNC_CBO_3_PERFEVTSEL2
Uncore C-Box 3, Counter 2 Event Select MSR Package
Register Address: 733H, 1843 MSR_UNC_CBO_3_PERFEVTSEL3
Uncore C-Box 3, counter 3 Event Select MSR Package
Register Address: 735H, 1845 MSR_UNC_CBO_3_UNIT_STATUS
Uncore C-Box 3, Unit Status for Counter 0-3 Package
Register Address: 736H, 1846 MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0 Package
Register Address: 737H, 1847 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 Package
Register Address: 738H, 1848 MSR_UNC_CBO_3_PERFCTR2
Uncore C-Box 3, Performance Counter 2 Package
Register Address: 739H, 1849 MSR_UNC_CBO_3_PERFCTR3
Uncore C-Box 3, Performance Counter 3 Package
Register Address: 740H, 1856 MSR_UNC_CBO_4_PERFEVTSEL0
Uncore C-Box 4, Counter 0 Event Select MSR Package
Register Address: 741H, 1857 MSR_UNC_CBO_4_PERFEVTSEL1
Uncore C-Box 4, Counter 1 Event Select MSR Package
Register Address: 742H, 1858 MSR_UNC_CBO_4_PERFEVTSEL2
Uncore C-Box 4, Counter 2 Event Select MSR Package
Register Address: 743H, 1859 MSR_UNC_CBO_4_PERFEVTSEL3
Uncore C-Box 4, Counter 3 Event Select MSR Package
Register Address: 745H, 1861 MSR_UNC_CBO_4_UNIT_STATUS
Uncore C-Box 4, Unit status for Counter 0-3 Package
Register Address: 746H, 1862 MSR_UNC_CBO_4_PERFCTR0
Uncore C-Box 4, Performance Counter 0 Package
Register Address: 747H, 1863 MSR_UNC_CBO_4_PERFCTR1
Uncore C-Box 4, Performance Counter 1 Package
Register Address: 748H, 1864 MSR_UNC_CBO_4_PERFCTR2
Uncore C-Box 4, Performance Counter 2 Package
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-225
MODEL-SPECIFIC REGISTERS (MSRS)
2.11.2 MSRs in the Intel® Xeon® Processor E5 Family Based on Sandy Bridge
Microarchitecture
Table 2-23 lists additional model-specific registers (MSRs) that are specific to the Intel
®
Xeon
®
Processor E5
Family based on Sandy Bridge microarchitecture. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2DH, and also support MSRs listed in Table 2-20 and Table 2-24.
Register Address: 749H, 1865 MSR_UNC_CBO_4_PERFCTR3
Uncore C-Box 4, Performance Counter 3 Package
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 17FH, 383 MSR_ERROR_CONTROL
MC Bank Error Configuration (R/W) Package
0 Reserved.
1 MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits 36:32.
63:2 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0. R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 cores active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 cores active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 cores active.
Package
39:32 Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 cores active.
Package
47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 cores active.
Package
55:48 Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 cores active.
Package
63:56 Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 cores active.
Package
Register Address: 285H, 645 IA32_MC5_CTL2
See Table 2-2. Package
Table 2-22. Uncore PMU MSRs Supported by 2nd Generation Intel® Core™ Processors (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-226 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 287H, 647 IA32_MC7_CTL2
See Table 2-2. Package
Register Address: 288H, 648 IA32_MC8_CTL2
See Table 2-2. Package
Register Address: 289H, 649 IA32_MC9_CTL2
See Table 2-2. Package
Register Address: 28AH, 650 IA32_MC10_CTL2
See Table 2-2. Package
Register Address: 28BH, 651 IA32_MC11_CTL2
See Table 2-2. Package
Register Address: 28CH, 652 IA32_MC12_CTL2
See Table 2-2. Package
Register Address: 28DH, 653 IA32_MC13_CTL2
See Table 2-2. Package
Register Address: 28EH, 654 IA32_MC14_CTL2
See Table 2-2. Package
Register Address: 28FH, 655 IA32_MC15_CTL2
See Table 2-2. Package
Register Address: 290H, 656 IA32_MC16_CTL2
See Table 2-2. Package
Register Address: 291H, 657 IA32_MC17_CTL2
See Table 2-2. Package
Register Address: 292H, 658 IA32_MC18_CTL2
See Table 2-2. Package
Register Address: 293H, 659 IA32_MC19_CTL2
See Table 2-2. Package
Register Address: 39CH, 924 MSR_PEBS_NUM_ALT
ENABLE_PEBS_NUM_ALT (R/W) Package
0 ENABLE_PEBS_NUM_ALT (R/W)
Write 1 to enable alternate PEBS counting logic for specific events
requiring additional configuration, see https://perfmon-events.intel.com/
.
63:1 Reserved, must be zero.
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 415H, 1045 IA32_MC5_STATUS
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-227
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 417H, 1047 IA32_MC5_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 420H, 1056 IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 421H, 1057 IA32_MC8_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 422H, 1058 IA32_MC8_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 423H, 1059 IA32_MC8_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 425H, 1061 IA32_MC9_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 426H, 1062 IA32_MC9_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-228 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 42BH, 1067 IA32_MC10_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 42CH, 1068 IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 42DH, 1069 IA32_MC11_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 42EH, 1070 IA32_MC11_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 42FH, 1071 IA32_MC11_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 430H, 1072 IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 431H, 1073 IA32_MC12_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 432H, 1074 IA32_MC12_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 433H, 1075 IA32_MC12_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 434H, 1076 IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 435H, 1077 IA32_MC13_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 436H, 1078 IA32_MC13_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 437H, 1079 IA32_MC13_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 438H, 1080 IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 439H, 1081 IA32_MC14_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 43AH, 1082 IA32_MC14_ADDR
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-229
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 43BH, 1083 IA32_MC14_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 43CH, 1084 IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 43DH, 1085 IA32_MC15_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 43EH, 1086 IA32_MC15_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 43FH, 1087 IA32_MC15_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 440H, 1088 IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 441H, 1089 IA32_MC16_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 442H, 1090 IA32_MC16_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 443H, 1091 IA32_MC16_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Package
Register Address: 445H, 1093 IA32_MC17_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.” Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 449H, 1097 IA32_MC18_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-230 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.11.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 Family
Intel Xeon Processor E5 family is based on the Sandy Bridge microarchitecture. The MSR-based uncore PMU inter-
faces are listed in Table 2-24. For complete details of the uncore PMU, refer to the Intel Xeon Processor E5 Product
Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_2DH.
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS,” and Chapter 17. Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 44FH, 1103 IA32_MC19_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.” Package
Register Address: 613H, 1555 MSR_PKG_PERF_STATUS
Package RAPL Perf Status (R/O) Package
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
See Table 2-20, Table 2-23, and Table 2-24 for MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_2DH.
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: C08H, 3080 MSR_U_PMON_UCLK_FIXED_CTL
Uncore U-box UCLK Fixed Counter Control Package
Register Address: C09H, 3081 MSR_U_PMON_UCLK_FIXED_CTR
Table 2-23. Additional MSRs Supported by the Intel® Xeon® Processors E5 Family Based on Sandy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-231
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore U-box UCLK Fixed Counter Package
Register Address: C10H, 3088 MSR_U_PMON_EVNTSEL0
Uncore U-box Perfmon Event Select for U-box Counter 0 Package
Register Address: C11H, 3089 MSR_U_PMON_EVNTSEL1
Uncore U-box Perfmon Event Select for U-box Counter 1 Package
Register Address: C16H, 3094 MSR_U_PMON_CTR0
Uncore U-box Perfmon Counter 0 Package
Register Address: C17H, 3095 MSR_U_PMON_CTR1
Uncore U-box Perfmon Counter 1 Package
Register Address: C24H, 3108 MSR_PCU_PMON_BOX_CTL
Uncore PCU Perfmon for PCU-box-wide Control Package
Register Address: C30H, 3120 MSR_PCU_PMON_EVNTSEL0
Uncore PCU Perfmon Event Select for PCU Counter 0 Package
Register Address: C31H, 3121 MSR_PCU_PMON_EVNTSEL1
Uncore PCU Perfmon Event Select for PCU Counter 1 Package
Register Address: C32H, 3122 MSR_PCU_PMON_EVNTSEL2
Uncore PCU Perfmon Event Select for PCU Counter 2 Package
Register Address: C33H, 3123 MSR_PCU_PMON_EVNTSEL3
Uncore PCU Perfmon Event Select for PCU Counter 3 Package
Register Address: C34H, 3124 MSR_PCU_PMON_BOX_FILTER
Uncore PCU Perfmon box-wide Filter Package
Register Address: C36H, 3126 MSR_PCU_PMON_CTR0
Uncore PCU Perfmon Counter 0 Package
Register Address: C37H, 3127 MSR_PCU_PMON_CTR1
Uncore PCU Perfmon Counter 1 Package
Register Address: C38H, 3128 MSR_PCU_PMON_CTR2
Uncore PCU Perfmon Counter 2 Package
Register Address: C39H, 3129 MSR_PCU_PMON_CTR3
Uncore PCU Perfmon Counter 3 Package
Register Address: D04H, 3332 MSR_C0_PMON_BOX_CTL
Uncore C-box 0 Perfmon Local Box Wide Control Package
Register Address: D10H, 3344 MSR_C0_PMON_EVNTSEL0
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 0 Package
Register Address: D11H, 3345 MSR_C0_PMON_EVNTSEL1
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 1 Package
Register Address: D12H, 3346 MSR_C0_PMON_EVNTSEL2
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 2 Package
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-232 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D13H, 3347 MSR_C0_PMON_EVNTSEL3
Uncore C-box 0 Perfmon Event Select for C-box 0 Counter 3 Package
Register Address: D14H, 3348 MSR_C0_PMON_BOX_FILTER
Uncore C-box 0 Perfmon Box Wide Filter Package
Register Address: D16H, 3350 MSR_C0_PMON_CTR0
Uncore C-box 0 Perfmon Counter 0 Package
Register Address: D17H, 3351 MSR_C0_PMON_CTR1
Uncore C-box 0 Perfmon Counter 1 Package
Register Address: D18H, 3352 MSR_C0_PMON_CTR2
Uncore C-box 0 Perfmon Counter 2 Package
Register Address: D19H, 3353 MSR_C0_PMON_CTR3
Uncore C-box 0 Perfmon Counter 3 Package
Register Address: D24H, 3364 MSR_C1_PMON_BOX_CTL
Uncore C-box 1 Perfmon Local Box Wide Control Package
Register Address: D30H, 3376 MSR_C1_PMON_EVNTSEL0
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 0 Package
Register Address: D31H, 3377 MSR_C1_PMON_EVNTSEL1
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 1 Package
Register Address: D32H, 3378 MSR_C1_PMON_EVNTSEL2
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 2 Package
Register Address: D33H, 3379 MSR_C1_PMON_EVNTSEL3
Uncore C-box 1 Perfmon Event Select for C-box 1 Counter 3 Package
Register Address: D34H, 3380 MSR_C1_PMON_BOX_FILTER
Uncore C-box 1 Perfmon Box Wide Filter Package
Register Address: D36H, 3382 MSR_C1_PMON_CTR0
Uncore C-box 1 Perfmon Counter 0 Package
Register Address: D37H, 3383 MSR_C1_PMON_CTR1
Uncore C-box 1 Perfmon Counter 1 Package
Register Address: D38H, 3384 MSR_C1_PMON_CTR2
Uncore C-box 1 Perfmon Counter 2 Package
Register Address: D39H, 3385 MSR_C1_PMON_CTR3
Uncore C-box 1 Perfmon Counter 3 Package
Register Address: D44H, 3396 MSR_C2_PMON_BOX_CTL
Uncore C-box 2 Perfmon Local Box Wide Control Package
Register Address: D50H, 3408 MSR_C2_PMON_EVNTSEL0
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 0 Package
Register Address: D51H, 3409 MSR_C2_PMON_EVNTSEL1
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-233
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 1 Package
Register Address: D52H, 3410 MSR_C2_PMON_EVNTSEL2
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 2 Package
Register Address: D53H, 3411 MSR_C2_PMON_EVNTSEL3
Uncore C-box 2 Perfmon Event Select for C-box 2 Counter 3 Package
Register Address: D54H, 3412 MSR_C2_PMON_BOX_FILTER
Uncore C-box 2 Perfmon Box Wide Filter Package
Register Address: D56H, 3414 MSR_C2_PMON_CTR0
Uncore C-box 2 Perfmon Counter 0 Package
Register Address: D57H, 3415 MSR_C2_PMON_CTR1
Uncore C-box 2 Perfmon Counter 1 Package
Register Address: D58H, 3416 MSR_C2_PMON_CTR2
Uncore C-box 2 Perfmon Counter 2 Package
Register Address: D59H, 3417 MSR_C2_PMON_CTR3
Uncore C-box 2 Perfmon Counter 3 Package
Register Address: D64H, 3428 MSR_C3_PMON_BOX_CTL
Uncore C-box 3 Perfmon Local Box Wide Control Package
Register Address: D70H, 3440 MSR_C3_PMON_EVNTSEL0
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 0 Package
Register Address: D71H, 3441 MSR_C3_PMON_EVNTSEL1
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 1 Package
Register Address: D72H, 3442 MSR_C3_PMON_EVNTSEL2
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 2 Package
Register Address: D73H, 3443 MSR_C3_PMON_EVNTSEL3
Uncore C-box 3 Perfmon Event Select for C-box 3 Counter 3 Package
Register Address: D74H, 3444 MSR_C3_PMON_BOX_FILTER
Uncore C-box 3 Perfmon Box Wide Filter Package
Register Address: D76H, 3446 MSR_C3_PMON_CTR0
Uncore C-box 3 Perfmon Counter 0 Package
Register Address: D77H, 3447 MSR_C3_PMON_CTR1
Uncore C-box 3 Perfmon Counter 1 Package
Register Address: D78H, 3448 MSR_C3_PMON_CTR2
Uncore C-box 3 Perfmon Counter 2 Package
Register Address: D79H, 3449 MSR_C3_PMON_CTR3
Uncore C-box 3 Perfmon Counter 3 Package
Register Address: D84H, 3460 MSR_C4_PMON_BOX_CTL
Uncore C-box 4 Perfmon Local Box Wide Control Package
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-234 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: D90H, 3472 MSR_C4_PMON_EVNTSEL0
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 0 Package
Register Address: D91H, 3473 MSR_C4_PMON_EVNTSEL1
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 1 Package
Register Address: D92H, 3474 MSR_C4_PMON_EVNTSEL2
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 2 Package
Register Address: D93H, 3475 MSR_C4_PMON_EVNTSEL3
Uncore C-box 4 Perfmon Event Select for C-box 4 Counter 3 Package
Register Address: D94H, 3476 MSR_C4_PMON_BOX_FILTER
Uncore C-box 4 Perfmon Box Wide Filter Package
Register Address: D96H, 3478 MSR_C4_PMON_CTR0
Uncore C-box 4 Perfmon Counter 0 Package
Register Address: D97H, 3479 MSR_C4_PMON_CTR1
Uncore C-box 4 Perfmon Counter 1 Package
Register Address: D98H, 3480 MSR_C4_PMON_CTR2
Uncore C-box 4 Perfmon Counter 2 Package
Register Address: D99H, 3481 MSR_C4_PMON_CTR3
Uncore C-box 4 Perfmon Counter 3 Package
Register Address: DA4H, 3492 MSR_C5_PMON_BOX_CTL
Uncore C-box 5 Perfmon Local Box Wide Control Package
Register Address: DB0H, 3504 MSR_C5_PMON_EVNTSEL0
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 0 Package
Register Address: DB1H, 3505 MSR_C5_PMON_EVNTSEL1
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 1 Package
Register Address: DB2H, 3506 MSR_C5_PMON_EVNTSEL2
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 2 Package
Register Address: DB3H, 3507 MSR_C5_PMON_EVNTSEL3
Uncore C-box 5 Perfmon Event Select for C-box 5 Counter 3 Package
Register Address: DB4H, 3508 MSR_C5_PMON_BOX_FILTER
Uncore C-box 5 Perfmon Box Wide Filter Package
Register Address: DB6H, 3510 MSR_C5_PMON_CTR0
Uncore C-box 5 Perfmon Counter 0 Package
Register Address: DB7H, 3511 MSR_C5_PMON_CTR1
Uncore C-box 5 Perfmon Counter 1 Package
Register Address: DB8H, 3512 MSR_C5_PMON_CTR2
Uncore C-box 5 Perfmon Counter 2 Package
Register Address: DB9H, 3513 MSR_C5_PMON_CTR3
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-235
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-box 5 Perfmon Counter 3 Package
Register Address: DC4H, 3524 MSR_C6_PMON_BOX_CTL
Uncore C-box 6 Perfmon Local Box Wide Control Package
Register Address: DD0H, 3536 MSR_C6_PMON_EVNTSEL0
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 0 Package
Register Address: DD1H, 3537 MSR_C6_PMON_EVNTSEL1
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 1 Package
Register Address: DD2H, 3538 MSR_C6_PMON_EVNTSEL2
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 2 Package
Register Address: DD3H, 3539 MSR_C6_PMON_EVNTSEL3
Uncore C-box 6 Perfmon Event Select for C-box 6 Counter 3 Package
Register Address: DD4H, 3540 MSR_C6_PMON_BOX_FILTER
Uncore C-box 6 Perfmon Box Wide Filter Package
Register Address: DD6H, 3542 MSR_C6_PMON_CTR0
Uncore C-box 6 Perfmon Counter 0 Package
Register Address: DD7H, 3543 MSR_C6_PMON_CTR1
Uncore C-box 6 Perfmon Counter 1 Package
Register Address: DD8H, 3544 MSR_C6_PMON_CTR2
Uncore C-box 6 Perfmon Counter 2 Package
Register Address: DD9H, 3545 MSR_C6_PMON_CTR3
Uncore C-box 6 Perfmon Counter 3 Package
Register Address: DE4H, 3556 MSR_C7_PMON_BOX_CTL
Uncore C-box 7 Perfmon Local Box Wide Control Package
Register Address: DF0H, 3568 MSR_C7_PMON_EVNTSEL0
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 0 Package
Register Address: DF1H, 3569 MSR_C7_PMON_EVNTSEL1
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 1 Package
Register Address: DF2H, 3570 MSR_C7_PMON_EVNTSEL2
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 2 Package
Register Address: DF3H, 3571 MSR_C7_PMON_EVNTSEL3
Uncore C-box 7 Perfmon Event Select for C-box 7 Counter 3 Package
Register Address: DF4H, 3572 MSR_C7_PMON_BOX_FILTER
Uncore C-box 7 Perfmon Box Wide Filter Package
Register Address: DF6H, 3574 MSR_C7_PMON_CTR0
Uncore C-box 7 Perfmon Counter 0 Package
Register Address: DF7H, 3575 MSR_C7_PMON_CTR1
Uncore C-box 7 Perfmon Counter 1 Package
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-236 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.12 MSRS IN THE 3RD GENERATION INTEL® CORE™ PROCESSOR FAMILY BASED
ON IVY BRIDGE MICROARCHITECTURE
The 3rd generation Intel
®
Core™ processor family and the Intel
®
Xeon
®
processor E3-1200v2 product family
based on Ivy Bridge microarchitecture support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and
Table 2-25. These processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3AH.
Register Address: DF8H, 3576 MSR_C7_PMON_CTR2
Uncore C-box 7 Perfmon Counter 2 Package
Register Address: DF9H, 3577 MSR_C7_PMON_CTR3
Uncore C-box 7 Perfmon Counter 3 Package
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs at. Frequency =
ratio * 100 MHz.
Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode is programmable.
When set to 0, indicates that TDP Limit for Turbo mode is not
programmable.
Package
31:30 Reserved.
32 Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported. When set to 0, indicates
LPM is not supported.
Package
34:33 Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
03: Reserved
Package
39:35 Reserved.
Table 2-24. Uncore PMU MSRs in Intel® Xeon® Processor E5 Family (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-237
MODEL-SPECIFIC REGISTERS (MSRS)
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
Package
55:48 Minimum Operating Ratio (R/O)
Contains the minimum supported operating ratio in units of 100 MHz.
Package
63:56 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated
to MWAIT extension C-state parameters or ACPI C-States.
See http://biosbits.org.
Core
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
24:16 Reserved
25 C3 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote C6/C7 requests to C3
based on uncore auto-demote information.
26 C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote C3/C6/C7 requests to
C1 based on uncore auto-demote information.
27 Enable C3 Undemotion (R/W)
When set, enables undemotion from demoted C3.
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-238 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
28 Enable C1 Undemotion (R/W)
When set, enables undemotion from demoted C1.
63:29 Reserved.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 648H, 1608 MSR_CONFIG_TDP_NOMINAL
Base TDP Ratio (R/O) Package
7:0 Config_TDP_Base
Base TDP level ratio to be used for this specific processor (in units of 100
MHz).
63:8 Reserved.
Register Address: 649H, 1609 MSR_CONFIG_TDP_LEVEL1
ConfigTDP Level 1 ratio and power level (R/O) Package
14:0 PKG_TDP_LVL1
Power setting for ConfigTDP Level 1.
15 Reserved.
23:16 Config_TDP_LVL1_Ratio
ConfigTDP level 1 ratio to be used for this specific processor.
31:24 Reserved.
46:32 PKG_MAX_PWR_LVL1
Max Power setting allowed for ConfigTDP Level 1.
47 Reserved.
62:48 PKG_MIN_PWR_LVL1
MIN Power setting allowed for ConfigTDP Level 1.
63 Reserved.
Register Address: 64AH, 1610 MSR_CONFIG_TDP_LEVEL2
ConfigTDP Level 2 ratio and power level (R/O) Package
14:0 PKG_TDP_LVL2
Power setting for ConfigTDP Level 2.
15 Reserved.
23:16 Config_TDP_LVL2_Ratio
ConfigTDP level 2 ratio to be used for this specific processor.
31:24 Reserved.
46:32 PKG_MAX_PWR_LVL2
Max Power setting allowed for ConfigTDP Level 2.
47 Reserved.
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-239
MODEL-SPECIFIC REGISTERS (MSRS)
2.12.1 MSRs in the Intel® Xeon® Processor E5 v2 Product Family Based on Ivy Bridge-E
Microarchitecture
Table 2-26 lists model-specific registers (MSRs) that are specific to the Intel
®
Xeon
®
Processor E5 v2 Product
Family (based on Ivy Bridge-E microarchitecture). These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_3EH; see Table 2-1. These processors supports the MSR interfaces listed
in Table 2-20 and Table 2-26.
62:48 PKG_MIN_PWR_LVL2
MIN Power setting allowed for ConfigTDP Level 2.
63 Reserved.
Register Address: 64BH, 1611 MSR_CONFIG_TDP_CONTROL
ConfigTDP Control (R/W) Package
1:0 TDP_LEVEL (RW/L)
System BIOS can program this field.
30:2 Reserved.
31 Config_TDP_Lock (RW/L)
When this bit is set, the content of this register is locked until a reset.
63:32 Reserved.
Register Address: 64CH, 1612 MSR_TURBO_ACTIVATION_RATIO
ConfigTDP Control (R/W) Package
7:0 MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8 Reserved.
31 TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is locked until a reset.
63:32 Reserved.
See Table 2-20, Table 2-21, and Table 2-22 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3AH.
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 4EH, 78 IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W) Package
0LockOut (R/WO)
See Table 2-2.
1 Enable_PPIN (R/W)
See Table 2-2.
63:2 Reserved.
Table 2-25. Additional MSRs Supported by 3rd Generation Intel® Core™ Processors Based on Ivy Bridge
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-240 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 4FH, 79 IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O) Package
63:0 Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs at. Frequency =
ratio * 100 MHz.
Package
22:16 Reserved.
23 PPIN_CAP (R/O)
When set to 1, indicates that Protected Processor Inventory Number (PPIN)
capability can be enabled for a privileged system inventory agent to read
PPIN from MSR_PPIN.
When set to 0, PPIN capability is not supported. An attempt to access
MSR_PPIN_CTL or MSR_PPIN will cause #GP.
Package
27:24 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo mode
is disabled.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode is programmable.
When set to 0, indicates TDP Limit for Turbo mode is not programmable.
Package
30 Programmable TJ OFFSET (R/O)
When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid
and writable to specify a temperature offset.
Package
39:31 Reserved.
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
Core
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-241
MODEL-SPECIFIC REGISTERS (MSRS)
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-sate support)
001b: C2
010b: C6 no retention
011b: C6 retention
100b: C7
101b: C7s
111: No package C-state limit.
Note: This field cannot be used to limit package C-state to C3.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO register specified by
MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/WO)
When set, locks bits 15:0 of this register until next reset.
63:16 Reserved.
Register Address: 179H, 377 IA32_MCG_CAP
Global Machine Check Capability (R/O) Thread
7:0 Count
8 MCG_CTL_P
9 MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved.
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 Reserved.
26 MCG_ELOG_P
63:27 Reserved.
Register Address: 17FH, 383 MSR_ERROR_CONTROL
MC Bank Error Configuration (R/W) Package
0 Reserved.
1 MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits 36:32.
63:2 Reserved.
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-242 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Package
15:0 Reserved.
23:16 Temperature Target (R/O)
The minimum temperature at which PROCHOT# will be asserted. The value
is degrees C.
27:24 TCC Activation Offset (R/W)
Specifies a temperature offset in degrees C from the temperature target
(bits 23:16). PROCHOT# will assert at the offset target temperature. Write
is permitted only if MSR_PLATFORM_INFO.[30] is set.
63:28 Reserved.
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0. R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
Package
15:8 Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10 core active.
Package
23:16 Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
Package
31:24 Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
Package
63:32 Reserved.
Register Address: 285H, 645 IA32_MC5_CTL2
See Table 2-2. Package
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 287H, 647 IA32_MC7_CTL2
See Table 2-2. Package
Register Address: 288H, 648 IA32_MC8_CTL2
See Table 2-2. Package
Register Address: 289H, 649 IA32_MC9_CTL2
See Table 2-2. Package
Register Address: 28AH, 650 IA32_MC10_CTL2
See Table 2-2. Package
Register Address: 28BH, 651 IA32_MC11_CTL2
See Table 2-2. Package
Register Address: 28CH, 652 IA32_MC12_CTL2
See Table 2-2. Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-243
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 28DH, 653 IA32_MC13_CTL2
See Table 2-2. Package
Register Address: 28EH, 654 IA32_MC14_CTL2
See Table 2-2. Package
Register Address: 28FH, 655 IA32_MC15_CTL2
See Table 2-2. Package
Register Address: 290H, 656 IA32_MC16_CTL2
See Table 2-2. Package
Register Address: 291H, 657 IA32_MC17_CTL2
See Table 2-2. Package
Register Address: 292H, 658 IA32_MC18_CTL2
See Table 2-2. Package
Register Address: 293H, 659 IA32_MC19_CTL2
See Table 2-2. Package
Register Address: 294H, 660 IA32_MC20_CTL2
See Table 2-2. Package
Register Address: 295H, 661 IA32_MC21_CTL2
See Table 2-2. Package
Register Address: 296H, 662 IA32_MC22_CTL2
See Table 2-2. Package
Register Address: 297H, 663 IA32_MC23_CTL2IA32_MC23_CTL2
See Table 2-2. Package
Register Address: 298H, 664 IA32_MC24_CTL2
See Table 2-2. Package
Register Address: 299H, 665 IA32_MC25_CTL2
See Table 2-2. Package
Register Address: 29AH, 666 IA32_MC26_CTL2
See Table 2-2. Package
Register Address: 29BH, 667 IA32_MC27_CTL2
See Table 2-2. Package
Register Address: 29CH, 668 IA32_MC28_CTL2
See Table 2-2. Package
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI module.
Package
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI module.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-244 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI module.
Package
Register Address: 417H, 1047 IA32_MC5_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI module.
Package
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 420H, 1056 IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 421H, 1057 IA32_MC8_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 422H, 1058 IA32_MC8_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-245
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 423H, 1059 IA32_MC8_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC7 and MC 8 report MC errors from the two home agents.
Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 425H, 1061 IA32_MC9_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 426H, 1062 IA32_MC9_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42BH, 1067 IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42CH, 1068 IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Bank MC11 reports MC errors from a specific channel of the integrated memory controller.
Package
Register Address: 42DH, 1069 IA32_MC11_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.”
Bank MC11 reports MC errors from a specific channel of the integrated memory controller.
Package
Register Address: 42EH, 1070 IA32_MC11_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Bank MC11 reports MC errors from a specific channel of the integrated memory controller.
Package
Register Address: 42FH, 1071 IA32_MC11_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Bank MC11 reports MC errors from a specific channel of the integrated memory controller.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-246 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 430H, 1072 IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 431H, 1073 IA32_MC12_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 432H, 1074 IA32_MC12_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 433H, 1075 IA32_MC12_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 434H, 1076 IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 435H, 1077 IA32_MC13_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 436H, 1078 IA32_MC13_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 437H, 1079 IA32_MC13_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 438H, 1080 IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 439H, 1081 IA32_MC14_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43AH, 1082 IA32_MC14_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43BH, 1083 IA32_MC14_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43CH, 1084 IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-247
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 43DH, 1085 IA32_MC15_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43EH, 1086 IA32_MC15_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43FH, 1087 IA32_MC15_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 440H, 1088 IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 441H, 1089 IA32_MC16_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 442H, 1090 IA32_MC16_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 443H, 1091 IA32_MC16_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 445H, 1093 IA32_MC17_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 449H, 1097 IA32_MC18_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-248 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 44FH, 1103 IA32_MC19_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 450H, 1104 IA32_MC20_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 451H, 1105 IA32_MC20_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.”
Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 452H, 1106 IA32_MC20_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 453H, 1107 IA32_MC20_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Bank MC20 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 454H, 1108 IA32_MC21_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 455H, 1109 IA32_MC21_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 456H, 1110 IA32_MC21_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-249
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 457H, 1111 IA32_MC21_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 458H, 1112 IA32_MC22_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 459H, 1113 IA32_MC22_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 45AH, 1114 IA32_MC22_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 45BH, 1115 IA32_MC22_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC22 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 45CH, 1116 IA32_MC23_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 45DH, 1117 IA32_MC23_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 45EH, 1118 IA32_MC23_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 45FH, 1119 IA32_MC23_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC23 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 460H, 1120 IA32_MC24_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 461H, 1121 IA32_MC24_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 462H, 1122 IA32_MC24_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 463H, 1123 IA32_MC24_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC24 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-250 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 464H, 1124 IA32_MC25_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 465H, 1125 IA32_MC25_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 466H, 1126 IA32_MC25_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 467H, 1127 IA32_MC2MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC25 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 468H, 1128 IA32_MC26_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 469H, 1129 IA32_MC26_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 46AH, 1130 IA32_MC26_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 46BH, 1131 IA32_MC26_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC26 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 46CH, 1132 IA32_MC27_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 46DH, 1133 IA32_MC27_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 46EH, 1134 IA32_MC27_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 46FH, 1135 IA32_MC27_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC27 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 470H, 1136 IA32_MC28_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-251
MODEL-SPECIFIC REGISTERS (MSRS)
2.12.2 Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family
The Intel
®
Xeon
®
processor E7 v2 family (based on Ivy Bridge-E microarchitecture) with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3EH supports the MSR interfaces listed in Table 2-20, Table 2-26, and
Table 2-27.
Register Address: 471H, 1137 IA32_MC28_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 472H, 1138 IA32_MC28_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 473H, 1139 IA32_MC28_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC28 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 613H, 1555 MSR_PKG_PERF_STATUS
Package RAPL Perf Status (R/O) Package
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
See Table 2-20, for other MSR definitions applicable to Intel Xeon processor E5 v2 with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3EH.
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Table 2-26. MSRs Supported by the Intel® Xeon® Processor E5 v2 Product Family (Ivy Bridge-E Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-252 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Thread
0Lock (R/WL)
1 Enable VMX Inside SMX Operation (R/WL)
2 Enable VMX Outside SMX Operation (R/WL)
14:8 SENTER Local Functions Enables (R/WL)
15 SENTER Global Functions Enable (R/WL)
63:16 Reserved.
Register Address: 179H, 377 IA32_MCG_CAP
Global Machine Check Capability (R/O) Thread
7:0 Count
8 MCG_CTL_P
9MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved.
23:16 MCG_EXT_CNT
24 MCG_SER_P
63:25 Reserved.
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status (R/W) Thread
0RIPV
1EIPV
2MCIP
3LMCE Signaled
63:4 Reserved.
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
Package
15:8 Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10core active.
Package
23:16 Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
Package
31:24 Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
Package
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-253
MODEL-SPECIFIC REGISTERS (MSRS)
39:32 Maximum Ratio Limit for 13C
Maximum turbo ratio limit of 13 core active.
Package
47:40 Maximum Ratio Limit for 14C
Maximum turbo ratio limit of 14 core active.
Package
55:48 Maximum Ratio Limit for 15C
Maximum turbo ratio limit of 15 core active.
Package
62:56 Reserved.
63 Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration
1
specified in
MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).
Package
Register Address: 29DH, 669 IA32_MC29_CTL2
See Table 2-2. Package
Register Address: 29EH, 670 IA32_MC30_CTL2
See Table 2-2. Package
Register Address: 29FH, 671 IA32_MC31_CTL2
See Table 2-2. Package
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Section 20.3.1.1.1, “Processor Event Based Sampling (PEBS).” Thread
n:0 Enable PEBS on IA32_PMCx. (R/W)
31:n+1 Reserved.
32+m:32 Enable Load Latency on IA32_PMCx. (R/W)
63:33+m Reserved.
Register Address: 41BH, 1051 IA32_MC6_MISC
Misc MAC Information of Integrated I/O (R/O)
See Section 16.3.2.4.
Package
5:0 Recoverable Address LSB
8:6 Address Mode
15:9 Reserved.
31:16 PCI Express Requestor ID
39:32 PCI Express Segment Number
63:32 Reserved.
Register Address: 474H, 1140 IA32_MC29_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 475H, 1141 IA32_MC29_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-254 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.12.3 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Intel Xeon Processor E5 v2 and E7 v2 families are based on the Ivy Bridge-E microarchitecture. The MSR-based
uncore PMU interfaces are listed in Table 2-24 and Table 2-28. For complete detail of the uncore PMU, refer to Intel
Register Address: 476H, 1142 IA32_MC29_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 477H, 1143 IA32_MC29_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC29 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 478H, 1144 IA32_MC30_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 479H, 1145 IA32_MC30_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 47AH, 1146 IA32_MC30_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 47BH, 1147 IA32_MC30_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC30 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 47CH, 1148 IA32_MC31_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 47DH, 1149 IA32_MC31_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 47EH, 1150 IA32_MC31_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
Register Address: 47FH, 1147 IA32_MC31_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC31 reports MC errors from a specific CBo (core broadcast) and its corresponding slice of L3.
Package
See Table 2-20, Table 2-26 for other MSR definitions applicable to Intel Xeon processor E7 v2 with a CPUID Signature
DisplayFamily_DisplayModel value of 06_3AH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
Table 2-27. Additional MSRs Supported by the Intel® Xeon® Processor E7 v2 Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_3EH (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-255
MODEL-SPECIFIC REGISTERS (MSRS)
Xeon Processor E5 v2 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID
Signature DisplayFamily_DisplayModel value of 06_3EH.
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: C00H, 3072 MSR_PMON_GLOBAL_CTL
Uncore Perfmon Per-Socket Global Control Package
Register Address: C01H, 3073 MSR_PMON_GLOBAL_STATUS
Uncore Perfmon Per-Socket Global Status Package
Register Address: C06H, 3078 MSR_PMON_GLOBAL_CONFIG
Uncore Perfmon Per-Socket Global Configuration Package
Register Address: C15H, 3093 MSR_U_PMON_BOX_STATUS
Uncore U-box Perfmon U-Box Wide Status Package
Register Address: C35H, 3125 MSR_PCU_PMON_BOX_STATUS
Uncore PCU Perfmon Box Wide Status Package
Register Address: D1AH, 3354 MSR_C0_PMON_BOX_FILTER1
Uncore C-Box 0 Perfmon Box Wide Filter1 Package
Register Address: D3AH, 3386 MSR_C1_PMON_BOX_FILTER1
Uncore C-Box 1 Perfmon Box Wide Filter1 Package
Register Address: D5AH, 3418 MSR_C2_PMON_BOX_FILTER1
Uncore C-Box 2 Perfmon Box Wide Filter1 Package
Register Address: D7AH, 3450 MSR_C3_PMON_BOX_FILTER1
Uncore C-Box 3 Perfmon Box Wide Filter1 Package
Register Address: D9AH, 3482 MSR_C4_PMON_BOX_FILTER1
Uncore C-Box 4 Perfmon Box Wide Filter1 Package
Register Address: DBAH, 3514 MSR_C5_PMON_BOX_FILTER1
Uncore C-Box 5 Perfmon Box Wide Filter1 Package
Register Address: DDAH, 3546 MSR_C6_PMON_BOX_FILTER1
Uncore C-Box 6 Perfmon Box Wide Filter1 Package
Register Address: DFAH, 3578 MSR_C7_PMON_BOX_FILTER1
Uncore C-Box 7 Perfmon Box Wide Filter1 Package
Register Address: E04H, 3588 MSR_C8_PMON_BOX_CTL
Uncore C-Box 8 Perfmon Local Box Wide Control Package
Register Address: E10H, 3600 MSR_C8_PMON_EVNTSEL0
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 0 Package
Register Address: E11H, 3601 MSR_C8_PMON_EVNTSEL1
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 1 Package
Register Address: E12H, 3602 MSR_C8_PMON_EVNTSEL2
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 2 Package
Register Address: E13H, 3603 MSR_C8_PMON_EVNTSEL3
2-256 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 3 Package
Register Address: E14H, 3604 MSR_C8_PMON_BOX_FILTER
Uncore C-Box 8 Perfmon Box Wide Filter Package
Register Address: E16H, 3606 MSR_C8_PMON_CTR0
Uncore C-Box 8 Perfmon Counter 0 Package
Register Address: E17H, 3607 MSR_C8_PMON_CTR1
Uncore C-Box 8 Perfmon Counter 1 Package
Register Address: E18H, 3608 MSR_C8_PMON_CTR2
Uncore C-Box 8 Perfmon Counter 2 Package
Register Address: E19H, 3609 MSR_C8_PMON_CTR3
Uncore C-Box 8 Perfmon Counter 3 Package
Register Address: E1AH, 3610 MSR_C8_PMON_BOX_FILTER1
Uncore C-Box 8 Perfmon Box Wide Filter1 Package
Register Address: E24H, 3620 MSR_C9_PMON_BOX_CTL
Uncore C-Box 9 Perfmon Local Box Wide Control Package
Register Address: E30H, 3632 MSR_C9_PMON_EVNTSEL0
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 0 Package
Register Address: E31H, 3633 MSR_C9_PMON_EVNTSEL1
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 1 Package
Register Address: E32H, 3634 MSR_C9_PMON_EVNTSEL2
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 2 Package
Register Address: E33H, 3635 MSR_C9_PMON_EVNTSEL3
Uncore C-Box 9 Perfmon Event Select for C-box 9 Counter 3 Package
Register Address: E34H, 3636 MSR_C9_PMON_BOX_FILTER
Uncore C-Box 9 Perfmon Box Wide Filter Package
Register Address: E36H, 3638 MSR_C9_PMON_CTR0
Uncore C-Box 9 Perfmon Counter 0 Package
Register Address: E37H, 3639 MSR_C9_PMON_CTR1
Uncore C-Box 9 Perfmon Counter 1 Package
Register Address: E38H, 3640 MSR_C9_PMON_CTR2
Uncore C-Box 9 Perfmon Counter 2 Package
Register Address: E39H, 3641 MSR_C9_PMON_CTR3
Uncore C-Box 9 Perfmon Counter 3 Package
Register Address: E3AH, 3642 MSR_C9_PMON_BOX_FILTER1
Uncore C-Box 9 Perfmon Box Wide Filter1 Package
Register Address: E44H, 3652 MSR_C10_PMON_BOX_CTL
Uncore C-Box 10 Perfmon Local Box Wide Control Package
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-257
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E50H, 3664 MSR_C10_PMON_EVNTSEL0
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 0 Package
Register Address: E51H, 3665 MSR_C10_PMON_EVNTSEL1
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 1 Package
Register Address: E52H, 3666 MSR_C10_PMON_EVNTSEL2
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2 Package
Register Address: E53H, 3667 MSR_C10_PMON_EVNTSEL3
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 3 Package
Register Address: E54H, 3668 MSR_C10_PMON_BOX_FILTER
Uncore C-Box 10 Perfmon Box Wide Filter Package
Register Address: E56H, 3670 MSR_C10_PMON_CTR0
Uncore C-Box 10 Perfmon Counter 0 Package
Register Address: E57H, 3671 MSR_C10_PMON_CTR1
Uncore C-Box 10 Perfmon Counter 1 Package
Register Address: E58H, 3672 MSR_C10_PMON_CTR2
Uncore C-Box 10 Perfmon Counter 2 Package
Register Address: E59H, 3673 MSR_C10_PMON_CTR3
Uncore C-Box 10 Perfmon Counter 3 Package
Register Address: E5AH, 3674 MSR_C10_PMON_BOX_FILTER1
Uncore C-Box 10 Perfmon Box Wide Filter1 Package
Register Address: E64H, 3684 MSR_C11_PMON_BOX_CTL
Uncore C-Box 11 Perfmon Local Box Wide Control Package
Register Address: E70H, 3696 MSR_C11_PMON_EVNTSEL0
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 0 Package
Register Address: E71H, 3697 MSR_C11_PMON_EVNTSEL1
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 1 Package
Register Address: E72H, 3698 MSR_C11_PMON_EVNTSEL2
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 2 Package
Register Address: E73H, 3699 MSR_C11_PMON_EVNTSEL3
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 3 Package
Register Address: E74H, 3700 MSR_C11_PMON_BOX_FILTER
Uncore C-Box 11 Perfmon Box Wide Filter Package
Register Address: E76H, 3702 MSR_C11_PMON_CTR0
Uncore C-Box 11 Perfmon Counter 0 Package
Register Address: E77H, 3703 MSR_C11_PMON_CTR1
Uncore C-Box 11 Perfmon Counter 1 Package
Register Address: E78H, 3704 MSR_C11_PMON_CTR2
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-258 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 11 Perfmon Counter 2 Package
Register Address: E79H, 3705 MSR_C11_PMON_CTR3
Uncore C-Box 11 Perfmon Counter 3 Package
Register Address: E7AH, 3706 MSR_C11_PMON_BOX_FILTER1
Uncore C-Box 11 Perfmon Box Wide Filter1 Package
Register Address: E84H, 3716 MSR_C12_PMON_BOX_CTL
Uncore C-Box 12 Perfmon Local Box Wide Control Package
Register Address: E90H, 3728 MSR_C12_PMON_EVNTSEL0
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 0 Package
Register Address: E91H, 3729 MSR_C12_PMON_EVNTSEL1
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 1 Package
Register Address: E92H, 3730 MSR_C12_PMON_EVNTSEL2
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 2 Package
Register Address: E93H, 3731 MSR_C12_PMON_EVNTSEL3
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 3 Package
Register Address: E94H, 3732 MSR_C12_PMON_BOX_FILTER
Uncore C-Box 12 Perfmon Box Wide Filter Package
Register Address: E96H, 3734 MSR_C12_PMON_CTR0
Uncore C-Box 12 Perfmon Counter 0 Package
Register Address: E97H, 3735 MSR_C12_PMON_CTR1
Uncore C-Box 12 Perfmon Counter 1 Package
Register Address: E98H, 3736 MSR_C12_PMON_CTR2
Uncore C-Box 12 Perfmon Counter 2 Package
Register Address: E99H, 3737 MSR_C12_PMON_CTR3
Uncore C-Box 12 Perfmon Counter 3 Package
Register Address: E9AH, 3738 MSR_C12_PMON_BOX_FILTER1
Uncore C-Box 12 Perfmon Box Wide Filter1 Package
Register Address: EA4H, 3748 MSR_C13_PMON_BOX_CTL
Uncore C-Box 13 Perfmon Local Box Wide Control Package
Register Address: EB0H, 3760 MSR_C13_PMON_EVNTSEL0
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 0 Package
Register Address: EB1H, 3761 MSR_C13_PMON_EVNTSEL1
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 1 Package
Register Address: EB2H, 3762 MSR_C13_PMON_EVNTSEL2
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 2 Package
Register Address: EB3H, 3763 MSR_C13_PMON_EVNTSEL3
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3 Package
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-259
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: EB4H, 3764 MSR_C13_PMON_BOX_FILTER
Uncore C-Box 13 Perfmon Box Wide Filter Package
Register Address: EB6H, 3766 MSR_C13_PMON_CTR0
Uncore C-Box 13 Perfmon Counter 0 Package
Register Address: EB7H, 3767 MSR_C13_PMON_CTR1
Uncore C-Box 13 Perfmon Counter 1 Package
Register Address: EB8H, 3768 MSR_C13_PMON_CTR2
Uncore C-Box 13 Perfmon Counter 2 Package
Register Address: EB9H, 3769 MSR_C13_PMON_CTR3
Uncore C-Box 13 Perfmon Counter 3 Package
Register Address: EBAH, 3770 MSR_C13_PMON_BOX_FILTER1
Uncore C-Box 13 Perfmon Box Wide Filter1 Package
Register Address: EC4H, 3780 MSR_C14_PMON_BOX_CTL
Uncore C-Box 14 Perfmon Local Box Wide Control Package
Register Address: ED0H, 3792 MSR_C14_PMON_EVNTSEL0
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 0 Package
Register Address: ED1H, 3793 MSR_C14_PMON_EVNTSEL1
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 1 Package
Register Address: ED2H, 3794 MSR_C14_PMON_EVNTSEL2
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 2 Package
Register Address: ED3H, 3795 MSR_C14_PMON_EVNTSEL3
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 3 Package
Register Address: ED4H, 3796 MSR_C14_PMON_BOX_FILTER
Uncore C-Box 14 Perfmon Box Wide Filter Package
Register Address: ED6H, 3798 MSR_C14_PMON_CTR0
Uncore C-Box 14 Perfmon Counter 0 Package
Register Address: ED7H, 3799 MSR_C14_PMON_CTR1
Uncore C-Box 14 Perfmon Counter 1 Package
Register Address: ED8H, 3800 MSR_C14_PMON_CTR2
Uncore C-Box 14 Perfmon Counter 2 Package
Register Address: ED9H, 3801 MSR_C14_PMON_CTR3
Uncore C-Box 14 Perfmon Counter 3 Package
Register Address: EDAH, 3802 MSR_C14_PMON_BOX_FILTER1
Uncore C-Box 14 Perfmon Box Wide Filter1 Package
Table 2-28. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v2 and E7 v2 Families (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-260 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.13 MSRS IN THE 4TH GENERATION INTEL® CORE™ PROCESSORS BASED ON
HASWELL MICROARCHITECTURE
The 4th generation Intel
®
Core™ processor family and the Intel
®
Xeon
®
processor E3-1200v3 product family
(based on Haswell microarchitecture), with a CPUID Signature DisplayFamily_DisplayModel value of 06_3CH,
06_45H, or 06_46H, support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, and Table 2-29. For an
MSR listed in Table 2-20 that also appears in Table 2-29, Table 2-29 supersedes Table 2-20.
The MSRs listed in Table 2-29 also apply to processors based on Haswell-E microarchitecture (see Section 2.14).
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 3BH, 59 IA32_TSC_ADJUST
Per-Logical-Processor TSC ADJUST (R/W)
See Table 2-2.
Thread
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs at. Frequency =
ratio * 100 MHz.
Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode is
enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode is programmable.
When set to 0, indicates TDP Limit for Turbo mode is not programmable.
Package
31:30 Reserved.
32 Low Power Mode Support (LPM) (R/O)
When set to 1, indicates that LPM is supported. When set to 0, indicates
LPM is not supported.
Package
34:33 Number of ConfigTDP Levels (R/O)
00: Only Base TDP level available.
01: One additional TDP level available.
02: Two additional TDP level available.
03: Reserved.
Package
39:35 Reserved.
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
Package
55:48 Minimum Operating Ratio (R/O)
Contains the minimum supported operating ratio in units of 100 MHz.
Package
63:56 Reserved.
Vol. 4 2-261
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 186H, 390 IA32_PERFEVTSEL0
Performance Event Select for Counter 0 (R/W)
Supports all fields described inTable 2-2 and the fields below.
Thread
32 IN_TX: See Section 20.3.6.5.1.
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results.
Register Address: 187H, 391 IA32_PERFEVTSEL1
Performance Event Select for Counter 1 (R/W)
Supports all fields described inTable 2-2 and the fields below.
Thread
32 IN_TX: See Section 20.3.6.5.1.
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results.
Register Address: 188H, 392 IA32_PERFEVTSEL2
Performance Event Select for Counter 2 (R/W)
Supports all fields described inTable 2-2 and the fields below.
Thread
32 IN_TX: See Section 20.3.6.5.1.
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results.
33 IN_TXCP: See Section 20.3.6.5.1.
When IN_TXCP=1 & IN_TX=1 and in sampling, a spurious PMI may occur
and transactions may continuously abort near overflow conditions.
Software should favor using IN_TXCP for counting over sampling. If
sampling, software should use large “sample-after” value after clearing
the counter configured to use IN_TXCP and also always reset the counter
even when no overflow condition was reported.
Register Address: 189H, 393 IA32_PERFEVTSEL3
Performance Event Select for Counter 3 (R/W)
Supports all fields described inTable 2-2 and the fields below.
Thread
32 IN_TX: See Section 20.3.6.5.1
When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to
prevent incorrect results.
Register Address: 1C8H, 456 MSR_LBR_SELECT
Last Branch Record Filtering Select Register (R/W) Thread
0CPL_EQ_0
1 CPL_NEQ_0
2JCC
3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET
6 NEAR_IND_JMP
7 NEAR_REL_JMP
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-262 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
8 FAR_BRANCH
9 EN_CALL_STACK
63:9 Reserved.
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
See Table 2-2.
Thread
0 LBR: Last Branch Record
1BTF
5:2 Reserved.
6 TR: Branch Trace
7 BTS: Log Branch Trace Message to BTS Buffer
8BTINT
9 BTS_OFF_OS
10 BTS_OFF_USER
11 FREEZE_LBR_ON_PMI
12 FREEZE_PERFMON_ON_PMI
13 ENABLE_UNCORE_PMI
14 FREEZE_WHILE_SMM
15 RTM_DEBUG
63:15 Reserved.
Register Address: 491H, 1169 IA32_VMX_VMFUNC
Capability Reporting Register of VM-Function Controls (R/O)
See Table 2-2.
Thread
Register Address: 60BH, 1548 MSR_PKGC_IRTL1
Package C6/C7 Interrupt Response Limit 1 (R/W)
This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or
C7 state. The latency programmed in this register is for the shorter-latency sub C-states used by an MWAIT hint to a
C6 or C7 state.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
9:0 Interrupt Response Time Limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C6 or C7 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. See Table 2-20 for supported time unit encodings.
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by
the processor for package C-sate management.
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-263
MODEL-SPECIFIC REGISTERS (MSRS)
63:16 Reserved.
Register Address: 60CH, 1548 MSR_PKGC_IRTL2
Package C6/C7 Interrupt Response Limit 2 (R/W)
This MSR defines the interrupt response time limit used by the processor to manage a transition to a package C6 or
C7 state. The latency programmed in this register is for the longer-latency sub C-states used by an MWAIT hint to a C6
or C7 state.
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
9:0 Interrupt response time limit (R/W)
Specifies the limit that should be used to decide if the package should be
put into a package C6 or C7 state.
12:10 Time Unit (R/W)
Specifies the encoding value of time unit of the interrupt response time
limit. See Table 2-20 for supported time unit encodings.
14:13 Reserved.
15 Valid (R/W)
Indicates whether the values in bits 12:0 are valid and can be used by
the processor for package C-sate management.
63:16 Reserved.
Register Address: 613H, 1555 MSR_PKG_PERF_STATUS
PKG Perf Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 648H, 1608 MSR_CONFIG_TDP_NOMINAL
Base TDP Ratio (R/O) Package
7:0 Config_TDP_Base
Base TDP level ratio to be used for this specific processor (in units of 100
MHz).
63:8 Reserved.
Register Address: 649H, 1609 MSR_CONFIG_TDP_LEVEL1
ConfigTDP Level 1 Ratio and Power Level (R/O) Package
14:0 PKG_TDP_LVL1
Power setting for ConfigTDP Level 1.
15 Reserved.
23:16 Config_TDP_LVL1_Ratio
ConfigTDP level 1 ratio to be used for this specific processor.
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-264 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
31:24 Reserved.
46:32 PKG_MAX_PWR_LVL1
Max Power setting allowed for ConfigTDP Level 1.
62:47 PKG_MIN_PWR_LVL1
MIN Power setting allowed for ConfigTDP Level 1.
63 Reserved.
Register Address: 64AH, 1610 MSR_CONFIG_TDP_LEVEL2
ConfigTDP Level 2 Ratio and Power Level (R/O) Package
14:0 PKG_TDP_LVL2
Power setting for ConfigTDP Level 2.
15 Reserved.
23:16 Config_TDP_LVL2_Ratio
ConfigTDP level 2 ratio to be used for this specific processor.
31:24 Reserved.
46:32 PKG_MAX_PWR_LVL2
Max Power setting allowed for ConfigTDP Level 2.
62:47 PKG_MIN_PWR_LVL2
MIN Power setting allowed for ConfigTDP Level 2.
63 Reserved.
Register Address: 64BH, 1611 MSR_CONFIG_TDP_CONTROL
ConfigTDP Control (R/W) Package
1:0 TDP_LEVEL (RW/L)
System BIOS can program this field.
30:2 Reserved.
31 Config_TDP_Lock (RW/L)
When this bit is set, the content of this register is locked until a reset.
63:32 Reserved.
Register Address: 64CH, 1612 MSR_TURBO_ACTIVATION_RATIO
ConfigTDP Control (R/W) Package
7:0 MAX_NON_TURBO_RATIO (RW/L)
System BIOS can program this field.
30:8 Reserved.
31 TURBO_ACTIVATION_RATIO_Lock (RW/L)
When this bit is set, the content of this register is locked until a reset.
63:32 Reserved.
Register Address: C80H, 3200 IA32_DEBUG_INTERFACE
Silicon Debug Feature Control (R/W)
See Table 2-2.
Package
Table 2-29. Additional MSRs Supported by Processors Based on the Haswell and Haswell-E Microarchitectures
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-265
MODEL-SPECIFIC REGISTERS (MSRS)
2.13.1 MSRs in the 4th Generation Intel® Core™ Processor Family Based on Haswell
Microarchitecture
Table 2-30 lists model-specific registers (MSRs) that are specific to the 4th generation Intel
®
Core™ processor
family and the Intel
®
Xeon
®
processor E3-1200 v3 product family (based on Haswell microarchitecture). These
processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3CH, 06_45H, or 06_46H; see Table
2-1.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
Core
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package. The default is set
as factory-configured package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
Package C states C7 are not available to processors with a
CPUID Signature DisplayFamily_DisplayModel value of 06_3CH.
9:4 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved
15 CFG Lock (R/WO)
24:16 Reserved.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
63:29 Reserved.
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in SMM.
Thread
57:0 Reserved.
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access restriction is
supported and the MSR_SMM_FEATURE_CONTROL is
supported.
2-266 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is
supported and the MSR_SMM_DELAYED is supported.
63:60 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
63:32 Reserved.
Register Address: 391H, 913 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Core 0 select.
1 Core 1 select.
2 Core 2 select.
3 Core 3 select.
18:4 Reserved.
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved.
Register Address: 392H, 914 MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status Package
0 Fixed counter overflowed.
1An ARB counter overflowed.
2 Reserved.
3 A CBox counter overflowed (on any slice).
63:4 Reserved.
Register Address: 394H, 916 MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W) Package
19:0 Reserved.
20 Enable overflow propagation.
21 Reserved.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-267
MODEL-SPECIFIC REGISTERS (MSRS)
22 Enable counting.
63:23 Reserved.
Register Address: 395H, 917 MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter Package
47:0 Current count.
63:48 Reserved.
Register Address: 396H, 918 MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O) Package
3:0 Encoded number of C-Box, derive value by “-1“.
63:4 Reserved.
Register Address: 3B0H, 946 MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0 Package
Register Address: 3B1H, 947 MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1 Package
Register Address: 3B2H, 944 MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR Package
Register Address: 3B3H, 945 MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb Unit, Counter 1 Event Select MSR Package
Register Address: 391H, 913 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Core 0 select.
1 Core 1 select.
2 Core 2 select.
3 Core 3 select.
18:4 Reserved.
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved.
Register Address: 395H, 917 MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter Package
47:0 Current count.
63:48 Reserved.
Register Address: 3B3H, 945 MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb Unit, Counter 1 Event Select MSR Package
Register Address: 4E0H, 1248 MSR_SMM_FEATURE_CONTROL
Enhanced SMM Feature Control (SMM-RW)
Reports SMM capability Enhancement. Accessible only while in SMM.
Package
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-268 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
0Lock (SMM-RWO)
When set to ‘1’ locks this register from further changes.
1 Reserved.
2 SMM_Code_Chk_En (SMM-RW)
This control bit is available only if MSR_SMM_MCA_CAP[58] ==
1. When set to ‘0’ (default) none of the logical processors are
prevented from executing SMM code outside the ranges defined
by the SMRR.
When set to ‘1’ any logical processor in the package that
attempts to execute SMM code not within the ranges defined
by the SMRR will assert an unrecoverable MCE.
63:3 Reserved.
Register Address: 4E2H, 1250 MSR_SMM_DELAYED
SMM Delayed (SMM-RO)
Reports the interruptible state of all logical processors in the package. Available only while in SMM and
MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
Package
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a logical processor of its state in a long flow
of internal operation which delays servicing an interrupt. The
corresponding bit will be set at the start of long events such as:
Microcode Update Load, C6, WBINVD, Ratio Change, Throttle.
The bit is automatically cleared at the end of each long event.
The reset value of this field is 0.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N Reserved.
Register Address: 4E3H, 1251 MSR_SMM_BLOCKED
SMM Blocked (SMM-RO)
Reports the blocked state of all logical processors in the package. Available only while in SMM.
Package
N-1:0 LOG_PROC_STATE (SMM-RO)
Each bit represents a logical processor of its blocked state to
service an SMI. The corresponding bit will be set if the logical
processor is in one of the following states: Wait For SIPI or
SENTER Sleep.
The reset value of this field is 0FFFH.
Only bit positions below N = CPUID.(EAX=0BH,
ECX=PKG_LVL):EBX[15:0] can be updated.
63:N Reserved.
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O) Package
3:0 Power Units
See Section 15.10.1, “RAPL Interfaces.”
Package
7:4 Reserved. Package
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-269
MODEL-SPECIFIC REGISTERS (MSRS)
12:8 Energy Status Units
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits
12:8. Default value is 0EH (or 61 micro-joules).
Package
15:13 Reserved. Package
19:16 Time Units
See Section 15.10.1, “RAPL Interfaces.”
Package
63:20 Reserved.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 640H, 1600 MSR_PP1_POWER_LIMIT
PP1 RAPL Power Limit Control (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 641H, 1601 MSR_PP1_ENERGY_STATUS
PP1 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 642H, 1602 MSR_PP1_POLICY
PP1 Balance Policy (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 690H, 1680 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
Package
0 PROCHOT Status (R0)
When set, processor core frequency is reduced below the
operating system request due to assertion of external
PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2 Reserved.
4 Graphics Driver Status (R0)
When set, frequency is reduced below the operating system
request due to Processor Graphics driver override.
5 Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is
low.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7 Reserved.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-270 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g.,
maximum electrical current consumption).
9 Core Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to domain-level power limiting.
10 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
12 Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system
request due to multi-core turbo limits.
13 Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system
request due to Turbo transition attenuation. This prevents
performance degradation due to frequent operating ratio
changes.
15:14 Reserved.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18 Reserved.
20 Graphics Driver Log
When set, indicates that the Graphics Driver Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-271
MODEL-SPECIFIC REGISTERS (MSRS)
23 Reserved.
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30 Reserved.
Register Address: 6B0H, 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Processor Graphics (R/W)
(Frequency refers to processor graphics frequency.)
Package
0 PROCHOT Status (R0)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
3:2 Reserved.
4 Graphics Driver Status (R0)
When set, frequency is reduced below the operating system
request due to Processor Graphics driver override.
5 Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system
request because the processor has detected that utilization is
low.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-272 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7 Reserved.
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g.,
maximum electrical current consumption).
9 Graphics Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to domain-level power limiting.
10 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
15:12 Reserved.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18 Reserved.
20 Graphics Driver Log
When set, indicates that the Graphics Driver Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 Reserved.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-273
MODEL-SPECIFIC REGISTERS (MSRS)
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30 Reserved.
Register Address: 6B1H, 1713 MSR_RING_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Ring Interconnect (R/W)
(Frequency refers to ring interconnect in the uncore.)
Package
0 PROCHOT Status (R0)
When set, frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal event.
5:2 Reserved.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system
request due to a thermal alert from the Voltage Regulator.
7 Reserved.
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system
request due to electrical design point constraints (e.g.,
maximum electrical current consumption).
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-274 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
9 Reserved.
10 Package-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL1.
11 Package-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system
request due to package-level power limiting PL2.
15:12 Reserved.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18 Reserved.
20 Graphics Driver Log
When set, indicates that the Graphics Driver Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the Autonomous Utilization-Based
Frequency Control Status bit has asserted since the log bit was
last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 Reserved.
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Core Power Limiting Log
When set, indicates that the Core Power Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
26 Package-Level PL1 Power Limiting Log
When set, indicates that the Package Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-275
MODEL-SPECIFIC REGISTERS (MSRS)
27 Package-Level PL2 Power Limiting Log
When set, indicates that the Package Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30 Reserved.
Register Address: 700H, 1792 MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR Package
Register Address: 701H, 1793 MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR Package
Register Address: 706H, 1798 MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0 Package
Register Address: 707H, 1799 MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1 Package
Register Address: 710H, 1808 MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR Package
Register Address: 711H, 1809 MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR Package
Register Address: 716H, 1814 MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0 Package
Register Address: 717H, 1815 MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1 Package
Register Address: 720H, 1824 MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR Package
Register Address: 721H, 1824 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR Package
Register Address: 726H, 1830 MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0 Package
Register Address: 727H, 1831 MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1 Package
Register Address: 730H, 1840 MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR Package
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-276 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.13.2 Additional Residency MSRs Supported in 4th Generation Intel® Core™ Processors
The 4th generation Intel
®
Core™ processor family (based on Haswell microarchitecture) with a CPUID Signature
DisplayFamily_DisplayModel value of 06_45H supports the MSR interfaces listed in Table 2-20, Table 2-21, Table
2-29, Table 2-30, and Table 2-31.
Register Address: 731H, 1841 MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR Package
Register Address: 736H, 1846 MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0 Package
Register Address: 737H, 1847 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 Package
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, and Table 2-29 for other MSR definitions applicable to processors with a CPUID
Signature DisplayFamily_DisplayModel value of 063CH or 06_46H.
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a
CPUID Signature DisplayFamily_DisplayModel Value of 06_45H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
Core
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved.
15 CFG Lock (R/WO)
24:16 Reserved.
Table 2-30. MSRs Supported by 4th Generation Intel® Core™ Processors (Haswell Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-277
MODEL-SPECIFIC REGISTERS (MSRS)
2.14 MSRS IN THE INTEL® XEON® PROCESSOR E5 V3 AND E7 V3 PRODUCT
FAMILY
The Intel
®
Xeon
®
processor E5 v3 family and the Intel
®
Xeon
®
processor E7 v3 family are based on Haswell-E
microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of 06_3F). These processors support the
MSR interfaces listed in Table 2-20, Table 2-29, and Table 2-32.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
63:29 Reserved.
Register Address: 630H, 1584 MSR_PKG_C8_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
59:0 Package C8 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C8 states.
Count at the same frequency as the TSC.
63:60 Reserved.
Register Address: 631H, 1585 MSR_PKG_C9_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
59:0 Package C9 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C9 states.
Count at the same frequency as the TSC.
63:60 Reserved.
Register Address: 632H, 1586 MSR_PKG_C10_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Package
59:0 Package C10 Residency Counter (R/O)
Value since last reset that this package is in processor-specific C10 states.
Count at the same frequency as the TSC.
63:60 Reserved.
See Table 2-20, Table 2-21, Table 2-22, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID
Signature DisplayFamily_DisplayModel value of 06_45H.
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 35H, 53 MSR_CORE_THREAD_COUNT
Table 2-31. Additional Residency MSRs Supported by 4th Generation Intel® Core™ Processors with a
CPUID Signature DisplayFamily_DisplayModel Value of 06_45H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-278 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Configured State of Enabled Processor Core Count and Logical Processor Count (R/O)
• After a Power-On RESET, enumerates factory configuration of the number of processor cores and logical
processors in the physical package.
• Following the sequence of (i) BIOS modified a Configuration Mask which selects a subset of processor cores to be
active post RESET and (ii) a RESET event after the modification, enumerates the current configuration of enabled
processor core count and logical processor count in the physical package.
Package
15:0 THREAD_COUNT (R/O)
The number of logical processors that are currently enabled (by either
factory configuration or BIOS configuration) in the physical package.
31:16 Core_COUNT (R/O)
The number of processor cores that are currently enabled (by either factory
configuration or BIOS configuration) in the physical package.
63:32 Reserved.
Register Address: 53H, 83 MSR_THREAD_ID_INFO
A Hardware Assigned ID for the Logical Processor (R/O) Thread
7:0 Logical_Processor_ID (R/O)
An implementation-specific numerical value physically assigned to each
logical processor. This ID is not related to Initial APIC ID or x2APIC ID, it is
unique within a physical package.
63:8 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states.
See http://biosbits.org.
Core
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor are
available.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved.
15 CFG Lock (R/WO)
24:16 Reserved.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-279
MODEL-SPECIFIC REGISTERS (MSRS)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State Undemotion Enable (R/W)
63:31 Reserved.
Register Address: 179H, 377 IA32_MCG_CAP
Global Machine Check Capability (R/O) Thread
7:0 Count
8 MCG_CTL_P
9 MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved.
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 MCG_EM_P
26 MCG_ELOG_P
63:27 Reserved.
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in SMM.
Thread
57:0 Reserved.
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access restriction is supported and a
host-space interface available to SMM handler.
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is supported and a
host-space interface available to SMM handler.
63:60 Reserved.
Register Address: 17FH, 383 MSR_ERROR_CONTROL
MC Bank Error Configuration (R/W) Package
0 Reserved.
1 MemError Log Enable (R/W)
When set, enables IMC status bank to log additional info in bits 36:32.
63:2 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-280 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
39:32 Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5 core active.
Package
47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6 core active.
Package
55:48 Maximum Ratio Limit for 7C
Maximum turbo ratio limit of 7 core active.
Package
63:56 Maximum Ratio Limit for 8C
Maximum turbo ratio limit of 8 core active.
Package
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 9C
Maximum turbo ratio limit of 9 core active.
Package
15:8 Maximum Ratio Limit for 10C
Maximum turbo ratio limit of 10 core active.
Package
23:16 Maximum Ratio Limit for 11C
Maximum turbo ratio limit of 11 core active.
Package
31:24 Maximum Ratio Limit for 12C
Maximum turbo ratio limit of 12 core active.
Package
39:32 Maximum Ratio Limit for 13C
Maximum turbo ratio limit of 13 core active.
Package
47:40 Maximum Ratio Limit for 14C
Maximum turbo ratio limit of 14 core active.
Package
55:48 Maximum Ratio Limit for 15C
Maximum turbo ratio limit of 15 core active.
Package
63:56 Maximum Ratio Limit for16C
Maximum turbo ratio limit of 16 core active.
Package
Register Address: 1AFH, 431 MSR_TURBO_RATIO_LIMIT2
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 17C
Maximum turbo ratio limit of 17 core active.
Package
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-281
MODEL-SPECIFIC REGISTERS (MSRS)
15:8 Maximum Ratio Limit for 18C
Maximum turbo ratio limit of 18 core active.
Package
62:16 Reserved. Package
63 Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration
1
specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1, and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
Package
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 417H, 1047 IA32_MC5_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-282 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 420H, 1056 IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 421H, 1057 IA32_MC8_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 422H, 1058 IA32_MC8_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 423H, 1059 IA32_MC8_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 425H, 1061 IA32_MC9_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 426H, 1062 IA32_MC9_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42BH, 1067 IA32_MC10_MISC
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-283
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42CH, 1068 IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42DH, 1069 IA32_MC11_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42EH, 1070 IA32_MC11_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42FH, 1071 IA32_MC11_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 430H, 1072 IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 431H, 1073 IA32_MC12_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 432H, 1074 IA32_MC12_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 433H, 1075 IA32_MC12_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 434H, 1076 IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 435H, 1077 IA32_MC13_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 436H, 1078 IA32_MC13_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 437H, 1079 IA32_MC13_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 438H, 1080 IA32_MC14_CTL
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-284 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 439H, 1081 IA32_MC14_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43AH, 1082 IA32_MC14_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43BH, 1083 IA32_MC14_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43CH, 1084 IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43DH, 1085 IA32_MC15_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43EH, 1086 IA32_MC15_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43FH, 1087 IA32_MC15_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 440H, 1088 IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 441H, 1089 IA32_MC16_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 442H, 1090 IA32_MC16_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 443H, 1091 IA32_MC16_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-285
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 445H, 1093 IA32_MC17_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 449H, 1097 IA32_MC18_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44FH, 1103 IA32_MC19_MISC
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-286 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 450H, 1104 IA32_MC20_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 451H, 1105 IA32_MC20_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 452H, 1106 IA32_MC20_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 453H, 1107 IA32_MC20_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 454H, 1108 IA32_MC21_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 455H, 1109 IA32_MC21_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 456H, 1110 IA32_MC21_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 457H, 1111 IA32_MC21_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O) Package
3:0 Power Units
See Section 15.10.1, “RAPL Interfaces.”
Package
7:4 Reserved. Package
12:8 Energy Status Units
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value is
0EH (or 61 micro-joules).
Package
15:13 Reserved. Package
19:16 Time Units
See Section 15.10.1, “RAPL Interfaces.”
Package
63:20 Reserved.
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-287
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Energy Consumed by DRAM devices.
Package
31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32 Reserved.
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61EH, 1566 MSR_PCIE_PLL_RATIO
Configuration of PCIE PLL Relative to BCLK(R/W) Package
1:0 PCIE Ratio (R/W)
00b: Use 5:5 mapping for100MHz operation (default).
01b: Use 5:4 mapping for125MHz operation.
10b: Use 5:3 mapping for166MHz operation.
11b: Use 5:2 mapping for250MHz operation.
Package
2LPLL Select (R/W)
If 1, use configured setting of PCIE Ratio.
Package
3LONG RESET (R/W)
If 1, wait an additional time-out before re-locking Gen2/Gen3 PLLs.
Package
63:4 Reserved.
Register Address: 620H, 1568 MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum frequency that hardware will select.
Package
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
7 Reserved.
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
63:15 Reserved.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Reads return 0.
Package
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-288 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 690H, 1680 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
Package
0PROCHOT Status (R0)
When set, processor core frequency is reduced below the operating system
request due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system request due to
a thermal event.
2 Power Budget Management Status (R0)
When set, frequency is reduced below the operating system request due to
PBM limit
3 Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system request due to
PCS limit
4 Reserved.
5 Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system request
because the processor has detected that utilization is low.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due to
a thermal alert from the Voltage Regulator.
7 Reserved.
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system request due to
electrical design point constraints (e.g., maximum electrical current
consumption).
9 Reserved.
10 Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system request due to
Multi-Core Turbo limits.
12:11 Reserved.
13 Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1.
14 Core Max N-Core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency.
15 Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system request.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-289
MODEL-SPECIFIC REGISTERS (MSRS)
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18 Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
19 Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
20 Reserved.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 Reserved.
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Reserved.
26 Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27 Reserved.
29 Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30 Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-290 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.14.1 Additional Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
The Intel Xeon Processor E5 v3 and E7 v3 families are based on Haswell-E microarchitecture. The MSR-based
uncore PMU interfaces are listed in Table 2-33. For complete details of the uncore PMU, refer to the Intel Xeon
Processor E5 v3 Product Family Uncore Performance Monitoring Guide. These processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_3FH.
31 Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32 Reserved.
Register Address: C8DH, 3213 IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
Thread
7:0 EventID (R/W)
Event encoding:
0x0: No monitoring.
0x1: L3 occupancy monitoring.
All other encoding reserved.
31:8 Reserved.
41:32 RMID (R/W)
63:42 Reserved.
Register Address: C8EH, 3214 IA32_QM_CTR
Monitoring Counter Register (R/O)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
Thread
61:0 Resource Monitored Data
62 Unavailable: If 1, indicates data for this RMID is not available or not
monitored for this resource or RMID.
63 Error: If 1, indicates an unsupported RMID or event type was written to
IA32_PQR_QM_EVTSEL.
Register Address: C8FH, 3215 IA32_PQR_ASSOC
Resource Association Register (R/W) Thread
9:0 RMID
63: 10 Reserved.
See Table 2-20 and Table 2-29 for other MSR definitions applicable to processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_3FH.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the fac-
tory-set configuration is dependent on features specific to the processor and the platform.
Table 2-32. Additional MSRs Supported by the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-291
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 700H, 1792 MSR_PMON_GLOBAL_CTL
Uncore Perfmon Per-Socket Global Control Package
Register Address: 701H, 1793 MSR_PMON_GLOBAL_STATUS
Uncore Perfmon Per-Socket Global Status Package
Register Address: 702H, 1794 MSR_PMON_GLOBAL_CONFIG
Uncore Perfmon Per-Socket Global Configuration Package
Register Address: 703H, 1795 MSR_U_PMON_UCLK_FIXED_CTL
Uncore U-Box UCLK Fixed Counter Control Package
Register Address: 704H, 1796 MSR_U_PMON_UCLK_FIXED_CTR
Uncore U-Box UCLK Fixed Counter Package
Register Address: 705H, 1797 MSR_U_PMON_EVNTSEL0
Uncore U-Box Perfmon Event Select for U-Box Counter 0 Package
Register Address: 706H, 1798 MSR_U_PMON_EVNTSEL1
Uncore U-Box Perfmon Event Select for U-Box Counter 1 Package
Register Address: 708H, 1800 MSR_U_PMON_BOX_STATUS
Uncore U-Box Perfmon U-Box Wide Status Package
Register Address: 709H, 1801 MSR_U_PMON_CTR0
Uncore U-Box Perfmon Counter 0 Package
Register Address: 70AH, 1802 MSR_U_PMON_CTR1
Uncore U-Box Perfmon Counter 1 Package
Register Address: 710H, 1808 MSR_PCU_PMON_BOX_CTL
Uncore PCU Perfmon for PCU-Box-Wide Control Package
Register Address: 711H, 1809 MSR_PCU_PMON_EVNTSEL0
Uncore PCU Perfmon Event Select for PCU Counter 0 Package
Register Address: 712H, 1810 MSR_PCU_PMON_EVNTSEL1
Uncore PCU Perfmon Event Select for PCU Counter 1 Package
Register Address: 713H, 1811 MSR_PCU_PMON_EVNTSEL2
Uncore PCU Perfmon Event Select for PCU Counter 2 Package
Register Address: 714H, 1812 MSR_PCU_PMON_EVNTSEL3
Uncore PCU Perfmon Event Select for PCU Counter 3 Package
Register Address: 715H, 1813 MSR_PCU_PMON_BOX_FILTER
Uncore PCU Perfmon Box-Wide Filter Package
Register Address: 716H, 1814 MSR_PCU_PMON_BOX_STATUS
Uncore PCU Perfmon Box Wide Status Package
Register Address: 717H, 1815 MSR_PCU_PMON_CTR0
Uncore PCU Perfmon Counter 0 Package
Register Address: 718H, 1816 MSR_PCU_PMON_CTR1
2-292 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore PCU Perfmon Counter 1 Package
Register Address: 719H, 1817 MSR_PCU_PMON_CTR2
Uncore PCU Perfmon Counter 2 Package
Register Address: 71AH, 1818 MSR_PCU_PMON_CTR3
Uncore PCU Perfmon Counter 3 Package
Register Address: 720H, 1824 MSR_S0_PMON_BOX_CTL
Uncore SBo 0 Perfmon for SBo 0 Box-Wide Control Package
Register Address: 721H, 1825 MSR_S0_PMON_EVNTSEL0
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 0 Package
Register Address: 722H, 1826 MSR_S0_PMON_EVNTSEL1
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 1 Package
Register Address: 723H, 1827 MSR_S0_PMON_EVNTSEL2
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 2 Package
Register Address: 724H, 1828 MSR_S0_PMON_EVNTSEL3
Uncore SBo 0 Perfmon Event Select for SBo 0 Counter 3 Package
Register Address: 725H, 1829 MSR_S0_PMON_BOX_FILTER
Uncore SBo 0 Perfmon Box-Wide Filter Package
Register Address: 726H, 1830 MSR_S0_PMON_CTR0
Uncore SBo 0 Perfmon Counter 0 Package
Register Address: 727H, 1831 MSR_S0_PMON_CTR1
Uncore SBo 0 Perfmon Counter 1 Package
Register Address: 728H, 1832 MSR_S0_PMON_CTR2
Uncore SBo 0 Perfmon Counter 2 Package
Register Address: 729H, 1833 MSR_S0_PMON_CTR3
Uncore SBo 0 Perfmon Counter 3 Package
Register Address: 72AH, 1834 MSR_S1_PMON_BOX_CTL
Uncore SBo 1 Perfmon for SBo 1 Box-Wide Control Package
Register Address: 72BH, 1835 MSR_S1_PMON_EVNTSEL0
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 0 Package
Register Address: 72CH, 1836 MSR_S1_PMON_EVNTSEL1
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 1 Package
Register Address: 72DH, 1837 MSR_S1_PMON_EVNTSEL2
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 2 Package
Register Address: 72EH, 1838 MSR_S1_PMON_EVNTSEL3
Uncore SBo 1 Perfmon Event Select for SBo 1 Counter 3 Package
Register Address: 72FH, 1839 MSR_S1_PMON_BOX_FILTER
Uncore SBo 1 Perfmon Box-Wide Filter Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-293
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 730H, 1840 MSR_S1_PMON_CTR0
Uncore SBo 1 Perfmon Counter 0 Package
Register Address: 731H, 1841 MSR_S1_PMON_CTR1
Uncore SBo 1 Perfmon Counter 1 Package
Register Address: 732H, 1842 MSR_S1_PMON_CTR2
Uncore SBo 1 Perfmon Counter 2 Package
Register Address: 733H, 1843 MSR_S1_PMON_CTR3
Uncore SBo 1 Perfmon Counter 3 Package
Register Address: 734H, 1844 MSR_S2_PMON_BOX_CTL
Uncore SBo 2 Perfmon for SBo 2 Box-Wide Control Package
Register Address: 735H, 1845 MSR_S2_PMON_EVNTSEL0
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 0 Package
Register Address: 736H, 1846 MSR_S2_PMON_EVNTSEL1
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 1 Package
Register Address: 737H, 1847 MSR_S2_PMON_EVNTSEL2
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 2 Package
Register Address: 738H, 1848 MSR_S2_PMON_EVNTSEL3
Uncore SBo 2 Perfmon Event Select for SBo 2 Counter 3 Package
Register Address: 739H, 1849 MSR_S2_PMON_BOX_FILTER
Uncore SBo 2 Perfmon Box-Wide Filter Package
Register Address: 73AH, 1850 MSR_S2_PMON_CTR0
Uncore SBo 2 Perfmon Counter 0 Package
Register Address: 73BH, 1851 MSR_S2_PMON_CTR1
Uncore SBo 2 Perfmon Counter 1 Package
Register Address: 73CH, 1852 MSR_S2_PMON_CTR2
Uncore SBo 2 Perfmon Counter 2 Package
Register Address: 73DH, 1853 MSR_S2_PMON_CTR3
Uncore SBo 2 Perfmon Counter 3 Package
Register Address: 73EH, 1854 MSR_S3_PMON_BOX_CTL
Uncore SBo 3 Perfmon for SBo 3 Box-Wide Control Package
Register Address: 73FH, 1855 MSR_S3_PMON_EVNTSEL0
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 0 Package
Register Address: 740H, 1856 MSR_S3_PMON_EVNTSEL1
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 1 Package
Register Address: 741H, 1857 MSR_S3_PMON_EVNTSEL2
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 2 Package
Register Address: 742H, 1858 MSR_S3_PMON_EVNTSEL3
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-294 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore SBo 3 Perfmon Event Select for SBo 3 Counter 3 Package
Register Address: 743H, 1859 MSR_S3_PMON_BOX_FILTER
Uncore SBo 3 Perfmon Box-Wide Filter Package
Register Address: 744H, 1860 MSR_S3_PMON_CTR0
Uncore SBo 3 Perfmon Counter 0 Package
Register Address: 745H, 1861 MSR_S3_PMON_CTR1
Uncore SBo 3 Perfmon Counter 1 Package
Register Address: 746H, 1862 MSR_S3_PMON_CTR2
Uncore SBo 3 Perfmon Counter 2 Package
Register Address: 747H, 1863 MSR_S3_PMON_CTR3
Uncore SBo 3 Perfmon Counter 3 Package
Register Address: E00H, 3584 MSR_C0_PMON_BOX_CTL
Uncore C-Box 0 Perfmon for Box-Wide Control Package
Register Address: E01H, 3585 MSR_C0_PMON_EVNTSEL0
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 0 Package
Register Address: E02H, 3586 MSR_C0_PMON_EVNTSEL1
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 1 Package
Register Address: E03H, 3587 MSR_C0_PMON_EVNTSEL2
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 2 Package
Register Address: E04H, 3588 MSR_C0_PMON_EVNTSEL3
Uncore C-Box 0 Perfmon Event Select for C-Box 0 Counter 3 Package
Register Address: E05H, 3589 MSR_C0_PMON_BOX_FILTER0
Uncore C-Box 0 Perfmon Box Wide Filter 0 Package
Register Address: E06H, 3590 MSR_C0_PMON_BOX_FILTER1
Uncore C-Box 0 Perfmon Box Wide Filter 1 Package
Register Address: E07H, 3591 MSR_C0_PMON_BOX_STATUS
Uncore C-Box 0 Perfmon Box Wide Status Package
Register Address: E08H, 3592 MSR_C0_PMON_CTR0
Uncore C-Box 0 Perfmon Counter 0 Package
Register Address: E09H, 3593 MSR_C0_PMON_CTR1
Uncore C-Box 0 Perfmon Counter 1 Package
Register Address: E0AH, 3594 MSR_C0_PMON_CTR2
Uncore C-Box 0 Perfmon Counter 2 Package
Register Address: E0BH, 3595 MSR_C0_PMON_CTR3
Uncore C-Box 0 Perfmon Counter 3 Package
Register Address: E10H, 3600 MSR_C1_PMON_BOX_CTL
Uncore C-Box 1 Perfmon for Box-Wide Control Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-295
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E11H, 3601 MSR_C1_PMON_EVNTSEL0
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 0 Package
Register Address: E12H, 3602 MSR_C1_PMON_EVNTSEL1
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 1 Package
Register Address: E13H, 3603 MSR_C1_PMON_EVNTSEL2
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 2 Package
Register Address: E14H, 3604 MSR_C1_PMON_EVNTSEL3
Uncore C-Box 1 Perfmon Event Select for C-Box 1 Counter 3 Package
Register Address: E15H, 3605 MSR_C1_PMON_BOX_FILTER0
Uncore C-Box 1 Perfmon Box Wide Filter 0 Package
Register Address: E16H, 3606 MSR_C1_PMON_BOX_FILTER1
Uncore C-Box 1 Perfmon Box Wide Filter1 Package
Register Address: E17H, 3607 MSR_C1_PMON_BOX_STATUS
Uncore C-Box 1 Perfmon Box Wide Status Package
Register Address: E18H, 3608 MSR_C1_PMON_CTR0
Uncore C-Box 1 Perfmon Counter 0 Package
Register Address: E19H, 3609 MSR_C1_PMON_CTR1
Uncore C-Box 1 Perfmon Counter 1 Package
Register Address: E1AH, 3610 MSR_C1_PMON_CTR2
Uncore C-Box 1 Perfmon Counter 2 Package
Register Address: E1BH, 3611 MSR_C1_PMON_CTR3
Uncore C-Box 1 Perfmon Counter 3 Package
Register Address: E20H, 3616 MSR_C2_PMON_BOX_CTL
Uncore C-Box 2 Perfmon for Box-Wide Control Package
Register Address: E21H, 3617 MSR_C2_PMON_EVNTSEL0
Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 0 Package
Register Address: E22H, 3618 MSR_C2_PMON_EVNTSEL1
Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 1 Package
Register Address: E23H, 3619 MSR_C2_PMON_EVNTSEL2
Uncore C-Box 2 Perfmon Event Select for C-Box 2 Counter 2 Package
Register Address: E24H, 3620 MSR_C2_PMON_EVNTSEL3
Uncore C-Box 2 Perfmon Event select for C-Box 2 Counter 3 Package
Register Address: E25H, 3621 MSR_C2_PMON_BOX_FILTER0
Uncore C-Box 2 Perfmon Box Wide Filter 0 Package
Register Address: E26H, 3622 MSR_C2_PMON_BOX_FILTER1
Uncore C-Box 2 Perfmon Box Wide Filter1 Package
Register Address: E27H, 3623 MSR_C2_PMON_BOX_STATUS
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-296 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 2 Perfmon Box Wide Status Package
Register Address: E28H, 3624 MSR_C2_PMON_CTR0
Uncore C-Box 2 Perfmon Counter 0 Package
Register Address: E29H, 3625 MSR_C2_PMON_CTR1
Uncore C-Box 2 Perfmon Counter 1 Package
Register Address: E2AH, 3626 MSR_C2_PMON_CTR2
Uncore C-Box 2 Perfmon Counter 2 Package
Register Address: E2BH, 3627 MSR_C2_PMON_CTR3
Uncore C-Box 2 Perfmon Counter 3 Package
Register Address: E30H, 3632 MSR_C3_PMON_BOX_CTL
Uncore C-Box 3 Perfmon for Box-Wide Control Package
Register Address: E31H, 3633 MSR_C3_PMON_EVNTSEL0
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 0 Package
Register Address: E32H, 3634 MSR_C3_PMON_EVNTSEL1
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 1 Package
Register Address: E33H, 3635 MSR_C3_PMON_EVNTSEL2
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 2 Package
Register Address: E34H, 3636 MSR_C3_PMON_EVNTSEL3
Uncore C-Box 3 Perfmon Event Select for C-Box 3 Counter 3 Package
Register Address: E35H, 3637 MSR_C3_PMON_BOX_FILTER0
Uncore C-Box 3 Perfmon Box Wide Filter 0 Package
Register Address: E36H, 3638 MSR_C3_PMON_BOX_FILTER1
Uncore C-Box 3 Perfmon Box Wide Filter1 Package
Register Address: E37H, 3639 MSR_C3_PMON_BOX_STATUS
Uncore C-Box 3 Perfmon Box Wide Status Package
Register Address: E38H, 3640 MSR_C3_PMON_CTR0
Uncore C-Box 3 Perfmon Counter 0 Package
Register Address: E39H, 3641 MSR_C3_PMON_CTR1
Uncore C-Box 3 Perfmon Counter 1 Package
Register Address: E3AH, 3642 MSR_C3_PMON_CTR2
Uncore C-Box 3 Perfmon Counter 2 Package
Register Address: E3BH, 3643 MSR_C3_PMON_CTR3
Uncore C-Box 3 Perfmon Counter 3 Package
Register Address: E40H, 3648 MSR_C4_PMON_BOX_CTL
Uncore C-Box 4 Perfmon for Box-Wide Control Package
Register Address: E41H, 3649 MSR_C4_PMON_EVNTSEL0
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 0 Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-297
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E42H, 3650 MSR_C4_PMON_EVNTSEL1
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 1 Package
Register Address: E43H, 3651 MSR_C4_PMON_EVNTSEL2
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 2 Package
Register Address: E44H, 3652 MSR_C4_PMON_EVNTSEL3
Uncore C-Box 4 Perfmon Event Select for C-Box 4 Counter 3 Package
Register Address: E45H, 3653 MSR_C4_PMON_BOX_FILTER0
Uncore C-Box 4 Perfmon Box Wide Filter 0 Package
Register Address: E46H, 3654 MSR_C4_PMON_BOX_FILTER1
Uncore C-Box 4 Perfmon Box Wide Filter1 Package
Register Address: E47H, 3655 MSR_C4_PMON_BOX_STATUS
Uncore C-Box 4 Perfmon Box Wide Status Package
Register Address: E48H, 3656 MSR_C4_PMON_CTR0
Uncore C-Box 4 Perfmon Counter 0 Package
Register Address: E49H, 3657 MSR_C4_PMON_CTR1
Uncore C-Box 4 Perfmon Counter 1 Package
Register Address: E4AH, 3658 MSR_C4_PMON_CTR2
Uncore C-Box 4 Perfmon Counter 2 Package
Register Address: E4BH, 3659 MSR_C4_PMON_CTR3
Uncore C-Box 4 Perfmon Counter 3 Package
Register Address: E50H, 3664 MSR_C5_PMON_BOX_CTL
Uncore C-Box 5 Perfmon for Box-Wide Control Package
Register Address: E51H, 3665 MSR_C5_PMON_EVNTSEL0
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 0 Package
Register Address: E52H, 3666 MSR_C5_PMON_EVNTSEL1
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 1 Package
Register Address: E53H, 3667 MSR_C5_PMON_EVNTSEL2
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 2 Package
Register Address: E54H, 3668 MSR_C5_PMON_EVNTSEL3
Uncore C-Box 5 Perfmon Event Select for C-Box 5 Counter 3 Package
Register Address: E55H, 3669 MSR_C5_PMON_BOX_FILTER0
Uncore C-Box 5 Perfmon Box Wide Filter 0 Package
Register Address: E56H, 3670 MSR_C5_PMON_BOX_FILTER1
Uncore C-Box 5 Perfmon Box Wide Filter 1 Package
Register Address: E57H, 3671 MSR_C5_PMON_BOX_STATUS
Uncore C-Box 5 Perfmon Box Wide Status Package
Register Address: E58H, 3672 MSR_C5_PMON_CTR0
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-298 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 5 Perfmon Counter 0 Package
Register Address: E59H, 3673 MSR_C5_PMON_CTR1
Uncore C-Box 5 Perfmon Counter 1 Package
Register Address: E5AH, 3674 MSR_C5_PMON_CTR2
Uncore C-Box 5 Perfmon Counter 2 Package
Register Address: E5BH, 3675 MSR_C5_PMON_CTR3
Uncore C-Box 5 Perfmon Counter 3 Package
Register Address: E60H, 3680 MSR_C6_PMON_BOX_CTL
Uncore C-Box 6 Perfmon for Box-Wide Control Package
Register Address: E61H, 3681 MSR_C6_PMON_EVNTSEL0
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 0 Package
Register Address: E62H, 3682 MSR_C6_PMON_EVNTSEL1
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 1 Package
Register Address: E63H, 3683 MSR_C6_PMON_EVNTSEL2
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 2 Package
Register Address: E64H, 3684 MSR_C6_PMON_EVNTSEL3
Uncore C-Box 6 Perfmon Event Select for C-Box 6 Counter 3 Package
Register Address: E65H, 3685 MSR_C6_PMON_BOX_FILTER0
Uncore C-Box 6 Perfmon Box Wide Filter 0 Package
Register Address: E66H, 3686 MSR_C6_PMON_BOX_FILTER1
Uncore C-Box 6 Perfmon Box Wide Filter 1 Package
Register Address: E67H, 3687 MSR_C6_PMON_BOX_STATUS
Uncore C-Box 6 Perfmon Box Wide Status Package
Register Address: E68H, 3688 MSR_C6_PMON_CTR0
Uncore C-Box 6 Perfmon Counter 0 Package
Register Address: E69H, 3689 MSR_C6_PMON_CTR1
Uncore C-Box 6 Perfmon Counter 1 Package
Register Address: E6AH, 3690 MSR_C6_PMON_CTR2
Uncore C-Box 6 Perfmon Counter 2 Package
Register Address: E6BH, 3691 MSR_C6_PMON_CTR3
Uncore C-Box 6 Perfmon Counter 3 Package
Register Address: E70H, 3696 MSR_C7_PMON_BOX_CTL
Uncore C-Box 7 Perfmon for Box-Wide Control Package
Register Address: E71H, 3697 MSR_C7_PMON_EVNTSEL0
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 0 Package
Register Address: E72H, 3698 MSR_C7_PMON_EVNTSEL1
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 1 Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-299
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: E73H, 3699 MSR_C7_PMON_EVNTSEL2
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 2 Package
Register Address: E74H, 3700 MSR_C7_PMON_EVNTSEL3
Uncore C-Box 7 Perfmon Event Select for C-Box 7 Counter 3 Package
Register Address: E75H, 3701 MSR_C7_PMON_BOX_FILTER0
Uncore C-Box 7 Perfmon Box Wide Filter 0 Package
Register Address: E76H, 3702 MSR_C7_PMON_BOX_FILTER1
Uncore C-Box 7 Perfmon Box Wide Filter 1 Package
Register Address: E77H, 3703 MSR_C7_PMON_BOX_STATUS
Uncore C-Box 7 Perfmon Box Wide Status Package
Register Address: E78H, 3704 MSR_C7_PMON_CTR0
Uncore C-Box 7 Perfmon Counter 0 Package
Register Address: E79H, 3705 MSR_C7_PMON_CTR1
Uncore C-Box 7 Perfmon Counter 1 Package
Register Address: E7AH, 3706 MSR_C7_PMON_CTR2
Uncore C-Box 7 Perfmon Counter 2 Package
Register Address: E7BH, 3707 MSR_C7_PMON_CTR3
Uncore C-Box 7 Perfmon Counter 3 Package
Register Address: E80H, 3712 MSR_C8_PMON_BOX_CTL
Uncore C-Box 8 Perfmon Local Box Wide Control Package
Register Address: E81H, 3713 MSR_C8_PMON_EVNTSEL0
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 0 Package
Register Address: E82H, 3714 MSR_C8_PMON_EVNTSEL1
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 1 Package
Register Address: E83H, 3715 MSR_C8_PMON_EVNTSEL2
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 2 Package
Register Address: E84H, 3716 MSR_C8_PMON_EVNTSEL3
Uncore C-Box 8 Perfmon Event Select for C-Box 8 Counter 3 Package
Register Address: E85H, 3717 MSR_C8_PMON_BOX_FILTER0
Uncore C-Box 8 Perfmon Box Wide Filter 0 Package
Register Address: E86H, 3718 MSR_C8_PMON_BOX_FILTER1
Uncore C-Box 8 Perfmon Box Wide Filter 1 Package
Register Address: E87H, 3719 MSR_C8_PMON_BOX_STATUS
Uncore C-Box 8 Perfmon Box Wide Status Package
Register Address: E88H, 3720 MSR_C8_PMON_CTR0
Uncore C-Box 8 Perfmon Counter 0 Package
Register Address: E89H, 3721 MSR_C8_PMON_CTR1
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-300 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 8 Perfmon Counter 1 Package
Register Address: E8AH, 3722 MSR_C8_PMON_CTR2
Uncore C-Box 8 Perfmon Counter 2 Package
Register Address: E8BH, 3723 MSR_C8_PMON_CTR3
Uncore C-Box 8 Perfmon Counter 3 Package
Register Address: E90H, 3728 MSR_C9_PMON_BOX_CTL
Uncore C-Box 9 Perfmon Local Box Wide Control Package
Register Address: E91H, 3729 MSR_C9_PMON_EVNTSEL0
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 0 Package
Register Address: E92H, 3730 MSR_C9_PMON_EVNTSEL1
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 1 Package
Register Address: E93H, 3731 MSR_C9_PMON_EVNTSEL2
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 2 Package
Register Address: E94H, 3732 MSR_C9_PMON_EVNTSEL3
Uncore C-Box 9 Perfmon Event Select for C-Box 9 Counter 3 Package
Register Address: E95H, 3733 MSR_C9_PMON_BOX_FILTER0
Uncore C-Box 9 Perfmon Box Wide Filter 0 Package
Register Address: E96H, 3734 MSR_C9_PMON_BOX_FILTER1
Uncore C-Box 9 Perfmon Box Wide Filter 1 Package
Register Address: E97H, 3735 MSR_C9_PMON_BOX_STATUS
Uncore C-Box 9 Perfmon Box Wide Status Package
Register Address: E98H, 3736 MSR_C9_PMON_CTR0
Uncore C-Box 9 Perfmon Counter 0 Package
Register Address: E99H, 3737 MSR_C9_PMON_CTR1
Uncore C-Box 9 Perfmon Counter 1 Package
Register Address: E9AH, 3738 MSR_C9_PMON_CTR2
Uncore C-Box 9 Perfmon Counter 2 Package
Register Address: E9BH, 3739 MSR_C9_PMON_CTR3
Uncore C-Box 9 Perfmon Counter 3 Package
Register Address: EA0H, 3744 MSR_C10_PMON_BOX_CTL
Uncore C-Box 10 Perfmon Local Box Wide Control Package
Register Address: EA1H, 3745 MSR_C10_PMON_EVNTSEL0
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 0 Package
Register Address: EA2H, 3746 MSR_C10_PMON_EVNTSEL1
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 1 Package
Register Address: EA3H, 3747 MSR_C10_PMON_EVNTSEL2
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 2 Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-301
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: EA4H, 3748 MSR_C10_PMON_EVNTSEL3
Uncore C-Box 10 Perfmon Event Select for C-Box 10 Counter 3 Package
Register Address: EA5H, 3749 MSR_C10_PMON_BOX_FILTER0
Uncore C-Box 10 Perfmon Box Wide Filter 0 Package
Register Address: EA6H, 3750 MSR_C10_PMON_BOX_FILTER1
Uncore C-Box 10 Perfmon Box Wide Filter 1 Package
Register Address: EA7H, 3751 MSR_C10_PMON_BOX_STATUS
Uncore C-Box 10 Perfmon Box Wide Status Package
Register Address: EA8H, 3752 MSR_C10_PMON_CTR0
Uncore C-Box 10 Perfmon Counter 0 Package
Register Address: EA9H, 3753 MSR_C10_PMON_CTR1
Uncore C-Box 10 perfmon Counter 1 Package
Register Address: EAAH, 3754 MSR_C10_PMON_CTR2
Uncore C-Box 10 Perfmon Counter 2 Package
Register Address: EABH, 3755 MSR_C10_PMON_CTR3
Uncore C-Box 10 Perfmon Counter 3 Package
Register Address: EB0H, 3760 MSR_C11_PMON_BOX_CTL
Uncore C-Box 11 Perfmon Local Box Wide Control Package
Register Address: EB1H, 3761 MSR_C11_PMON_EVNTSEL0
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 0 Package
Register Address: EB2H, 3762 MSR_C11_PMON_EVNTSEL1
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 1 Package
Register Address: EB3H, 3763 MSR_C11_PMON_EVNTSEL2
Uncore C-Box 11 Perfmon Event Select for C-Box 11 Counter 2 Package
Register Address: EB4H, 3764 MSR_C11_PMON_EVNTSEL3
Uncore C-box 11 Perfmon Event Select for C-Box 11 Counter 3 Package
Register Address: EB5H, 3765 MSR_C11_PMON_BOX_FILTER0
Uncore C-Box 11 Perfmon Box Wide Filter 0 Package
Register Address: EB6H, 3766 MSR_C11_PMON_BOX_FILTER1
Uncore C-Box 11 Perfmon Box Wide Filter 1 Package
Register Address: EB7H, 3767 MSR_C11_PMON_BOX_STATUS
Uncore C-Box 11 Perfmon Box Wide Status Package
Register Address: EB8H, 3768 MSR_C11_PMON_CTR0
Uncore C-Box 11 Perfmon Counter 0 Package
Register Address: EB9H, 3769 MSR_C11_PMON_CTR1
Uncore C-Box 11 Perfmon Counter 1 Package
Register Address: EBAH, 3770 MSR_C11_PMON_CTR2
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-302 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 11 Perfmon Counter 2 Package
Register Address: EBBH, 3771 MSR_C11_PMON_CTR3
Uncore C-Box 11 Perfmon Counter 3 Package
Register Address: EC0H, 3776 MSR_C12_PMON_BOX_CTL
Uncore C-Box 12 Perfmon Local Box Wide Control Package
Register Address: EC1H, 3777 MSR_C12_PMON_EVNTSEL0
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 0 Package
Register Address: EC2H, 3778 MSR_C12_PMON_EVNTSEL1
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 1 Package
Register Address: EC3H, 3779 MSR_C12_PMON_EVNTSEL2
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 2 Package
Register Address: EC4H, 3780 MSR_C12_PMON_EVNTSEL3
Uncore C-Box 12 Perfmon Event Select for C-Box 12 Counter 3 Package
Register Address: EC5H, 3781 MSR_C12_PMON_BOX_FILTER0
Uncore C-Box 12 Perfmon Box Wide Filter 0 Package
Register Address: EC6H, 3782 MSR_C12_PMON_BOX_FILTER1
Uncore C-Box 12 Perfmon Box Wide Filter 1 Package
Register Address: EC7H, 3783 MSR_C12_PMON_BOX_STATUS
Uncore C-Box 12 Perfmon Box Wide Status Package
Register Address: EC8H, 3784 MSR_C12_PMON_CTR0
Uncore C-Box 12 Perfmon Counter 0 Package
Register Address: EC9H, 3785 MSR_C12_PMON_CTR1
Uncore C-Box 12 Perfmon Counter 1 Package
Register Address: ECAH, 3786 MSR_C12_PMON_CTR2
Uncore C-Box 12 Perfmon Counter 2 Package
Register Address: ECBH, 3787 MSR_C12_PMON_CTR3
Uncore C-Box 12 Perfmon Counter 3 Package
Register Address: ED0H, 3792 MSR_C13_PMON_BOX_CTL
Uncore C-Box 13 Perfmon local box wide control. Package
Register Address: ED1H, 3793 MSR_C13_PMON_EVNTSEL0
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 0 Package
Register Address: ED2H, 3794 MSR_C13_PMON_EVNTSEL1
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 1 Package
Register Address: ED3H, 3795 MSR_C13_PMON_EVNTSEL2
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 2 Package
Register Address: ED4H, 3796 MSR_C13_PMON_EVNTSEL3
Uncore C-Box 13 Perfmon Event Select for C-Box 13 Counter 3 Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-303
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: ED5H, 3797 MSR_C13_PMON_BOX_FILTER0
Uncore C-Box 13 Perfmon Box Wide Filter 0 Package
Register Address: ED6H, 3798 MSR_C13_PMON_BOX_FILTER1
Uncore C-Box 13 Perfmon Box Wide Filter 1 Package
Register Address: ED7H, 3799 MSR_C13_PMON_BOX_STATUS
Uncore C-Box 13 Perfmon Box Wide Status Package
Register Address: ED8H, 3800 MSR_C13_PMON_CTR0
Uncore C-Box 13 Perfmon Counter 0 Package
Register Address: ED9H, 3801 MSR_C13_PMON_CTR1
Uncore C-Box 13 Perfmon Counter 1 Package
Register Address: EDAH, 3802 MSR_C13_PMON_CTR2
Uncore C-Box 13 Perfmon Counter 2 Package
Register Address: EDBH, 3803 MSR_C13_PMON_CTR3
Uncore C-Box 13 Perfmon Counter 3 Package
Register Address: EE0H, 3808 MSR_C14_PMON_BOX_CTL
Uncore C-Box 14 Perfmon Local Box Wide Control Package
Register Address: EE1H, 3809 MSR_C14_PMON_EVNTSEL0
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 0 Package
Register Address: EE2H, 3810 MSR_C14_PMON_EVNTSEL1
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 1 Package
Register Address: EE3H, 3811 MSR_C14_PMON_EVNTSEL2
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 2 Package
Register Address: EE4H, 3812 MSR_C14_PMON_EVNTSEL3
Uncore C-Box 14 Perfmon Event Select for C-Box 14 Counter 3 Package
Register Address: EE5H, 3813 MSR_C14_PMON_BOX_FILTER
Uncore C-Box 14 Perfmon Box Wide Filter 0 Package
Register Address: EE6H, 3814 MSR_C14_PMON_BOX_FILTER1
Uncore C-Box 14 Perfmon Box Wide Filter 1 Package
Register Address: EE7H, 3815 MSR_C14_PMON_BOX_STATUS
Uncore C-Box 14 Perfmon Box Wide Status Package
Register Address: EE8H, 3816 MSR_C14_PMON_CTR0
Uncore C-Box 14 Perfmon Counter 0 Package
Register Address: EE9H, 3817 MSR_C14_PMON_CTR1
Uncore C-Box 14 Perfmon Counter 1 Package
Register Address: EEAH, 3818 MSR_C14_PMON_CTR2
Uncore C-Box 14 Perfmon Counter 2 Package
Register Address: EEBH, 3819 MSR_C14_PMON_CTR3
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-304 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 14 Perfmon Counter 3 Package
Register Address: EF0H, 3824 MSR_C15_PMON_BOX_CTL
Uncore C-Box 15 Perfmon Local Box Wide Control Package
Register Address: EF1H, 3825 MSR_C15_PMON_EVNTSEL0
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 0 Package
Register Address: EF2H, 3826 MSR_C15_PMON_EVNTSEL1
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 1 Package
Register Address: EF3H, 3827 MSR_C15_PMON_EVNTSEL2
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 2 Package
Register Address: EF4H, 3828 MSR_C15_PMON_EVNTSEL3
Uncore C-Box 15 Perfmon Event Select for C-Box 15 Counter 3 Package
Register Address: EF5H, 3829 MSR_C15_PMON_BOX_FILTER0
Uncore C-Box 15 Perfmon Box Wide Filter 0 Package
Register Address: EF6H, 3830 MSR_C15_PMON_BOX_FILTER1
Uncore C-Box 15 Perfmon Box Wide Filter 1 Package
Register Address: EF7H, 3831 MSR_C15_PMON_BOX_STATUS
Uncore C-Box 15 Perfmon Box Wide Status Package
Register Address: EF8H, 3832 MSR_C15_PMON_CTR0
Uncore C-Box 15 Perfmon Counter 0 Package
Register Address: EF9H, 3833 MSR_C15_PMON_CTR1
Uncore C-Box 15 Perfmon Counter 1 Package
Register Address: EFAH, 3834 MSR_C15_PMON_CTR2
Uncore C-Box 15 Perfmon Counter 2 Package
Register Address: EFBH, 3835 MSR_C15_PMON_CTR3
Uncore C-Box 15 Perfmon Counter 3 Package
Register Address: F00H, 3840 MSR_C16_PMON_BOX_CTL
Uncore C-Box 16 Perfmon for Box-Wide Control Package
Register Address: F01H, 3841 MSR_C16_PMON_EVNTSEL0
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 0 Package
Register Address: F02H, 3842 MSR_C16_PMON_EVNTSEL1
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 1 Package
Register Address: F03H, 3843 MSR_C16_PMON_EVNTSEL2
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 2 Package
Register Address: F04H, 3844 MSR_C16_PMON_EVNTSEL3
Uncore C-Box 16 Perfmon Event Select for C-Box 16 Counter 3 Package
Register Address: F05H, 3845 MSR_C16_PMON_BOX_FILTER0
Uncore C-Box 16 Perfmon Box Wide Filter 0 Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-305
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: F06H, 3846 MSR_C16_PMON_BOX_FILTER1
Uncore C-Box 16 Perfmon Box Wide Filter 1 Package
Register Address: F07H, 3847 MSR_C16_PMON_BOX_STATUS
Uncore C-Box 16 Perfmon Box Wide Status Package
Register Address: F08H, 3848 MSR_C16_PMON_CTR0
Uncore C-Box 16 Perfmon Counter 0 Package
Register Address: F09H, 3849 MSR_C16_PMON_CTR1
Uncore C-Box 16 Perfmon Counter 1 Package
Register Address: F0AH, 3850 MSR_C16_PMON_CTR2
Uncore C-Box 16 Perfmon Counter 2 Package
Register Address: F0BH, 3851 MSR_C16_PMON_CTR3
Uncore C-Box 16 Perfmon Counter 3 Package
Register Address: F10H, 3856 MSR_C17_PMON_BOX_CTL
Uncore C-Box 17 Perfmon for Box-Wide Control Package
Register Address: F11H, 3857 MSR_C17_PMON_EVNTSEL0
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 0 Package
Register Address: F12H, 3858 MSR_C17_PMON_EVNTSEL1
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 1 Package
Register Address: F13H, 3859 MSR_C17_PMON_EVNTSEL2
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 2 Package
Register Address: F14H, 3860 MSR_C17_PMON_EVNTSEL3
Uncore C-Box 17 Perfmon Event Select for C-Box 17 Counter 3 Package
Register Address: F15H, 3861 MSR_C17_PMON_BOX_FILTER0
Uncore C-Box 17 Perfmon Box Wide Filter 0 Package
Register Address: F16H, 3862 MSR_C17_PMON_BOX_FILTER1
Uncore C-Box 17 Perfmon Box Wide Filter1 Package
Register Address: F17H, 3863 MSR_C17_PMON_BOX_STATUS
Uncore C-Box 17 Perfmon Box Wide Status Package
Register Address: F18H, 3864 MSR_C17_PMON_CTR0
Uncore C-Box 17 Perfmon Counter 0 Package
Register Address: F19H, 3865 MSR_C17_PMON_CTR1
Uncore C-Box 17 Perfmon Counter 1 Package
Register Address: F1AH, 3866 MSR_C17_PMON_CTR2
Uncore C-Box 17 Perfmon Counter 2 Package
Register Address: F1BH, 3867 MSR_C17_PMON_CTR3
Uncore C-Box 17 Perfmon Counter 3 Package
Table 2-33. Uncore PMU MSRs in the Intel® Xeon® Processor E5 v3 Family (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-306 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.15 MSRS IN THE INTEL® CORE™ M PROCESSORS AND THE 5TH GENERATION
INTEL® CORE™ PROCESSORS
The Intel
®
Core™ M-5xxx processors, 5th generation Intel
®
Core™ Processors, and the Intel
®
Xeon
®
Processor
E3-1200 v4 family are based on Broadwell microarchitecture. The Intel
®
Core™ M-5xxx processors and 5th gener-
ation Intel
®
Core™ Processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_3DH. The Intel
®
Xeon
®
Processor E3-1200 v4 family and 5th generation Intel
®
Core™ Processors have a CPUID Signature
DisplayFamily_DisplayModel value of 06_47H. Processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_3DH or 06_47H support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-22, Table 2-25,
Table 2-29, Table 2-30, Table 2-34, and Table 2-35. For an MSR listed in Table 2-35 that also appears in the model-
specific tables of prior generations, Table 2-35 supersedes prior generation tables.
Table 2-34 lists MSRs that are common to processors based on the Broadwell microarchitectures (including CPUID
Signature DisplayFamily_DisplayModel values of 06_3DH, 06_47H, 06_4FH, and 06_56H).
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.” Thread
0Ovf_PMC0
1Ovf_PMC1
2Ovf_PMC2
3Ovf_PMC3
31:4 Reserved
32 Ovf_FixedCtr0
33 Ovf_FixedCtr1
34 Ovf_FixedCtr2
54:35 Reserved.
55 Trace_ToPA_PMI
See Section 33.2.7.2, “Table of Physical Addresses (ToPA).”
60:56 Reserved.
61 Ovf_Uncore
62 Ovf_BufDSSAVE
63 CondChgd
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2 and Section 20.6.2.2, “Global Counter Control Facilities.” Thread
0 Set 1 to clear Ovf_PMC0.
1 Set 1 to clear Ovf_PMC1.
2 Set 1 to clear Ovf_PMC2.
3 Set 1 to clear Ovf_PMC3.
31:4 Reserved.
32 Set 1 to clear Ovf_FixedCtr0.
33 Set 1 to clear Ovf_FixedCtr1.
34 Set 1 to clear Ovf_FixedCtr2
Vol. 4 2-307
MODEL-SPECIFIC REGISTERS (MSRS)
54:35 Reserved.
55 Set 1 to clear Trace_ToPA_PMI. See Section 33.2.7.2, “Table of Physical
Addresses (ToPA).”
60:56 Reserved.
61 Set 1 to clear Ovf_Uncore.
62 Set 1 to clear Ovf_BufDSSAVE.
63 Set 1 to clear CondChgd.
Register Address: 560H, 1376 IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W) Thread
6:0 Reserved.
MAXPHYADDR
1
-1:7 Base physical address.
63:MAXPHYADDR Reserved.
Register Address: 561H, 1377 IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W) Thread
6:0 Reserved.
31:7 MaskOrTableOffset
63:32 Output Offset.
Register Address: 570H, 1392 IA32_RTIT_CTL
Trace Control Register (R/W) Thread
0 TraceEn
1 Reserved, must be zero.
2OS
3User
6:4 Reserved, must be zero.
7CR3Filter
8ToPA
Writing 0 will #GP if also setting TraceEn.
9 Reserved, must be zero.
10 TSCEn
11 DisRETC
12 Reserved, must be zero.
13 Reserved; writing 0 will #GP if also setting TraceEn.
63:14 Reserved, must be zero.
Register Address: 571H, 1393 IA32_RTIT_STATUS
Tracing Status Register (R/W) Thread
0 Reserved, writes ignored.
1 ContexEn, writes ignored.
2 TriggerEn, writes ignored.
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-308 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-35 lists MSRs that are specific to Intel Core M processors and 5th Generation Intel Core Processors.
3 Reserved
4Error (R/W)
5Stopped
63:6 Reserved, must be zero.
Register Address: 572H, 1394 IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W) Thread
4:0 Reserved.
63:5 CR3[63:5] value to match.
Register Address: 620H, 1568 MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum frequency that hardware will select.
Package
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
7 Reserved.
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
63:15 Reserved.
NOTES:
1. MAXPHYADDR is reported by CPUID.80000008H:EAX[7:0].
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
Core
Table 2-34. Additional MSRs Common to Processors Based on Broadwell Microarchitectures
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-309
MODEL-SPECIFIC REGISTERS (MSRS)
3:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
9:4 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved.
15 CFG Lock (R/WO)
24:16 Reserved.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Enable Package C-State Auto-Demotion (R/W)
30 Enable Package C-State Undemotion (R/W)
63:31 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
39:32 Maximum Ratio Limit for 5C
Maximum turbo ratio limit of 5core active.
Package
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-310 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.16 MSRS IN THE INTEL® XEON® PROCESSOR E5 V4 FAMILY
The MSRs listed in Table 2-36 are available and common to the Intel
®
Xeon
®
Processor D Product Family (CPUID
Signature DisplayFamily_DisplayModel value of 06_56H) and to the Intel Xeon processors E5 v4 and E7 v4 families
(CPUID Signature DisplayFamily_DisplayModel value of 06_4FH). These processors are based on Broadwell
microarchitecture.
See Section 2.16.1 for lists of tables of MSRs that are supported by the Intel
®
Xeon
®
Processor D Family.
47:40 Maximum Ratio Limit for 6C
Maximum turbo ratio limit of 6core active.
Package
63:48 Reserved.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
See Table 2-20, Table 2-21, Table 2-22, Table 2-25, Table 2-29, Table 2-30, and Table 2-34 for other MSR definitions applicable to
processors with a CPUID Signature DisplayFamily_DisplayModel value of 06_3DH.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 4EH, 78 IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W) Package
0LockOut (R/WO)
See Table 2-2.
1Enable_PPIN (R/W)
See Table 2-2.
63:2 Reserved
Register Address: 4FH, 79 IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O) Package
63:0 Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
See Table 2-26.
Package
22:16 Reserved.
Table 2-35. Additional MSRs Supported by Intel® Core™ M Processors and 5th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-311
MODEL-SPECIFIC REGISTERS (MSRS)
23 PPIN_CAP (R/O)
See Table 2-26.
Package
27:24 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
See Table 2-26.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
See Table 2-26.
Package
30 Programmable TJ OFFSET (R/O)
See Table 2-26.
Package
39:31 Reserved.
47:40 Maximum Efficiency Ratio (R/O)
See Table 2-26.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
Core
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor
are available.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved.
15 CFG Lock (R/WO)
16 Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).
24:17 Reserved.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-312 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
30 Package C State Undemotion Enable (R/W)
63:31 Reserved.
Register Address: 179H, 377 IA32_MCG_CAP
Global Machine Check Capability (R/O) Thread
7:0 Count
8 MCG_CTL_P
9MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
15:12 Reserved
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 MCG_EM_P
26 MCG_ELOG_P
63:27 Reserved.
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in SMM.
Thread
57:0 Reserved.
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1, indicates that the SMM code access restriction is supported and
a host-space interface available to SMM handler.
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is supported and a
host-space interface available to SMM handler.
63:60 Reserved.
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Core
0 Thermal Status (R/O)
See Table 2-2.
1 Thermal Status Log (R/WC0)
See Table 2-2.
2 PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-313
MODEL-SPECIFIC REGISTERS (MSRS)
4 Critical Temperature Status (R/O)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal Threshold #1 Status (R/O)
See Table 2-2.
7 Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (R/O)
See Table 2-2.
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (R/O)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
12 Current Limit Status (R/O)
See Table 2-2.
13 Current Limit Log (R/WC0)
See Table 2-2.
14 Cross Domain Limit Status (R/O)
See Table 2-2.
15 Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16 Digital Readout (R/O)
See Table 2-2.
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O)
See Table 2-2.
31 Reading Valid (R/O)
See Table 2-2.
63:32 Reserved.
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Package
15:0 Reserved.
23:16 Temperature Target (R/O)
See Table 2-26.
27:24 TCC Activation Offset (R/W)
See Table 2-26.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-314 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:28 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 1C Package
15:8 Maximum Ratio Limit for 2C Package
23:16 Maximum Ratio Limit for 3C Package
31:24 Maximum Ratio Limit for 4C Package
39:32 Maximum Ratio Limit for 5C Package
47:40 Maximum Ratio Limit for 6C Package
55:48 Maximum Ratio Limit for 7C Package
63:56 Maximum Ratio Limit for 8C Package
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT1
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
7:0 Maximum Ratio Limit for 9C Package
15:8 Maximum Ratio Limit for 10C Package
23:16 Maximum Ratio Limit for 11C Package
31:24 Maximum Ratio Limit for 12C Package
39:32 Maximum Ratio Limit for 13C Package
47:40 Maximum Ratio Limit for 14C Package
55:48 Maximum Ratio Limit for 15C Package
63:56 Maximum Ratio Limit for 16C Package
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O) Package
3:0 Power Units
See Section 15.10.1, “RAPL Interfaces.”
Package
7:4 Reserved. Package
12:8 Energy Status Units
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value
is 0EH (or 61 micro-joules).
Package
15:13 Reserved. Package
19:16 Time Units
See Section 15.10.1, “RAPL Interfaces.”
Package
63:20 Reserved.
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-315
MODEL-SPECIFIC REGISTERS (MSRS)
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Energy consumed by DRAM devices.
Package
31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32 Reserved.
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 620H, 1568 MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing
to these fields allows software to control the minimum and the maximum frequency that hardware will select.
Package
63:15 Reserved.
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
7 Reserved.
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Reads return 0.
Package
Register Address: 690H, 1680 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
Package
0PROCHOT Status (R0)
When set, processor core frequency is reduced below the operating
system request due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
2 Power Budget Management Status (R0)
When set, frequency is reduced below the operating system request due
to PBM limit.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-316 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
3 Platform Configuration Services Status (R0)
When set, frequency is reduced below the operating system request due
to PCS limit.
4 Reserved.
5 Autonomous Utilization-Based Frequency Control Status (R0)
When set, frequency is reduced below the operating system request
because the processor has detected that utilization is low.
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from the Voltage Regulator.
7 Reserved.
8 Electrical Design Point Status (R0)
When set, frequency is reduced below the operating system request due
to electrical design point constraints (e.g., maximum electrical current
consumption).
9 Reserved.
10 Multi-Core Turbo Status (R0)
When set, frequency is reduced below the operating system request due
to Multi-Core Turbo limits.
12:11 Reserved.
13 Core Frequency P1 Status (R0)
When set, frequency is reduced below max non-turbo P1.
14 Core Max N-Core Turbo Frequency Limiting Status (R0)
When set, frequency is reduced below max n-core turbo frequency.
15 Core Frequency Limiting Status (R0)
When set, frequency is reduced below the operating system request.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
18 Power Budget Management Log
When set, indicates that the PBM Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
19 Platform Configuration Services Log
When set, indicates that the PCS Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-317
MODEL-SPECIFIC REGISTERS (MSRS)
20 Reserved.
21 Autonomous Utilization-Based Frequency Control Log
When set, indicates that the AUBFC Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 Reserved.
24 Electrical Design Point Log
When set, indicates that the EDP Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Reserved.
26 Multi-Core Turbo Log
When set, indicates that the Multi-Core Turbo Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28:27 Reserved.
29 Core Frequency P1 Log
When set, indicates that the Core Frequency P1 Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
30 Core Max N-Core Turbo Frequency Limiting Log
When set, indicates that the Core Max n-core Turbo Frequency Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
31 Core Frequency Limiting Log
When set, indicates that the Core Frequency Limiting Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:32 Reserved.
Register Address: 770H, 1904 IA32_PM_ENABLE
See Section 15.4.2, “Enabling HWP.” Package
Register Address: 771H, 1905 IA32_HWP_CAPABILITIES
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.” Thread
Register Address: 774H, 1908 IA32_HWP_REQUEST
See Section 15.4.4, “Managing HWP.” Thread
7:0 Minimum Performance (R/W)
15:8 Maximum Performance (R/W)
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-318 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
23:16 Desired Performance (R/W)
63:24 Reserved.
Register Address: 777H, 1911 IA32_HWP_STATUS
See Section 15.4.5, “HWP Feedback.” Thread
1:0 Reserved.
2 Excursion to Minimum (R/O)
63:3 Reserved.
Register Address: C8DH, 3213 IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
Thread
7:0 EventID (R/W)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8 Reserved.
41:32 RMID (R/W)
63:42 Reserved.
Register Address: C8FH, 3215 IA32_PQR_ASSOC
Resource Association Register (R/W) Thread
9:0 RMID
31:10 Reserved.
51:32 CLOS (R/W)
63: 52 Reserved.
Register Address: C90H, 3216 IA32_L3_QOS_MASK_0
L3 Class Of Service Mask - CLOS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 0 enforcement.
63:20 Reserved.
Register Address: C91H, 3217 IA32_L3_QOS_MASK_1
L3 Class Of Service Mask - CLOS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 1 enforcement.
63:20 Reserved.
Register Address: C92H, 3218 IA32_L3_QOS_MASK_2
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-319
MODEL-SPECIFIC REGISTERS (MSRS)
L3 Class Of Service Mask - CLOS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 2 enforcement.
63:20 Reserved.
Register Address: C93H, 3219 IA32_L3_QOS_MASK_3
L3 Class Of Service Mask - CLOS 3 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 3 enforcement.
63:20 Reserved.
Register Address: C94H, 3220 IA32_L3_QOS_MASK_4
L3 Class Of Service Mask - CLOS 4 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 4 enforcement.
63:20 Reserved.
Register Address: C95H, 3221 IA32_L3_QOS_MASK_5
L3 Class Of Service Mask - CLOS 5 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 5 enforcement.
63:20 Reserved.
Register Address: C96H, 3222 IA32_L3_QOS_MASK_6
L3 Class Of Service Mask - CLOS 6 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 6 enforcement.
63:20 Reserved.
Register Address: C97H, 3223 IA32_L3_QOS_MASK_7
L3 Class Of Service Mask - CLOS 7 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 7 enforcement.
63:20 Reserved.
Register Address: C98H, 3224 IA32_L3_QOS_MASK_8
L3 Class Of Service Mask - CLOS 8 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 8 enforcement.
63:20 Reserved.
Register Address: C99H, 3225 IA32_L3_QOS_MASK_9
L3 Class Of Service Mask - CLOS 9 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 9 enforcement.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-320 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.16.1 Additional MSRs Supported in the Intel® Xeon® Processor D Product Family
The MSRs listed in Table 2-37 are available to Intel
®
Xeon
®
Processor D Product Family (CPUID Signature
DisplayFamily_DisplayModel value of 06_56H). The Intel
®
Xeon
®
processor D product family is based on Broadwell
microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-29, Table 2-34, Table 2-36, and
Table 2-37.
63:20 Reserved.
Register Address: C9AH, 3226 IA32_L3_QOS_MASK_10
L3 Class Of Service Mask - CLOS 10 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 10 enforcement.
63:20 Reserved.
Register Address: C9BH, 3227 IA32_L3_QOS_MASK_11
L3 Class Of Service Mask - CLOS 11 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 11 enforcement.
63:20 Reserved.
Register Address: C9CH, 3228 IA32_L3_QOS_MASK_12
L3 Class Of Service Mask - CLOS 12 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 12 enforcement.
63:20 Reserved.
Register Address: C9DH, 3229 IA32_L3_QOS_MASK_13
L3 Class Of Service Mask - CLOS 13 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 13 enforcement.
63:20 Reserved.
Register Address: C9EH, 3230 IA32_L3_QOS_MASK_14
L3 Class Of Service Mask - CLOS 14 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 14 enforcement.
63:20 Reserved.
Register Address: C9FH, 3231 IA32_L3_QOS_MASK_15
L3 Class Of Service Mask - CLOS 15 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 15 enforcement.
63:20 Reserved.
Table 2-36. Additional MSRs Common to the Intel® Xeon® Processor D and the Intel® Xeon® Processor E5 v4 Family
Based on Broadwell Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-321
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 1ACH, 428 MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
62:0 Reserved. Package
63 Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration
1
specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1.
If 0, the processor uses factory-set configuration (Default).
Package
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 287H, 647 IA32_MC7_CTL2
See Table 2-2. Package
Register Address: 289H, 649 IA32_MC9_CTL2
See Table 2-2. Package
Register Address: 28AH, 650 IA32_MC10_CTL2
See Table 2-2. Package
Register Address: 291H, 657 IA32_MC17_CTL2
See Table 2-2. Package
Register Address: 292H, 658 IA32_MC18_CTL2
See Table 2-2. Package
Register Address: 293H, 659 IA32_MC19_CTL2
See Table 2-2. Package
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
2-322 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 425H, 1061 IA32_MC9_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 426H, 1062 IA32_MC9_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42BH, 1067 IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 10 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 445H, 1093 IA32_MC17_STATUS
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-323
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 449H, 1097 IA32_MC18_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44FH, 1103 IA32_MC19_MISC
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-324 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.16.2 Additional MSRs Supported in Intel® Xeon® Processors E5 v4 and E7 v4 Families
The MSRs listed in Table 2-37 are available to the Intel
®
Xeon
®
Processor E5 v4 and E7 v4 Families (CPUID
Signature DisplayFamily_DisplayModel value of 06_4FH). The Intel
®
Xeon
®
processor E5 v4 family is based on
Broadwell microarchitecture and supports the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-29, Table
2-34, Table 2-36, and Table 2-38.
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
See Table 2-20, Table 2-29, Table 2-34, and Table 2-36 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_56H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the
factory-set configuration is dependent on features specific to the processor and the platform.
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 1ACH, 428 MSR_TURBO_RATIO_LIMIT3
Config Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1.
Package
62:0 Reserved. Package
63 Semaphore for Turbo Ratio Limit Configuration
If 1, the processor uses override configuration
1
specified in
MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1, and
MSR_TURBO_RATIO_LIMIT2.
If 0, the processor uses factory-set configuration (Default).
Package
Register Address: 285H, 645 IA32_MC5_CTL2
See Table 2-2. Package
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 287H, 647 IA32_MC7_CTL2
See Table 2-2. Package
Register Address: 288H, 648 IA32_MC8_CTL2
See Table 2-2. Package
Register Address: 289H, 649 IA32_MC9_CTL2
See Table 2-2. Package
Register Address: 28AH, 650 IA32_MC10_CTL2
See Table 2-2. Package
Table 2-37. Additional MSRs Supported by Intel® Xeon® Processor D with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_56H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-325
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 28BH, 651 IA32_MC11_CTL2
See Table 2-2. Package
Register Address: 28CH, 652 IA32_MC12_CTL2
See Table 2-2. Package
Register Address: 28DH, 653 IA32_MC13_CTL2
See Table 2-2. Package
Register Address: 28EH, 654 IA32_MC14_CTL2
See Table 2-2. Package
Register Address: 28FH, 655 IA32_MC15_CTL2
See Table 2-2. Package
Register Address: 290H, 656 IA32_MC16_CTL2
See Table 2-2. Package
Register Address: 291H, 657 IA32_MC17_CTL2
See Table 2-2. Package
Register Address: 292H, 658 IA32_MC18_CTL2
See Table 2-2. Package
Register Address: 293H, 659 IA32_MC19_CTL2
See Table 2-2. Package
Register Address: 294H, 660 IA32_MC20_CTL2
See Table 2-2. Package
Register Address: 295H, 661 IA32_MC21_CTL2
See Table 2-2. Package
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 417H, 1047 IA32_MC5_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from the Intel QPI 0 module.
Package
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-326 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the home agent HA 0.
Package
Register Address: 420H, 1056 IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 421H, 1057 IA32_MC8_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 422H, 1058 IA32_MC8_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 423H, 1059 IA32_MC8_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the home agent HA 1.
Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 425H, 1061 IA32_MC9_STATUS
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-327
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 426H, 1062 IA32_MC9_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42BH, 1067 IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42CH, 1068 IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42DH, 1069 IA32_MC11_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42EH, 1070 IA32_MC11_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 42FH, 1071 IA32_MC11_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 430H, 1072 IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 431H, 1073 IA32_MC12_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-328 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 432H, 1074 IA32_MC12_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 433H, 1075 IA32_MC12_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 434H, 1076 IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 435H, 1077 IA32_MC13_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 436H, 1078 IA32_MC13_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 437H, 1079 IA32_MC13_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 438H, 1080 IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 439H, 1081 IA32_MC14_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43AH, 1082 IA32_MC14_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43BH, 1083 IA32_MC14_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43CH, 1084 IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43DH, 1085 IA32_MC15_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43EH, 1086 IA32_MC15_ADDR
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-329
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 43FH, 1087 IA32_MC15_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 440H, 1088 IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 441H, 1089 IA32_MC16_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 442H, 1090 IA32_MC16_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 443H, 1091 IA32_MC16_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 through MC 16 report MC errors from each channel of the integrated memory controllers.
Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 445H, 1093 IA32_MC17_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC17 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo0, CBo3, CBo6, CBo9,
CBo12, CBo15.
Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 449H, 1097 IA32_MC18_STATUS
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-330 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC18 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo1, CBo4, CBo7,
CBo10, CBo13, CBo16.
Package
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 44FH, 1103 IA32_MC19_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from the following pair of CBo/L3 Slices (if the pair is present): CBo2, CBo5, CBo8,
CBo11, CBo14, CBo17.
Package
Register Address: 450H, 1104 IA32_MC20_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 451H, 1105 IA32_MC20_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 452H, 1106 IA32_MC20_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 453H, 1107 IA32_MC20_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC20 reports MC errors from the Intel QPI 1 module.
Package
Register Address: 454H, 1108 IA32_MC21_CTL
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-331
MODEL-SPECIFIC REGISTERS (MSRS)
2.17 MSRS IN THE 6TH—13TH GENERATION INTEL® CORE™ PROCESSORS,
1ST
—5TH GENERATION INTEL® XEON® SCALABLE PROCESSOR FAMILIES,
INTEL® CORE™ ULTRA 7 PROCESSORS, 8TH GENERATION INTEL® CORE™ I3
PROCESSORS, AND INTEL® XEON® E PROCESSORS
6th generation Intel
®
Core™ processors are based on Skylake microarchitecture and have a CPUID Signature
DisplayFamily_DisplayModel value of 06_4EH or 06_5EH.
The Intel
®
Xeon
®
Scalable Processor Family based on the Skylake microarchitecture, the 2nd generation Intel
®
Xeon
®
Scalable Processor Family based on the Cascade Lake product, and the 3rd generation Intel
®
Xeon
®
Scal-
able Processor Family based on the Cooper Lake product all have a CPUID Signature DisplayFamily_DisplayModel
value of 06_55H.
7th generation Intel
®
Core™ processors are based on the Kaby Lake microarchitecture, 8th generation and 9th
generation Intel
®
Core™ processors, and Intel
®
Xeon
®
E processors are based on Coffee Lake microarchitecture;
these processors have a CPUID Signature DisplayFamily_DisplayModel value of 06_8EH or 06_9EH.
8th generation Intel
®
Core™ i3 processors are based on Cannon Lake microarchitecture and have a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_66H.
10th generation Intel
®
Core™ processors are based on Comet Lake microarchitecture (with a CPUID Signature
DisplayFamily_DisplayModel value of 06_A5H or 06_A6H) and Ice Lake microarchitecture (with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7DH or 06_7EH).
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 455H, 1109 IA32_MC21_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 456H, 1110 IA32_MC21_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: 457H, 1111 IA32_MC21_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC21 reports MC errors from the Intel QPI 2 module.
Package
Register Address: C81H, 3201 IA32_L3_QOS_CFG
Cache Allocation Technology Configuration (R/W) Package
0 CAT Enable. Set 1 to enable Cache Allocation Technology.
63:1 Reserved.
See Table 2-20, Table 2-21, Table 2-29, and Table 2-30 for other MSR definitions applicable to processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_45H.
NOTES:
1. An override configuration lower than the factory-set configuration is always supported. An override configuration higher than the fac-
tory-set configuration is dependent on features specific to the processor and the platform.
Table 2-38. Additional MSRs Supported by Intel® Xeon® Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_4FH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-332 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
11th generation Intel
®
Core™ processors are based on Tiger Lake microarchitecture and have a CPUID Signature
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH.
The 3rd generation Intel
®
Xeon
®
Scalable Processor Family is based on Ice Lake microarchitecture and has a
CPUID Signature DisplayFamily_DisplayModel value of 06_6AH or 06_6CH.
12th generation Intel
®
Core™ processors supporting the Alder Lake performance hybrid architecture have a CPUID
Signature DisplayFamily_DisplayModel value of 06_97H or 06_9AH.
13th generation Intel
®
Core™ processors supporting the Raptor Lake performance hybrid architecture have a
CPUID Signature DisplayFamily_DisplayModel value of 06_BAH, 06_B7H, or 06_BFH.
The 4th generation Intel
®
Xeon
®
Scalable Processor Family is based on Sapphire Rapids microarchitecture and has
a CPUID Signature DisplayFamily_DisplayModel value of 06_8FH.
The 5th generation Intel
®
Xeon
®
Scalable Processor Family is based on Emerald Rapids microarchitecture and has
a CPUID Signature DisplayFamily_DisplayModel value of 06_CFH.
The Intel
®
Core™ Ultra 7 processor is based on Meteor Lake hybrid architecture and has a CPUID Signature
DisplayFamily_DisplayModel value of 06_AAH.
These processors support the MSR interfaces listed in Table 2-20, Table 2-21, Table 2-25, Table 2-29, Table 2-35,
and Table 2-39
1
. For an MSR listed in Table 2-39 that also appears in the model-specific tables of prior generations,
Table 2-39 supersede prior generation tables.
Tables 2-40 through 2-52 list additional supported MSR interfaces for specific processors; see each table for addi-
tional details.
The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and
MSR_PLATFORM_POWER_LIMIT) is limited to the power-delivery domain and the specifics of the power delivery
integration may vary by platform vendor’s implementation.
1. MSRs at the following addresses are not supported in the 12th generation Intel Core processor E-core: 3F7H. MSRs at the following
addresses are not supported in the 12th generation Intel Core processor E-core or P-core: 652H, 653H, 655H, 656H, DB0H, DB1H,
DB2H, and D90H.
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Thread
Register Address: FEH, 254 IA32_MTRRCAP
MTRR Capability (R/O, Architectural)
See Table 2-2
Thread
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Core
0 Thermal Status (R/O)
See Table 2-2.
1 Thermal Status Log (R/WC0)
See Table 2-2.
2 PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
Vol. 4 2-333
MODEL-SPECIFIC REGISTERS (MSRS)
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4 Critical Temperature Status (R/O)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal threshold #1 Status (R/O)
See Table 2-2.
7 Thermal threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (R/O)
See Table 2-2.
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (R/O)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
12 Current Limit Status (R/O)
See Table 2-2.
13 Current Limit Log (R/WC0)
See Table 2-2.
14 Cross Domain Limit Status (R/O)
See Table 2-2.
15 Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16 Digital Readout (R/O)
See Table 2-2.
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O)
See Table 2-2.
31 Reading Valid (R/O)
See Table 2-2.
63:32 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode
R/O if MSR_PLATFORM_INFO.[28] = 0, and R/W if MSR_PLATFORM_INFO.[28] = 1
Package
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-334 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
7:0 Maximum Ratio Limit for 1C
Maximum turbo ratio limit of 1 core active.
Package
15:8 Maximum Ratio Limit for 2C
Maximum turbo ratio limit of 2 core active.
Package
23:16 Maximum Ratio Limit for 3C
Maximum turbo ratio limit of 3 core active.
Package
31:24 Maximum Ratio Limit for 4C
Maximum turbo ratio limit of 4 core active.
Package
63:32 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-4) that points to the MSR containing the most recent branch record.
Thread
Register Address: 1FCH, 508 MSR_POWER_CTL
Power Control Register
See http://biosbits.org.
Core
0 Reserved.
1C1E Enable (R/W)
When set to ‘1’, will enable the CPU to switch to the Minimum Enhanced
Intel SpeedStep Technology operating point when all execution cores enter
MWAIT (C1).
Package
18:2 Reserved.
19 Disable Energy Efficiency Optimization (R/W)
Setting this bit disables the P-States energy efficiency optimization.
Default value is 0. Disable/enable the energy efficiency optimization in P-
State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an
effect only in the turbo range or into PERF_MIN_CTL value if it is not zero
set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect
between the OS desired or OS maximize to the OS minimize performance
setting.
20 Disable Race to Halt Optimization (R/W)
Setting this bit disables the Race to Halt optimization and avoids this
optimization limitation to execute below the most efficient frequency ratio.
Default value is 0 for processors that support Race to Halt optimization.
63:21 Reserved.
Register Address: 300H, 768 MSR_SGXOWNEREPOCH0
Lower 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.
Package
63:0 Lower 64 bits of an 128-bit external entropy value for key derivation of an
enclave.
Register Address: 301H, 769 MSR_SGXOWNEREPOCH1
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-335
MODEL-SPECIFIC REGISTERS (MSRS)
Upper 64 Bit CR_SGXOWNEREPOCH (W)
Writes do not update CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in the package.
Package
63:0 Upper 64 bits of an 128-bit external entropy value for key derivation of an
enclave.
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”
0 Ovf_PMC0 Thread
1 Ovf_PMC1 Thread
2 Ovf_PMC2 Thread
3 Ovf_PMC3 Thread
4 Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4) Thread
5 Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5) Thread
6 Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6) Thread
7 Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7) Thread
31:8 Reserved.
32 Ovf_FixedCtr0 Thread
33 Ovf_FixedCtr1 Thread
34 Ovf_FixedCtr2 Thread
54:35 Reserved
55 Trace_ToPA_PMI Thread
57:56 Reserved.
58 LBR_Frz Thread
59 CTR_Frz Thread
60 ASCI Thread
61 Ovf_Uncore Thread
62 Ovf_BufDSSAVE Thread
63 CondChgd Thread
Register Address: 390H, 912 IA32_PERF_GLOBAL_STATUS_RESET
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”
0 Set 1 to clear Ovf_PMC0. Thread
1 Set 1 to clear Ovf_PMC1. Thread
2 Set 1 to clear Ovf_PMC2. Thread
3 Set 1 to clear Ovf_PMC3. Thread
4 Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). Thread
5 Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). Thread
6 Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-336 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
7 Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). Thread
31:8 Reserved.
32 Set 1 to clear Ovf_FixedCtr0. Thread
33 Set 1 to clear Ovf_FixedCtr1. Thread
34 Set 1 to clear Ovf_FixedCtr2. Thread
54:35 Reserved.
55 Set 1 to clear Trace_ToPA_PMI. Thread
57:56 Reserved.
58 Set 1 to clear LBR_Frz. Thread
59 Set 1 to clear CTR_Frz. Thread
60 Set 1 to clear ASCI. Thread
61 Set 1 to clear Ovf_Uncore. Thread
62 Set 1 to clear Ovf_BufDSSAVE. Thread
63 Set 1 to clear CondChgd. Thread
Register Address: 391H, 913 IA32_PERF_GLOBAL_STATUS_SET
See Table 2-2 and Section 20.2.4, “Architectural Performance Monitoring Version 4.”
0 Set 1 to cause Ovf_PMC0 = 1. Thread
1 Set 1 to cause Ovf_PMC1 = 1. Thread
2 Set 1 to cause Ovf_PMC2 = 1. Thread
3 Set 1 to cause Ovf_PMC3 = 1. Thread
4 Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4). Thread
5 Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5). Thread
6 Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6). Thread
7 Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7). Thread
31:8 Reserved.
32 Set 1 to cause Ovf_FixedCtr0 = 1. Thread
33 Set 1 to cause Ovf_FixedCtr1 = 1. Thread
34 Set 1 to cause Ovf_FixedCtr2 = 1. Thread
54:35 Reserved.
55 Set 1 to cause Trace_ToPA_PMI = 1. Thread
57:56 Reserved.
58 Set 1 to cause LBR_Frz = 1. Thread
59 Set 1 to cause CTR_Frz = 1. Thread
60 Set 1 to cause ASCI = 1. Thread
61 Set 1 to cause Ovf_Uncore. Thread
62 Set 1 to cause Ovf_BufDSSAVE. Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-337
MODEL-SPECIFIC REGISTERS (MSRS)
63 Reserved.
Register Address: 392H, 914 IA32_PERF_GLOBAL_INUSE
See Table 2-2. Thread
Register Address: 3F7H, 1015 MSR_PEBS_FRONTEND
FrontEnd Precise Event Condition Select (R/W) Thread
2:0 Event Code Select
3 Reserved
4 Event Code Select High
7:5 Reserved.
19:8 IDQ_Bubble_Length Specifier
22:20 IDQ_Bubble_Width Specifier
63:23 Reserved.
Register Address: 500H, 1280 IA32_SGX_SVN_STATUS
Status and SVN Threshold of SGX Support for ACM (R/O) Thread
0Lock
See Section 39.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
15:1 Reserved.
23:16 SGX_SVN_SINIT
See Section 39.11.3, “Interactions with Authenticated Code Modules
(ACMs).”
63:24 Reserved.
Register Address: 560H, 1376 IA32_RTIT_OUTPUT_BASE
Trace Output Base Register (R/W)
See Table 2-2.
Thread
Register Address: 561H, 1377 IA32_RTIT_OUTPUT_MASK_PTRS
Trace Output Mask Pointers Register (R/W)
See Table 2-2.
Thread
Register Address: 570H, 1392 IA32_RTIT_CTL
Trace Control Register (R/W) Thread
0 TraceEn
1CYCEn
2OS
3User
6:4 Reserved, must be zero.
7CR3Filter
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-338 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
8ToPA
Writing 0 will #GP if also setting TraceEn.
9MTCEn
10 TSCEn
11 DisRETC
12 Reserved, must be zero.
13 BranchEn
17:14 MTCFreq
18 Reserved, must be zero.
22:19 CycThresh
23 Reserved, must be zero.
27:24 PSBFreq
31:28 Reserved, must be zero.
35:32 ADDR0_CFG
39:36 ADDR1_CFG
63:40 Reserved, must be zero.
Register Address: 571H, 1393 IA32_RTIT_STATUS
Tracing Status Register (R/W) Thread
0 FilterEn, writes ignored.
1 ContexEn, writes ignored.
2 TriggerEn, writes ignored.
3 Reserved
4Error (R/W)
5Stopped
31:6 Reserved, must be zero.
48:32 PacketByteCnt
63:49 Reserved, must be zero.
Register Address: 572H, 1394 IA32_RTIT_CR3_MATCH
Trace Filter CR3 Match Register (R/W) Thread
4:0 Reserved
63:5 CR3[63:5] value to match
Register Address: 580H, 1408 IA32_RTIT_ADDR0_A
Region 0 Start Address (R/W) Thread
63:0 See Table 2-2.
Register Address: 581H, 1409 IA32_RTIT_ADDR0_B
Region 0 End Address (R/W) Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-339
MODEL-SPECIFIC REGISTERS (MSRS)
63:0 See Table 2-2.
Register Address: 582H, 1410 IA32_RTIT_ADDR1_A
Region 1 Start Address (R/W) Thread
63:0 See Table 2-2.
Register Address: 583H, 1411 IA32_RTIT_ADDR1_B
Region 1 End Address (R/W) Thread
63:0 See Table 2-2.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 64DH, 1613 MSR_PLATFORM_ENERGY_COUNTER
Platform Energy Counter (R/O)
This MSR is valid only if both platform vendor hardware implementation and BIOS enablement support it. This MSR
will read 0 if not valid.
Platform
31:0 Total energy consumed by all devices in the platform that receive power
from integrated power delivery mechanism, included platform devices are
processor cores, SOC, memory, add-on or peripheral devices that get
powered directly from the platform power delivery means. The energy
units are specified in the MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
63:32 Reserved.
Register Address: 64EH, 1614 MSR_PPERF
Productive Performance Count (R/O) Thread
63:0 Hardware’s view of workload scalability. See Section 15.4.5.1.
Register Address: 64FH, 1615 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
Package
0PROCHOT Status (R0)
When set, frequency is reduced below the operating system request due
to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal event.
3:2 Reserved.
4 Residency State Regulation Status (R0)
When set, frequency is reduced below the operating system request due
to residency state regulation limit.
5 Running Average Thermal Limit Status (R0)
When set, frequency is reduced below the operating system request due
to Running Average Thermal Limit (RATL).
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-340 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
6 VR Therm Alert Status (R0)
When set, frequency is reduced below the operating system request due
to a thermal alert from a processor Voltage Regulator (VR).
7VR Therm Design Current Status (R0)
When set, frequency is reduced below the operating system request due
to VR thermal design current limit.
8Other Status (R0)
When set, frequency is reduced below the operating system request due
to electrical or other constraints.
9 Reserved.
10 Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced below the operating system request due
to package/platform-level power limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced below the operating system request due
to package/platform-level power limiting PL2/PL3.
12 Max Turbo Limit Status (R0)
When set, frequency is reduced below the operating system request due
to multi-core turbo limits.
13 Turbo Transition Attenuation Status (R0)
When set, frequency is reduced below the operating system request due
to Turbo transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
15:14 Reserved.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
19:18 Reserved.
20 Residency State Regulation Log
When set, indicates that the Residency State Regulation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
21 Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-341
MODEL-SPECIFIC REGISTERS (MSRS)
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 VR Thermal Design Current Log
When set, indicates that the VR TDC Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24 Other Log
When set, indicates that the Other Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Reserved.
26 Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package or Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package or Platform Level PL2/PL3 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 Max Turbo Limit Log
When set, indicates that the Max Turbo Limit Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
29 Turbo Transition Attenuation Log
When set, indicates that the Turbo Transition Attenuation Status bit has
asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:30 Reserved.
Register Address: 652H, 1618 MSR_PKG_HDC_CONFIG
HDC Configuration (R/W) Package
2:0 PKG_Cx_Monitor
Configures Package Cx state threshold for
MSR_PKG_HDC_DEEP_RESIDENCY.
63: 3 Reserved.
Register Address: 653H, 1619 MSR_CORE_HDC_RESIDENCY
Core HDC Idle Residency (R/O) Core
63:0 Core_Cx_Duty_Cycle_Cnt
Register Address: 655H, 1621 MSR_PKG_HDC_SHALLOW_RESIDENCY
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-342 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Accumulate the cycles the package was in C2 state and at least one logical processor was in forced idle (R/O) Package
63:0 Pkg_C2_Duty_Cycle_Cnt
Register Address: 656H, 1622 MSR_PKG_HDC_DEEP_RESIDENCY
Package Cx HDC Idle Residency (R/O) Package
63:0 Pkg_Cx_Duty_Cycle_Cnt
Register Address: 658H, 1624 MSR_WEIGHTED_CORE_C0
Core-count Weighted C0 Residency (R/O) Package
63:0 Increment at the same rate as the TSC. The increment each cycle is
weighted by the number of processor cores in the package that reside in
C0. If N cores are simultaneously in C0, then each cycle the counter
increments by N.
Register Address: 659H, 1625 MSR_ANY_CORE_C0
Any Core C0 Residency (R/O) Package
63:0 Increment at the same rate as the TSC. The increment each cycle is one if
any processor core in the package is in C0.
Register Address: 65AH, 1626 MSR_ANY_GFXE_C0
Any Graphics Engine C0 Residency (R/O) Package
63:0 Increment at the same rate as the TSC. The increment each cycle is one if
any processor graphic device’s compute engines are in C0.
Register Address: 65BH, 1627 MSR_CORE_GFXE_OVERLAP_C0
Core and Graphics Engine Overlapped C0 Residency (R/O) Package
63:0 Increment at the same rate as the TSC. The increment each cycle is one if
at least one compute engine of the processor graphics is in C0 and at least
one processor core in the package is also in C0.
Register Address: 65CH, 1628 MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W-L)
Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration
power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor.
The processor implements an exponential-weighted algorithm in the placement of the time windows.
Platform
14:0 Platform Power Limit #1
Average Power limit value which the platform must not exceed over a time
window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies with
product skus. The unit is specified in MSR_RAPLPOWER_UNIT.
15 Enable Platform Power Limit #1
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #1 over the time
window specified by Power Limit #1 Time Window.
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-343
MODEL-SPECIFIC REGISTERS (MSRS)
16 Platform Clamping Limitation #1
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #1
value.
This bit is writeable only when CPUID (EAX=6):EAX[4] is set.
23:17 Time Window for Platform Power Limit #1
Specifies the duration of the time window over which Platform Power
Limit 1 value should be maintained for sustained long duration. This field is
made up of two numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, and the unit is specified in
MSR_RAPL_POWER_UNIT[Time Unit].
31:24 Reserved.
46:32 Platform Power Limit #2
Average Power limit value which the platform must not exceed over the
Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration Power
Limit (i.e., Platform Power Limit # 1).
47 Enable Platform Power Limit #2
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #2 over the Short
Duration time window.
48 Platform Clamping Limitation #2
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #2
value.
62:49 Reserved.
63 Lock. Setting this bit will lock all other bits of this MSR until system RESET.
Register Address: 690H, 1680 MSR_LASTBRANCH_16_FROM_IP
Last Branch Record 16 From IP (R/W)
One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the source instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.12.
Thread
Register Address: 691H, 1681 MSR_LASTBRANCH_17_FROM_IP
Last Branch Record 17 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 692H, 1682 MSR_LASTBRANCH_18_FROM_IP
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-344 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 18 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 693H, 1683 MSR_LASTBRANCH_19_FROM_IP
Last Branch Record 19From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 694H, 1684 MSR_LASTBRANCH_20_FROM_IP
Last Branch Record 20 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 695H, 1685 MSR_LASTBRANCH_21_FROM_IP
Last Branch Record 21 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 696H, 1686 MSR_LASTBRANCH_22_FROM_IP
Last Branch Record 22 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 697H, 1687 MSR_LASTBRANCH_23_FROM_IP
Last Branch Record 23 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 698H, 1688 MSR_LASTBRANCH_24_FROM_IP
Last Branch Record 24 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 699H, 1689 MSR_LASTBRANCH_25_FROM_IP
Last Branch Record 25 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 69AH, 1690 MSR_LASTBRANCH_26_FROM_IP
Last Branch Record 26 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 69BH, 1691 MSR_LASTBRANCH_27_FROM_IP
Last Branch Record 27 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 69CH, 1692 MSR_LASTBRANCH_28_FROM_IP
Last Branch Record 28 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 69DH, 1693 MSR_LASTBRANCH_29_FROM_IP
Last Branch Record 29 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 69EH, 1694 MSR_LASTBRANCH_30_FROM_IP
Last Branch Record 30 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-345
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 69FH, 1695 MSR_LASTBRANCH_31_FROM_IP
Last Branch Record 31 From IP (R/W)
See description of MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 6B0H, 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Processor Graphics (R/W)
(Frequency refers to processor graphics frequency.)
Package
0PROCHOT Status (R0)
When set, frequency is reduced due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2 Reserved.
5 Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal limit.
6 VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a processor
Voltage Regulator.
7 VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8Other Status (R0)
When set, frequency is reduced due to electrical or other constraints.
9 Reserved.
10 Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/platform-level power
limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/platform-level power
limiting PL2/PL3.
12 Inefficient Operation Status (R0)
When set, processor graphics frequency is operating below target
frequency.
15:13 Reserved.
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18 Reserved.
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-346 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
21 Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24 Other Log
When set, indicates that the OTHER Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Reserved.
26 Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 Inefficient Operation Log
When set, indicates that the Inefficient Operation Status bit has asserted
since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:29 Reserved.
Register Address: 6B1H, 1713 MSR_RING_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Ring Interconnect (R/W)
(Frequency refers to ring interconnect in the uncore.)
Package
0PROCHOT Status (R0)
When set, frequency is reduced due to assertion of external PROCHOT.
1 Thermal Status (R0)
When set, frequency is reduced due to a thermal event.
4:2 Reserved.
5 Running Average Thermal Limit Status (R0)
When set, frequency is reduced due to running average thermal limit.
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-347
MODEL-SPECIFIC REGISTERS (MSRS)
6 VR Therm Alert Status (R0)
When set, frequency is reduced due to a thermal alert from a processor
Voltage Regulator.
7 VR Thermal Design Current Status (R0)
When set, frequency is reduced due to VR TDC limit.
8Other Status (R0)
When set, frequency is reduced due to electrical or other constraints.
9 Reserved.
10 Package/Platform-Level Power Limiting PL1 Status (R0)
When set, frequency is reduced due to package/Platform-level power
limiting PL1.
11 Package/Platform-Level PL2 Power Limiting Status (R0)
When set, frequency is reduced due to package/Platform-level power
limiting PL2/PL3.
15:12 Reserved
16 PROCHOT Log
When set, indicates that the PROCHOT Status bit has asserted since the
log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
17 Thermal Log
When set, indicates that the Thermal Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
20:18 Reserved.
21 Running Average Thermal Limit Log
When set, indicates that the RATL Status bit has asserted since the log bit
was last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR Therm Alert Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
23 VR Thermal Design Current Log
When set, indicates that the VR Therm Alert Status bit has asserted since
the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
24 Other Log
When set, indicates that the OTHER Status bit has asserted since the log
bit was last cleared.
This log bit will remain set until cleared by software writing 0.
25 Reserved.
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-348 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
26 Package/Platform-Level PL1 Power Limiting Log
When set, indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
27 Package/Platform-Level PL2 Power Limiting Log
When set, indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
63:28 Reserved.
Register Address: 6D0H, 1744 MSR_LASTBRANCH_16_TO_IP
Last Branch Record 16 To IP (R/W)
One of 32 triplets of last branch record registers on the last branch record stack. This part of the stack contains
pointers to the destination instruction. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.12.
Thread
Register Address: 6D1H, 1745 MSR_LASTBRANCH_17_TO_IP
Last Branch Record 17 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D2H, 1746 MSR_LASTBRANCH_18_TO_IP
Last Branch Record 18 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D3H, 1747 MSR_LASTBRANCH_19_TO_IP
Last Branch Record 19To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D4H, 1748 MSR_LASTBRANCH_20_TO_IP
Last Branch Record 20 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D5H, 1749 MSR_LASTBRANCH_21_TO_IP
Last Branch Record 21 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D6H, 1750 MSR_LASTBRANCH_22_TO_IP
Last Branch Record 22 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D7H, 1751 MSR_LASTBRANCH_23_TO_IP
Last Branch Record 23 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6D8H, 1752 MSR_LASTBRANCH_24_TO_IP
Last Branch Record 24 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-349
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6D9H, 1753 MSR_LASTBRANCH_25_TO_IP
Last Branch Record 25 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6DAH, 1754 MSR_LASTBRANCH_26_TO_IP
Last Branch Record 26 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6DBH, 1755 MSR_LASTBRANCH_27_TO_IP
Last Branch Record 27 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6DCH, 1756 MSR_LASTBRANCH_28_TO_IP
Last Branch Record 28 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6DDH, 1757 MSR_LASTBRANCH_29_TO_IP
Last Branch Record 29 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6DEH, 1758 MSR_LASTBRANCH_30_TO_IP
Last Branch Record 30 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 6DFH, 1759 MSR_LASTBRANCH_31_TO_IP
Last Branch Record 31 To IP (R/W)
See description of MSR_LASTBRANCH_0_TO_IP.
Thread
Register Address: 770H, 1904 IA32_PM_ENABLE
See Section 15.4.2, “Enabling HWP.” Package
Register Address: 771H, 1905 IA32_HWP_CAPABILITIES
See Section 15.4.3, “HWP Performance Range and Dynamic Capabilities.” Thread
Register Address: 772H, 1906 IA32_HWP_REQUEST_PKG
See Section 15.4.4, “Managing HWP.” Package
Register Address: 773H, 1907 IA32_HWP_INTERRUPT
See Section 15.4.6, “HWP Notifications.” Thread
Register Address: 774H, 1908 IA32_HWP_REQUEST
See Section 15.4.4, “Managing HWP.” Thread
7:0 Minimum Performance (R/W)
15:8 Maximum Performance (R/W)
23:16 Desired Performance (R/W)
31:24 Energy/Performance Preference (R/W)
41:32 Activity Window (R/W)
42 Package Control (R/W)
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-350 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:43 Reserved.
Register Address: 777H, 1911 IA32_HWP_STATUS
See Section 15.4.5, “HWP Feedback.” Thread
Register Address: D90H, 3472 IA32_BNDCFGS
See Table 2-2. Thread
Register Address: DA0H, 3488 IA32_XSS
See Table 2-2. Thread
Register Address: DB0H, 3504 IA32_PKG_HDC_CTL
See Section 15.5.2, “Package level Enabling HDC.” Package
Register Address: DB1H, 3505 IA32_PM_CTL1
See Section 15.5.3, “Logical-Processor Level HDC Control.” Thread
Register Address: DB2H, 3506 IA32_THREAD_STALL
See Section 15.5.4.1, “IA32_THREAD_STALL.” Thread
Register Address: DC0H, 3520 MSR_LBR_INFO_0
Last Branch Record 0 Additional Information (R/W)
One of 32 triplet of last branch record registers on the last branch record stack. This part of the stack contains flag,
TSX-related and elapsed cycle information. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.9.1, “LBR Stack.”
Thread
Register Address: DC1H, 3521 MSR_LBR_INFO_1
Last Branch Record 1 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC2H, 3522 MSR_LBR_INFO_2
Last Branch Record 2 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC3H, 3523 MSR_LBR_INFO_3
Last Branch Record 3 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC4H, 3524 MSR_LBR_INFO_4
Last Branch Record 4 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC5H, 3525 MSR_LBR_INFO_5
Last Branch Record 5 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC6H, 3526 MSR_LBR_INFO_6
Last Branch Record 6 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC7H, 3527 MSR_LBR_INFO_7
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-351
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 7 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC8H, 3528 MSR_LBR_INFO_8
Last Branch Record 8 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DC9H, 3529 MSR_LBR_INFO_9
Last Branch Record 9 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DCAH, 3530 MSR_LBR_INFO_10
Last Branch Record 10 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DCBH, 3531 MSR_LBR_INFO_11
Last Branch Record 11 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DCCH, 3532 MSR_LBR_INFO_12
Last Branch Record 12 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DCDH, 3533 MSR_LBR_INFO_13
Last Branch Record 13 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DCEH, 3534 MSR_LBR_INFO_14
Last Branch Record 14 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DCFH, 3535 MSR_LBR_INFO_15
Last Branch Record 15 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD0H, 3536 MSR_LBR_INFO_16
Last Branch Record 16 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD1H, 3537 MSR_LBR_INFO_17
Last Branch Record 17 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD2H, 3538 MSR_LBR_INFO_18
Last Branch Record 18 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD3H, 3539 MSR_LBR_INFO_19
Last Branch Record 19 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-352 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: DD4H, 3540 MSR_LBR_INFO_20
Last Branch Record 20 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD5H, 3541 MSR_LBR_INFO_21
Last Branch Record 21 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD6H, 3542 MSR_LBR_INFO_22
Last Branch Record 22 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD7H, 3543 MSR_LBR_INFO_23
Last Branch Record 23 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD8H, 3544 MSR_LBR_INFO_24
Last Branch Record 24 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DD9H, 3545 MSR_LBR_INFO_25
Last Branch Record 25 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DDAH, 3546 MSR_LBR_INFO_26
Last Branch Record 26 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DDBH, 3547 MSR_LBR_INFO_27
Last Branch Record 27 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DDCH, 3548 MSR_LBR_INFO_28
Last Branch Record 28 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DDDH, 3549 MSR_LBR_INFO_29
Last Branch Record 29 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DDEH, 3550 MSR_LBR_INFO_30
Last Branch Record 30 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Register Address: DDFH, 3551 MSR_LBR_INFO_31
Last Branch Record 31 Additional Information (R/W)
See description of MSR_LBR_INFO_0.
Thread
Table 2-39. Additional MSRs Supported by the 6th—13th Generation Intel® Core™ Processors, 1st—5th Generation
Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Generation Intel® Core™ i3 Processors,
and Intel® Xeon® E Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-353
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-40 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_4EH, 06_5EH, 06_8EH, 06_9EH, or 06_66H.
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and 8th generation Intel® Core™ i3 Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 394H, 916 MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W) Package
19:0 Reserved.
20 Enable overflow propagation.
21 Reserved.
22 Enable counting.
63:23 Reserved.
Register Address: 395H, 917 MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter Package
43:0 Current count.
63:44 Reserved.
Register Address: 396H, 918 MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O) Package
3:0 Specifies the number of C-Box units with programmable counters
(including processor cores and processor graphics).
63:4 Reserved.
Register Address: 3B0H, 946 MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0 Package
Register Address: 3B1H, 947 MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1 Package
Register Address: 3B2H, 944 MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR Package
Register Address: 3B3H, 945 MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb Unit, Counter 1 Event Select MSR Package
Register Address: 700H, 1792 MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR Package
Register Address: 701H, 1793 MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR Package
Register Address: 706H, 1798 MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0 Package
Register Address: 707H, 1799 MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1 Package
Register Address: 710H, 1808 MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR Package
Register Address: 711H, 1809 MSR_UNC_CBO_1_PERFEVTSEL1
2-354 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 1, Counter 1 Event Select MSR Package
Register Address: 716H, 1814 MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0 Package
Register Address: 717H, 1815 MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1 Package
Register Address: 720H, 1824 MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR Package
Register Address: 721H, 1825 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR Package
Register Address: 726H, 1830 MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0 Package
Register Address: 727H, 1831 MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1 Package
Register Address: 730H, 1840 MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR Package
Register Address: 731H, 1841 MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR Package
Register Address: 736H, 1846 MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0 Package
Register Address: 737H, 1847 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 Package
Register Address: E01H, 3585 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4Slice 4select.
18:5 Reserved.
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved.
Register Address: E02H, 3586 MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status Package
0 Fixed counter overflowed.
1 An ARB counter overflowed.
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and 8th generation Intel® Core™ i3 Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-355
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.1 MSRs Introduced in 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Table 2-41 lists additional MSRs for 7th generation and 8th generation Intel Core processors with a CPUID Signa-
ture DisplayFamily_DisplayModel value of 06_8EH or 06_9EH. For an MSR listed in Table 2-41 that also appears in
the model-specific tables of prior generations, Table 2-41 supersedes prior generation tables.
2 Reserved.
3 A CBox counter overflowed (on any slice).
63:4 Reserved.
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 80H, 128 MSR_TRACE_HUB_STH_ACPIBAR_BASE
NPK Address Used by AET Messages (R/W) Package
0Lock Bit
If set, this MSR cannot be re-written anymore. Lock bit has to be set in
order for the AET packets to be directed to NPK MMIO.
17:1 Reserved.
63:18 ACPIBAR_BASE_ADDRESS
AET target address in NPK MMIO space.
Register Address: 1F4H, 500 MSR_PRMRR_PHYS_BASE
Processor Reserved Memory Range Register - Physical Base Control Register (R/W) Core
2:0 MemType
PRMRR BASE MemType.
11:3 Reserved.
45:12 Base
PRMRR Base Address.
63:46 Reserved.
Register Address: 1F5H, 501 MSR_PRMRR_PHYS_MASK
Processor Reserved Memory Range Register - Physical Mask Control Register (R/W) Core
9:0 Reserved.
10 Lock
Lock bit for the PRMRR.
11 VLD
Enable bit for the PRMRR.
45:12 Mask
PRMRR MASK bits.
Table 2-40. Uncore PMU MSRs Supported by 6th Generation, 7th Generation, and 8th Generation Intel® Core™
Processors, and 8th generation Intel® Core™ i3 Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-356 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:46 Reserved.
Register Address: 1FBH, 507 MSR_PRMRR_VALID_CONFIG
Valid PRMRR Configurations (R/W) Core
0 1M supported MEE size.
4:1 Reserved.
5 32M supported MEE size.
6 64M supported MEE size.
7 128M supported MEE size.
31:8 Reserved.
Register Address: 2F4H, 756 MSR_UNCORE_PRMRR_PHYS_BASE
1
(R/W)
The PRMRR range is used to protect the processor reserved memory from unauthorized reads and writes. Any IO
access to this range is aborted. This register controls the location of the PRMRR range by indicating its starting
address. It functions in tandem with the PRMRR mask register.
Package
11:0 Reserved.
PAWIDTH-1:12 Range Base
This field corresponds to bits PAWIDTH-1:12 of the base address memory
range which is allocated to PRMRR memory.
63:PAWIDTH Reserved.
Register Address: 2F5H, 757 MSR_UNCORE_PRMRR_PHYS_MASK
1
(R/W)
This register controls the size of the PRMRR range by indicating which address bits must match the PRMRR base
register value.
Package
9:0 Reserved.
10 Lock
Setting this bit locks all writeable settings in this register, including itself.
11 Range_En
Indicates whether the PRMRR range is enabled and valid.
38:12 Range_Mask
This field indicates which address bits must match PRMRR base in order
to qualify as an PRMRR access.
63:39 Reserved.
Register Address: 620H, 1568 MSR_RING_RATIO_LIMIT
Ring Ratio Limit (R/W)
This register provides Min/Max Ratio Limits for the LLC and Ring.
Package
6:0 MAX_Ratio
This field is used to limit the max ratio of the LLC/Ring.
7 Reserved.
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-357
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.2 MSRs Specific to 8th Generation Intel® Core™ i3 Processors
Table 2-42 lists additional MSRs for 8th generation Intel Core i3 processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_66H. For an MSR listed in Table 2-42 that also appears in the model-
specific tables of prior generations, Table 2-42 supersede prior generation tables.
14:8 MIN_Ratio
Writing to this field controls the minimum possible ratio of the LLC/Ring.
63:15 Reserved.
NOTES:
1. This MSR is specific to 7th generation and 8th generation Intel® Core™ processors.
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Thread
0Lock (R/WL)
1 Enable VMX Inside SMX Operation (R/WL)
2 Enable VMX Outside SMX Operation (R/WL)
14:8 SENTER Local Functions Enables (R/WL)
15 SENTER Global Functions Enable (R/WL)
17 SGX Launch Control Enable (R/WL)
This bit must be set to enable runtime reconfiguration of SGX Launch
Control via IA32_SGXLEPUBKEYHASHn MSR.
Available only if CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
18 SGX Global Functions Enable (R/WL)
63:21 Reserved.
Register Address: 350H, 848 MSR_BR_DETECT_CTRL
Branch Monitoring Global Control (R/W)
0 EnMonitoring
Global enable for branch monitoring.
1EnExcept
Enable branch monitoring event signaling on threshold trip.
The branch monitoring event handler is signaled via the existing PMI
signaling mechanism as programmed from the corresponding local APIC
LVT entry.
Table 2-41. Additional MSRs Supported by the 7th Generation and 8th Generation Intel® Core™ Processors Based
on Kaby Lake Microarchitecture and Coffee Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-358 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2EnLBRFrz
Enable LBR freeze on threshold trip. This will cause the LBR frozen bit
58 to be set in IA32_PERF_GLOBAL_STATUS when a triggering
condition occurs and this bit is enabled.
3DisableInGuest
When set to ‘1’, branch monitoring, event triggering and LBR freeze
actions are disabled when operating at VMX non-root operation.
7:4 Reserved.
17:8 WindowSize
Window size defined by WindowCntSel. Values 0 – 1023 are supported.
Once the Window counter reaches the WindowSize count both the
Window Counter and all Branch Monitoring Counters are cleared.
23:18 Reserved.
25:24 WindowCntSel
Window event count select:
‘00 = Instructions retired.
‘01 = Branch instructions retired
‘10 = Return instructions retired.
‘11 = Indirect branch instructions retired.
26 CntAndMode
When set to ‘1’, the overall branch monitoring event triggering
condition is true only if all enabled counters’ threshold conditions are
true.
When ‘0’, the threshold tripping condition is true if any enabled
counters’ threshold is true.
63:27 Reserved.
Register Address: 351H, 849 MSR_BR_DETECT_STATUS
Branch Monitoring Global Status (R/W)
0 Branch Monitoring Event Signaled
When set to '1', Branch Monitoring event signaling is blocked until this
bit is cleared by software.
1LBRsValid
This status bit is set to ‘1’ if the LBR state is considered valid for
sampling by branch monitoring software.
7:2 Reserved.
8CntrHit0
Branch monitoring counter #0 threshold hit. This status bit is sticky
and once set requires clearing by software. Counter operation
continues independent of the state of the bit.
9CntrHit1
Branch monitoring counter #1 threshold hit. This status bit is sticky
and once set requires clearing by software. Counter operation
continues independent of the state of the bit.
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-359
MODEL-SPECIFIC REGISTERS (MSRS)
15:10 Reserved.
Reserved for additional branch monitoring counters threshold hit
status.
25:16 CountWindow
The current value of the window counter. The count value is frozen on
a valid branch monitoring triggering condition. This is a 10-bit unsigned
value.
31:26 Reserved.
Reserved for future extension of CountWindow.
39:32 Count0
The current value of counter 0 updated after each occurrence of the
event being counted. The count value is frozen on a valid branch
monitoring triggering condition (in which case CntrHit0 will also be set).
This is an 8-bit signed value (2’s complement).
Heuristic events which only increment will saturate and freeze at
maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value 0x7F (+127) and
minimum value 0x80 (-128).
47:40 Count1
The current value of counter 1 updated after each occurrence of the
event being counted. The count value is frozen on a valid branch
monitoring triggering condition (in which case CntrHit1 will also be set).
This is an 8-bit signed value (2’s complement).
Heuristic events which only increment will saturate and freeze at
maximum value 0xFF (256).
RET-CALL event counter saturate at maximum value 0x7F (+127) and
minimum value 0x80 (-128).
63:48 Reserved.
Register Address: 354H−355H, 852−853 MSR_BR_DETECT_COUNTER_CONFIG_i
Branch Monitoring Detect Counter Configuration (R/W)
0CntrEn
Enable counter.
7:1 CntrEvSel
Event select (other values #GP)
‘0000000 = RETs.
‘0000001 = RET-CALL bias.
‘0000010 = RET mispredicts.
‘0000011 = Branch (all) mispredicts.
‘0000100 = Indirect branch mispredicts.
‘0000101 = Far branch instructions.
14:8 CntrThreshold
Threshold (an unsigned value of 0 to 127 supported). The value 0 of
counter threshold will result in event signaled after every instruction.
#GP if threshold is < 2.
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-360 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_66H.
15 MispredEventCnt
Mispredict events counting behavior:
‘0 = Mispredict events are counted in a window.
‘1 = Mispredict events are counted based on a consecutive occurrence.
CntrThreshold is treated as # of consecutive mispredicts. This control
bit only applies to events specified by CntrEvSel that involve a
prediction (0000010, 0000011, 0000100). Setting this bit for other
events is ignored.
63:16 Reserved.
Register Address: 3F8H, 1016 MSR_PKG_C3_RESIDENCY
Package C3 Residency Counter (R/O) Package
63:0 Note: C-state values are processor specific C-state code names,
unrelated to MWAIT extension C-state parameters or ACPI C-states.
Register Address: 620H, 1568 MSR_RING_RATIO_LIMIT
Ring Ratio Limit (R/W)
This register provides Min/Max Ratio Limits for the LLC and Ring.
Package
6:0 MAX_Ratio
This field is used to limit the max ratio of the LLC/Ring.
7 Reserved.
14:8 MIN_Ratio
Writing to this field controls the minimum possible ratio of the
LLC/Ring.
63:15 Reserved.
Register Address: 660H, 1632 MSR_CORE_C1_RESIDENCY
Core C1 Residency Counter (R/O) Core
63:0 Value since last reset for the Core C1 residency. Counter rate is the
Max Non-Turbo frequency (same as TSC). This counter counts in case
both of the core's threads are in an idle state and at least one of the
core's thread residency is in a C1 state or in one of its sub states. The
counter is updated only after a core C state exit. Note: Always reads 0
if core C1 is unsupported. A value of zero indicates that this processor
does not support core C1 or never entered core C1 level state.
Register Address: 662H, 1634 MSR_CORE_C3_RESIDENCY
Core C3 Residency Counter (R/O) Core
63:0 Will always return 0.
Table 2-42. Additional MSRs Supported by the 8th Generation Intel® Core™ i3 Processors
Based on Cannon Lake Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-361
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 394H, 916 MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W) Package
19:0 Reserved.
20 Enable overflow propagation.
21 Reserved
22 Enable counting.
63:23 Reserved.
Register Address: 395H, 917 MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter Package
47:0 Current count.
63:48 Reserved.
Register Address: 396H, 918 MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O) Package
3:0 Report the number of C-Box units with performance counters, including
processor cores and processor graphics.
63:4 Reserved.
Register Address: 3B0H, 946 MSR_UNC_ARB_PERFCTR0
Uncore Arb Unit, Performance Counter 0 Package
Register Address: 3B1H, 947 MSR_UNC_ARB_PERFCTR1
Uncore Arb Unit, Performance Counter 1 Package
Register Address: 3B2H, 944 MSR_UNC_ARB_PERFEVTSEL0
Uncore Arb Unit, Counter 0 Event Select MSR Package
Register Address: 3B3H, 945 MSR_UNC_ARB_PERFEVTSEL1
Uncore Arb unit, Counter 1 Event Select MSR Package
Register Address: 700H, 1792 MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR Package
Register Address: 701H, 1793 MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR Package
Register Address: 702H, 1794 MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0 Package
Register Address: 703H, 1795 MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1 Package
Register Address: 708H, 1800 MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR Package
Register Address: 709H, 1801 MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR Package
Register Address: 70AH, 1802 MSR_UNC_CBO_1_PERFCTR0
2-362 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 1, Performance Counter 0 Package
Register Address: 70BH, 1803 MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1 Package
Register Address: 710H, 1808 MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR Package
Register Address: 711H, 1809 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR Package
Register Address: 712H, 1810 MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0 Package
Register Address: 713H, 1811 MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1 Package
Register Address: 718H, 1816 MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR Package
Register Address: 719H, 1817 MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR Package
Register Address: 71AH, 1818 MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0 Package
Register Address: 71BH, 1819 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 Package
Register Address: 720H, 1824 MSR_UNC_CBO_4_PERFEVTSEL0
Uncore C-Box 4, Counter 0 Event Select MSR Package
Register Address: 721H, 1825 MSR_UNC_CBO_4_PERFEVTSEL1
Uncore C-Box 4, Counter 1 Event Select MSR Package
Register Address: 722H, 1826 MSR_UNC_CBO_4_PERFCTR0
Uncore C-Box 4, Performance Counter 0 Package
Register Address: 723H, 1827 MSR_UNC_CBO_4_PERFCTR1
Uncore C-Box 4, Performance Counter 1 Package
Register Address: 728H, 1832 MSR_UNC_CBO_5_PERFEVTSEL0
Uncore C-Box 5, Counter 0 Event Select MSR Package
Register Address: 729H, 1833 MSR_UNC_CBO_5_PERFEVTSEL1
Uncore C-Box 5, Counter 1 Event Select MSR Package
Register Address: 72AH, 1834 MSR_UNC_CBO_5_PERFCTR0
Uncore C-Box 5, Performance Counter 0 Package
Register Address: 72BH, 1835 MSR_UNC_CBO_5_PERFCTR1
Uncore C-Box 5, Performance Counter 1 Package
Register Address: 730H, 1840 MSR_UNC_CBO_6_PERFEVTSEL0
Uncore C-Box 6, Counter 0 Event Select MSR Package
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-363
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.3 MSRs Introduced in 10th Generation Intel® Core™ Processors
Table 2-44 lists additional MSRs for 10th generation Intel Core processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_7DH or 06_7EH. For an MSR listed in Table 2-44 that also appears in the
model-specific tables of prior generations, Table 2-44 supersede prior generation tables.
Register Address: 731H, 1841 MSR_UNC_CBO_6_PERFEVTSEL1
Uncore C-Box 6, Counter 1 Event Select MSR Package
Register Address: 732H, 1842 MSR_UNC_CBO_6_PERFCTR0
Uncore C-Box 6, Performance Counter 0 Package
Register Address: 733H, 1843 MSR_UNC_CBO_6_PERFCTR1
Uncore C-Box 6, Performance Counter 1 Package
Register Address: 738H, 1848 MSR_UNC_CBO_7_PERFEVTSEL0
Uncore C-Box 7, Counter 0 Event Select MSR Package
Register Address: 739H, 1849 MSR_UNC_CBO_7_PERFEVTSEL1
Uncore C-Box 7, Counter 1 Event Select MSR Package
Register Address: 73AH, 1850 MSR_UNC_CBO_7_PERFCTR0
Uncore C-Box 7, Performance Counter 0 Package
Register Address: 73BH, 1851 MSR_UNC_CBO_7_PERFCTR1
Uncore C-Box 7, Performance Counter 1 Package
Register Address: E01H, 3585 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4Slice 4select.
18:5 Reserved.
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved.
Register Address: E02H, 3586 MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status Package
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved.
3 A CBox counter overflowed (on any slice).
63:4 Reserved.
Table 2-43. Uncore PMU MSRs Supported by Intel® Core™ Processors Based on Cannon Lake Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
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MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 33H, 51 MSR_MEMORY_CTRL
Memory Control Register Core
28:0 Reserved.
29 SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30 Reserved.
31 Reserved.
Register Address: 48H, 72 IA32_SPEC_CTRL
See Table 2-2. Core
Register Address: 49H, 73 IA32_PREDICT_CMD
See Table 2-2. Thread
Register Address: 8CH, 140 IA32_SGXLEPUBKEYHASH0
See Table 2-2. Thread
Register Address: 8DH, 141 IA32_SGXLEPUBKEYHASH1
See Table 2-2. Thread
Register Address: 8EH, 142 IA32_SGXLEPUBKEYHASH2
See Table 2-2. Thread
Register Address: 8FH, 143 IA32_SGXLEPUBKEYHASH3
See Table 2-2. Thread
Register Address: A0H, 160 MSR_BIOS_MCU_ERRORCODE
BIOS MCU ERRORCODE (R/O)
This MSR indicates if WRMSR 0x79 failed to configure PRM memory and gives a hint to debug BIOS.
Package
15:0 Error Codes (R/O) Package
30:16 Reserved.
31 MCU Partial Success (R/O)
When set to 1, WRMSR 0x79 skipped part of the functionality during
BIOS.
Thread
Register Address: A5H, 165 MSR_FIT_BIOS_ERROR
FIT BIOS ERROR (R/W)
Report error codes for debug in case the processor failed to parse the Firmware Table in BIOS.
Can also be used to log BIOS information.
Thread
7:0 Error Codes (R/W)
Error codes for debug.
15:8 Entry Type (R/W)
Failed FIT entry type.
16 FIT MCU Entry (R/W)
FIT contains MCU entry.
Vol. 4 2-365
MODEL-SPECIFIC REGISTERS (MSRS)
62:17 Reserved.
63 LOCK (R/W)
When set to 1, writes to this MSR will be skipped.
Register Address: 10BH, 267 IA32_FLUSH_CMD
See Table 2-2. Thread
Register Address: 151H, 337 MSR_BIOS_DONE
BIOS Done (R/WO) Thread
0 BIOS Done Indication (R/WO)
Set by BIOS when it finishes programming the processor and wants to
lock the memory configuration from changes by software that is running
on this thread.
Writes to the bit will be ignored if EAX[0] is 0.
Thread
1Package BIOS Done Indication (R/O)
When set to 1, all threads in the package have bit 0 of this MSR set.
Package
31:2 Reserved.
Register Address: 1F1H, 497 MSR_CRASHLOG_CONTROL
Write Data to a Crash Log Configuration Thread
0 CDDIS: CrashDump_Disable
If set, indicates that Crash Dump is disabled.
63:1 Reserved.
Register Address: 2A0H, 672 MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W) Core
2:0 MEMTYPE: PRMRR BASE Memory Type.
3 CONFIGURED: PRMRR BASE Configured.
11:4 Reserved.
51:12 BASE: PRMRR Base Address.
63:52 Reserved.
Register Address: 30CH, 780 IA32_FIXED_CTR3
Fixed-Function Performance Counter Register 3 (R/W)
Bit definitions are the same as found in IA32_FIXED_CTR0, offset 309H. See Table 2-2.
Thread
Register Address: 329H, 809 MSR_PERF_METRICS
Performance Metrics (R/W)
Reports metrics directly. Software can check (and/or expose to its guests) the availability of PERF_METRICS feature
using IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE (bit 15).
Thread
7:0 Retiring. Percent of utilized slots by uops that eventually retire (commit).
15:8 Bad Speculation. Percent of wasted slots due to incorrect speculation,
covering utilized by uops that do not retire, or recovery bubbles
(unutilized slots).
23:16 Frontend Bound. Percent of unutilized slots where front-end did not
deliver a uop while back-end is ready.
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
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MODEL-SPECIFIC REGISTERS (MSRS)
31:24 Backend Bound. Percent of unutilized slots where a uop was not delivered
to back-end due to lack of back-end resources.
63:32 Reserved.
Register Address: 3F2H, 1010 MSR_PEBS_DATA_CFG
PEBS Data Configuration (R/W)
Provides software the capability to select data groups of interest and thus reduce the record size in memory and
record generation latency. Hence, a PEBS record's size and layout vary based on the selected groups. The MSR also
allows software to select LBR depth for branch data records.
Thread
0 Memory Info.
Setting this bit will capture memory information such as the linear
address, data source and latency of the memory access in the PEBS
record.
1GPRs.
Setting this bit will capture the contents of the General Purpose registers
in the PEBS record.
2XMMs.
Setting this bit will capture the contents of the XMM registers in the PEBS
record.
3LBRs.
Setting this bit will capture LBR TO, FROM, and INFO in the PEBS record.
23:4 Reserved.
31:24 LBR Entries.
Set the field to the desired number of entries - 1. For example, if the
LBR_entries field is 0, a single entry will be included in the record. To
include 32 LBR entries, set the LBR_entries field to 31 (0x1F). To ensure
all PEBS records are 16-byte aligned, software can use LBR_entries that
is multiple of 3.
Register Address: 541H, 1345 MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W) Core
0 L1 Scrubbing Enable
When set to 1, enable L1 scrubbing.
31:1 Reserved.
Register Address: 657H, 1623 MSR_FAST_UNCORE_MSRS_CTL
Fast WRMSR/RDMSR Control MSR (R/W) Thread
3:0 FAST_ACCESS_ENABLE:
Bit 0: When set to '1', provides a hint for the hardware to enable fast
access mode for the IA32_HWP_REQUEST MSR.
This bit is sticky and is cleaned by the hardware only during reset time.
This bit is valid only if FAST_UNCORE_MSRS_CAPABILITY[0] is set. Setting
this bit will cause CPUID[6].EAX[18] to be set.
31:4 Reserved.
Register Address: 65EH, 1630 MSR_FAST_UNCORE_MSRS_STATUS
Indication of Uncore MSRs, Post Write Activates Thread
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-367
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.4 MSRs Introduced in the 11th Generation Intel® Core™ Processors based on Tiger Lake
Microarchitecture
Table 2-45 lists additional MSRs for 11th generation Intel Core processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_8CH or 06_8DH. The MSRs listed in Table 2-44 are also supported by
these processors. For an MSR listed in Table 2-45 that also appears in the model-specific tables of prior genera-
tions, Table 2-45 supersedes prior generation tables.
0 Indicates whether the CPU is still in the middle of writing
IA32_HWP_REQUEST MSR, even after the WRMSR instruction has retired.
A value of 1 indicates the last write of IA32_HWP_REQUEST is still
ongoing.
A value of 0 indicates the last write of IA32_HWP_REQUEST is visible
outside the logical processor.
Software can use the status of this bit to avoid overwriting
IA32_HWP_REQUEST.
31:1 Reserved.
Register Address: 65FH, 1631 MSR_FAST_UNCORE_MSRS_CAPABILITY
Fast WRMSR/RDMSR Enumeration MSR (R/O) Thread
3:0 MSRS_CAPABILITY:
Bit 0: If set to ‘1’, hardware supports the fast access mode for the
IA32_HWP_REQUEST MSR.
31:4 Reserved.
Register Address: 772H, 1906 IA32_HWP_REQUEST_PKG
See Table 2-2. Package
Register Address: 775H, 1909 IA32_PECI_HWP_REQUEST_INFO
See Table 2-2. Thread
Register Address: 777H, 1911 IA32_HWP_STATUS
See Table 2-2. Thread
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: A0H, 160 MSR_BIOS_MCU_ERRORCODE
BIOS MCU ERRORCODE (R/O) Package
15:0 Error Codes
31:16 Reserved.
Register Address: A7H, 167 MSR_BIOS_DEBUG
BIOS DEBUG (R/O)
This MSR indicates if WRMSR 79H failed to configure PRM memory and gives a hint to debug BIOS.
Thread
30:0 Reserved.
Table 2-44. MSRs Supported by the 10th Generation Intel® Core™ Processors (Ice Lake Microarchitecture) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
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MODEL-SPECIFIC REGISTERS (MSRS)
31 MCU Partial Success
When set to 1, WRMSR 79H skipped part of the functionality during
BIOS.
63:32 Reserved.
Register Address: CFH, 207 IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/O)
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
Package
1:0 Reserved.
2 FUSA_SUPPORTED
3 RSM_IN_CPL0_ONLY
When set to 1, the RSM instruction is only allowed in CPL0 (#GP
triggered in any CPL != 0).
When set to 0, then any CPL may execute the RSM instruction.
4 Reserved.
5 SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL
(MSR address 33H).
31:6 Reserved.
Register Address: 492H, 1170 IA32_VMX_PROCBASED_CTLS3
IA32_VMX_PROCBASED_CTLS3
This MSR enumerates the allowed 1-settings of the third set of processor-based controls. Specifically, VM entry
allows bit X of the tertiary processor-based VM-execution controls to be 1 if and only if bit X of the MSR is set to 1.
If bit X of the MSR is cleared to 0, VM entry fails if control X and the “activate tertiary controls” primary processor-
based VM-execution control are both 1.
Core
0LOADIWKEY
This control determines whether executions of LOADIWKEY cause VM
exits.
63:1 Reserved.
Register Address: 601H, 1537 MSR_VR_CURRENT_CONFIG
Power Limit 4 (PL4)
Package-level maximum power limit (in Watts). It is a proactive, instantaneous limit.
Package
12:0 PL4 Value
PL4 value in 0.125 A increments. This field is locked by
VR_CURRENT_CONFIG[LOCK]. When the LOCK bit is set to 1b, this
field becomes Read Only.
30:13 Reserved.
31 Lock Indication (LOCK)
This bit will lock the CURRENT_LIMIT settings in this register and will
also lock this setting. This means that once set to 1b, the
CURRENT_LIMIT setting and this bit become Read Only until the next
Warm Reset.
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-369
MODEL-SPECIFIC REGISTERS (MSRS)
62:32 Not in use.
63 Reserved.
Register Address: 6A0H, 1696 IA32_U_CET
Configure User Mode CET (R/W)
See Table 2-2.
Register Address: 6A2H, 1698 IA32_S_CET
Configure Supervisor Mode CET (R/W)
See Table 2-2.
Register Address: 6A4H, 1700 IA32_PL0_SSP
Linear address to be loaded into SSP on transition to privilege level 0. (R/W)
See Table 2-2.
Register Address: 6A5H, 1701 IA32_PL1_SSP
Linear address to be loaded into SSP on transition to privilege level 1. (R/W)
See Table 2-2.
Register Address: 6A6H, 1702 IA32_PL2_SSP
Linear address to be loaded into SSP on transition to privilege level 2. (R/W)
See Table 2-2.
Register Address: 6A7H, 1703 IA32_PL3_SSP
Linear address to be loaded into SSP on transition to privilege level 3. (R/W)
See Table 2-2.
Register Address: 6A8H, 1704 IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when
not 0) from the interrupt gate descriptor. (R/W)
See Table 2-2.
Register Address: 981H, 2433 IA32_TME_CAPABILITY
See Table 2-2.
Register Address: 982H, 2434 IA32_TME_ACTIVATE
See Table 2-2.
Register Address: 983H, 2435 IA32_TME_EXCLUDE_MASK
See Table 2-2.
Register Address: 984H, 2436 IA32_TME_EXCLUDE_BASE
See Table 2-2.
Register Address: 990H, 2448 IA32_COPY_STATUS
1
See Table 2-2. Thread
Register Address: 991H, 2449 IA32_IWKEYBACKUP_STATUS
1
See Table 2-2. Platform
Register Address: C82H, 3202 IA32_L2_QOS_CFG
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-370 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.5 MSRs Introduced in the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture
Table 2-46 lists additional MSRs for 12th and 13th generation Intel Core processors with a CPUID Signature
DisplayFamily_DisplayModel value of 06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH. Table 2-47 lists the MSRs
unique to the processor P-core. Table 2-48 lists the MSRs unique to the processor E-core.
The MSRs listed in Table 2-44
1
and Table 2-45 are also supported by these processors. For an MSR listed in Table
2-46, Table 2-47, or Table 2-48 that also appears in the model-specific tables of prior generations, Table 2-46, Table
2-47, and Table 2-48 supersede prior generation tables.
IA32_CR_L2_QOS_CFG
This MSR provides software an enumeration of the parameters that L2 QoS (Intel RDT) support in any particular
implementation.
Core
0CDP_ENABLE
When set to 1, it will enable the code and data prioritization for the
L2 CAT/Intel RDT feature.
When set to 0, code and data prioritization is disabled for L2 CAT/Intel
RDT. See Chapter 18, “Debug, Branch Profile, TSC, and Intel® Resource
Director Technology (Intel® RDT) Features‚” for further details on CDP.
31:1 Reserved.
Register Address: D10H−D17H, 3220−3351 IA32_L2_QOS_MASK_[0-7]
IA32_CR_L2_QOS_MASK_[0-7]
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
Package
19:0 WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N is [0-
7]) to allocate to way X in the MLC. Ones are only allowed to be
written to ways that physically exist in the MLC
(CPUID.4.2:EBX[31:22] will indicate this).
Writing a 1 to a value beyond the highest way or a non-contiguous
set of 1s will cause a #GP on the WRMSR to this MSR.
31:20 Reserved.
Register Address: D91H, 3473 IA32_COPY_LOCAL_TO_PLATFORM
1
See Table 2-2. Thread
Register Address: D92H, 3474 IA32_COPY_PLATFORM_TO_LOCAL
1
See Table 2-2. Thread
NOTES:
1. Further details on Key Locker and usage of this MSR can be found here:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html
.
1. MSRs at the following addresses are not supported in the 12th and 13th generation Intel Core processor E-core: 30CH, 329H, 541H,
and 657H. The MSR at address 657H is not supported in the 12th and 13th generation Intel Core processor P-core.
Table 2-45. Additional MSRs Supported by the 11th Generation Intel® Core™ Processors Based on Tiger Lake
Microarchitecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-371
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 33H, 51 MSR_MEMORY_CTRL
Memory Control Register Core
26:0 Reserved.
27 UC_STORE_THROTTLE
If set to 1, when enabled, the processor will only allow one in-
progress UC store at a time.
28 UC_LOCK_DISABLE
If set to 1, a UC lock will cause a #GP(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
29 SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
30 Reserved.
31 Reserved.
Register Address: BCH, 188 IA32_MISC_PACKAGE_CTLS
Power Filtering Control (R/W)
IA32_ARCH_CAPABILITIES[bit 10] enumerates support for this MSR.
See Table 2-2.
Package
Register Address: C7H, 199 IA32_PMC6
General Performance Counter 6 (R/W)
See Table 2-2.
Core
Register Address: C8H, 200 IA32_PMC7
General Performance Counter 7 (R/W)
See Table 2-2.
Core
Register Address: CFH, 207 IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/O)
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
Package
0 STLB_QOS_SUPPORTED
When set to 1, the STLB QoS feature is supported and the STLB
QoS MSRs (1A8FH -1A97H) are accessible. When set to 0, access
to these MSRs will #GP.
1 Reserved.
2 FUSA_SUPPORTED
3 RSM_IN_CPL0_ONLY
When set to 1, the RSM instruction is only allowed in CPL0 (#GP
triggered in any CPL != 0).
When set to 0, then any CPL may execute the RSM instruction.
2-372 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
4 UC_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 28 of MSR_MEMORY_CTRL
(MSR address 33H).
5 SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL.
6 SNOOP_FILTER_QOS_SUPPORTED
When set to 1, the Snoop Filter Qos Mask MSRs are supported.
When set to 0, access to these MSRs will #GP.
7 UC_STORE_THROTTLING_SUPPORTED
When set 1, UC Store throttle capability exist through
MSR_MEMORY_CTRL (33H) bit 27.
31:8 Reserved.
Register Address: E1H, 225 IA32_UMWAIT_CONTROL
UMWAIT Control (R/W)
See Table 2-2.
Register Address: 10AH, 266 IA32_ARCH_CAPABILITIES
Enumeration of Architectural Features (R/O)
See Table 2-2.
Register Address: 18CH, 396 IA32_PERFEVTSEL6
See Table 2-20. Core
Register Address: 18DH, 397 IA32_PERFEVTSEL7
See Table 2-20. Core
Register Address: 195H, 405 IA32_OVERCLOCKING_STATUS
Overclocking Status (R/O)
IA32_ARCH_CAPABILITIES[bit 23] enumerates support for this MSR. See Table 2-2.
Package
Register Address: 1ADH, 429 MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turbo Ratio Limit (R/W)
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each
group. Maximum ratio for groups with more cores must decrease monotonically.
Package
7:0 MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8 MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16 MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24 MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32 MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-373
MODEL-SPECIFIC REGISTERS (MSRS)
47:40 MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48 MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56 MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 493H, 1171 IA32_VMX_EXIT_CTLS2
See Table 2-2.
Register Address: 4C7H, 1223 IA32_A_PMC6
Full Width Writable IA32_PMC6 Alias (R/W)
See Table 2-2.
Register Address: 4C8H, 1224 IA32_A_PMC7
Full Width Writable IA32_PMC7 Alias (R/W)
See Table 2-2.
Register Address: 650H, 1616 MSR_SECONDARY_TURBO_RATIO_LIMIT
Secondary Maximum Turbo Ratio Limit (R/W)
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.
Specifies Maximum Ratio Limit for each group. Maximum ratio for groups with more cores must decrease
monotonically.
Package
7:0 MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8 MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16 MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24 MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32 MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40 MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48 MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56 MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 664H, 1636 MSR_MC6_RESIDENCY_COUNTER
Module C6 Residency Counter (R/0)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-States.
Module
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-374 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-47 are unique to the 12th and 13th generation Intel Core processor P-core. These MSRs
are not supported on the processor E-core.
63:0 Time that this module is in module-specific C6 states since last
reset. Counts at 1 Mhz frequency.
Register Address: 6E1H, 1761 IA32_PKRS
Specifies the PK permissions associated with each protection domain for supervisor pages (R/W)
See Table 2-2.
Register Address: 776H, 1910 IA32_HWP_CTL
See Table 2-2.
Register Address: 981H, 2433 IA32_TME_CAPABILITY
Memory Encryption Capability MSR
See Table 2-2.
Register Address: 1200H−121FH, 4608−4639 IA32_LBR_x_INFO
Last Branch Record Entry X Info Register (R/W)
See Table 2-2.
Register Address: 14CEH, 5326 IA32_LBR_CTL
Last Branch Record Enabling and Configuration Register (R/W)
See Table 2-2.
Register Address: 14CFH, 5327 IA32_LBR_DEPTH
Last Branch Record Maximum Stack Depth Register (R/W)
See Table 2-2.
Register Address: 1500H−151FH, 5376−5407 IA32_LBR_x_FROM_IP
Last Branch Record Entry X Source IP Register (R/W)
See Table 2-2.
Register Address: 1600H−161FH, 5632−5663 IA32_LBR_x_TO_IP
Last Branch Record Entry X Destination IP Register (R/W)
See Table 2-2.
Register Address: 17D2H, 6098 IA32_THREAD_FEEDBACK_CHAR
Thread Feedback Characteristics (R/O)
See Table 2-2.
Register Address: 17D4H, 6100 IA32_HW_FEEDBACK_THREAD_CONFIG
Hardware Feedback Thread Configuration (R/W)
See Table 2-2.
Register Address: 17DAH, 6106 IA32_HRESET_ENABLE
History Reset Enable (R/W)
See Table 2-2.
Table 2-46. Additional MSRs Supported by the 12th and 13th Generation Intel® Core™ Processors Supporting
Performance Hybrid Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-375
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-47. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 1A4H, 420 MSR_PREFETCH_CONTROL
Prefetch Disable Bits (R/W)
0 L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches additional
lines of code or data into the L2 cache.
1 L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2 DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
3 DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses sequential
load history (based on instruction pointer of previous loads) to
determine whether to prefetch additional lines.
4 Reserved.
5AMP_PREFETCH_DISABLE
If 1, disables the L2 Adaptive Multipath Probability (AMP) prefetcher.
63:6 Reserved.
Register Address: 3F7H, 1015 MSR_PEBS_FRONTEND
FrontEnd Precise Event Condition Select (R/W)
See Table 2-39.
Thread
Register Address: 540H, 1344 MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W) Thread
0 WB_MEM_STRM_LD_DISABLE
Disable streaming behavior for MOVNTDQA loads to WB memory
type. If set, these accesses will be treated like regular cacheable
loads (Data will be cached).
63:1 Reserved.
Register Address: 541H, 1345 MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
See Table 2-44.
Core
Register Address: D10H−D17H, 3220−3351 IA32_L2_QOS_MASK_[0-7]
IA32_CR_L2_QOS_MASK_[0-7]
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
Core
2-376 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-48 are unique to the 12th and 13th generation Intel Core processor E-core. These MSRs
are not supported on the processor P-core.
Table 2-49 lists the MSRs of uncore PMU for Intel processors with a CPUID Signature DisplayFamily_DisplayModel
value of 06_97H, 06_9AH, 06_BAH, 06_B7H, or 06_BFH.
19:0 WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N is [0-
7]) to allocate to way X in the MLC. Ones are only allowed to be
written to ways that physically exist in the MLC
(CPUID.4.2:EBX[31:22] will indicate this).
Writing a 1 to a value beyond the highest way or a non-contiguous
set of 1s will cause a #GP on the WRMSR to this MSR.
31:20 Reserved.
Table 2-48. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor E-core
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: D10H−D1FH, 3220−3359 IA32_L2_QOS_MASK_[0-15]
IA32_CR_L2_QOS_MASK_[0-15]
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
Module
19:0 WAYS_MASK
Setting a 1 in this bit X allows threads with CLOS <n> (where N
is [0-7]) to allocate to way X in the MLC. Ones are only allowed to
be written to ways that physically exist in the MLC
(CPUID.4.2:EBX[31:22] will indicate this).
Writing a 1 to a value beyond the highest way or a non-
contiguous set of 1s will cause a #GP on the WRMSR to this MSR.
31:20 Reserved.
Register Address: 1309H−130BH, 4873
−4875
MSR_RELOAD_FIXED_CTRx
Reload value for IA32_FIXED_CTRx (R/W)
47:0 Value loaded into IA32_FIXED_CTRx when a PEBS record is
generated while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT =
01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
63:48 Reserved.
Register Address: 14C1H−14C6H, 5313 −5318 MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W) Core
47:0 Value loaded into IA32_PMCx when a PEBS record is generated
while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in
IA32_PEBS_ENABLE, and PMCx is overflowed.
63:48 Reserved.
Table 2-47. MSRs Supported by 12th and 13th Generation Intel® Core™ Processor P-core
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-377
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 396H, 918 MSR_UNC_CBO_CONFIG
Uncore C-Box Configuration Information (R/O) Package
3:0 Specifies the number of C-Box units with programmable counters
(including processor cores and processor graphics).
63:4 Reserved.
Register Address: 2000H, 8192 MSR_UNC_CBO_0_PERFEVTSEL0
Uncore C-Box 0, Counter 0 Event Select MSR Package
Register Address: 2001H, 8193 MSR_UNC_CBO_0_PERFEVTSEL1
Uncore C-Box 0, Counter 1 Event Select MSR Package
Register Address: 2002H, 8194 MSR_UNC_CBO_0_PERFCTR0
Uncore C-Box 0, Performance Counter 0 Package
Register Address: 2003H, 8195 MSR_UNC_CBO_0_PERFCTR1
Uncore C-Box 0, Performance Counter 1 Package
Register Address: 2008H, 8200 MSR_UNC_CBO_1_PERFEVTSEL0
Uncore C-Box 1, Counter 0 Event Select MSR Package
Register Address: 2009H, 8201 MSR_UNC_CBO_1_PERFEVTSEL1
Uncore C-Box 1, Counter 1 Event Select MSR Package
Register Address: 200AH, 8202 MSR_UNC_CBO_1_PERFCTR0
Uncore C-Box 1, Performance Counter 0 Package
Register Address: 200BH, 8203 MSR_UNC_CBO_1_PERFCTR1
Uncore C-Box 1, Performance Counter 1 Package
Register Address: 2010H, 8208 MSR_UNC_CBO_2_PERFEVTSEL0
Uncore C-Box 2, Counter 0 Event Select MSR Package
Register Address: 2011H, 8209 MSR_UNC_CBO_2_PERFEVTSEL1
Uncore C-Box 2, Counter 1 Event Select MSR Package
Register Address: 2012H, 8210 MSR_UNC_CBO_2_PERFCTR0
Uncore C-Box 2, Performance Counter 0 Package
Register Address: 2013H, 8211 MSR_UNC_CBO_2_PERFCTR1
Uncore C-Box 2, Performance Counter 1 Package
Register Address: 2018H, 8216 MSR_UNC_CBO_3_PERFEVTSEL0
Uncore C-Box 3, Counter 0 Event Select MSR Package
Register Address: 2019H, 8217 MSR_UNC_CBO_3_PERFEVTSEL1
Uncore C-Box 3, Counter 1 Event Select MSR Package
Register Address: 201AH, 8218 MSR_UNC_CBO_3_PERFCTR0
Uncore C-Box 3, Performance Counter 0 Package
Register Address: 201BH, 8219 MSR_UNC_CBO_3_PERFCTR1
Uncore C-Box 3, Performance Counter 1 Package
2-378 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 2020H, 8224 MSR_UNC_CBO_4_PERFEVTSEL0
Uncore C-Box 4, Counter 0 Event Select MSR Package
Register Address: 2021H, 8225 MSR_UNC_CBO_4_PERFEVTSEL1
Uncore C-Box 4, Counter 1 Event Select MSR Package
Register Address: 2022H, 8226 MSR_UNC_CBO_4_PERFCTR0
Uncore C-Box 4, Performance Counter 0 Package
Register Address: 2023H, 8227 MSR_UNC_CBO_4_PERFCTR1
Uncore C-Box 4, Performance Counter 1 Package
Register Address: 2028H, 8232 MSR_UNC_CBO_5_PERFEVTSEL0
Uncore C-Box 5, Counter 0 Event Select MSR Package
Register Address: 2029H, 8233 MSR_UNC_CBO_5_PERFEVTSEL1
Uncore C-Box 5, Counter 1 Event Select MSR Package
Register Address: 202AH, 8234 MSR_UNC_CBO_5_PERFCTR0
Uncore C-Box 5, Performance Counter 0 Package
Register Address: 202BH, 8235 MSR_UNC_CBO_5_PERFCTR1
Uncore C-Box 5, Performance Counter 1 Package
Register Address: 2030H, 8240 MSR_UNC_CBO_6_PERFEVTSEL0
Uncore C-Box 6, Counter 0 Event Select MSR Package
Register Address: 2031H, 8241 MSR_UNC_CBO_6_PERFEVTSEL1
Uncore C-Box 6, Counter 1 Event Select MSR Package
Register Address: 2032H, 8242 MSR_UNC_CBO_6_PERFCTR0
Uncore C-Box 6, Performance Counter 0 Package
Register Address: 2033H, 8243 MSR_UNC_CBO_6_PERFCTR1
Uncore C-Box 6, Performance Counter 1 Package
Register Address: 2038H, 8248 MSR_UNC_CBO_7_PERFEVTSEL0
Uncore C-Box 7, Counter 0 Event Select MSR Package
Register Address: 2039H, 8249 MSR_UNC_CBO_7_PERFEVTSEL1
Uncore C-Box 7, Counter 1 Event Select MSR Package
Register Address: 203AH, 8250 MSR_UNC_CBO_7_PERFCTR0
Uncore C-Box 7, Performance Counter 0 Package
Register Address: 203BH, 8251 MSR_UNC_CBO_7_PERFCTR1
Uncore C-Box 7, Performance Counter 1 Package
Register Address: 2040H, 8256 MSR_UNC_CBO_8_PERFEVTSEL0
Uncore C-Box 8, Counter 0 Event Select MSR Package
Register Address: 2041H, 8257 MSR_UNC_CBO_8_PERFEVTSEL1
Uncore C-Box 8, Counter 1 Event Select MSR Package
Register Address: 2042H, 8258 MSR_UNC_CBO_8_PERFCTR0
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-379
MODEL-SPECIFIC REGISTERS (MSRS)
Uncore C-Box 8, Performance Counter 0 Package
Register Address: 2043H, 8259 MSR_UNC_CBO_8_PERFCTR1
Uncore C-Box 8, Performance Counter 1 Package
Register Address: 2048H, 8264 MSR_UNC_CBO_9_PERFEVTSEL0
Uncore C-Box 9, Counter 0 Event Select MSR Package
Register Address: 2049H, 8265 MSR_UNC_CBO_9_PERFEVTSEL1
Uncore C-Box 9, Counter 1 Event Select MSR Package
Register Address: 204AH, 8266 MSR_UNC_CBO_9_PERFCTR0
Uncore C-Box 9, Performance Counter 0 Package
Register Address: 204BH, 8267 MSR_UNC_CBO_9_PERFCTR1
Uncore C-Box 9, Performance Counter 1 Package
Register Address: 2FD0H, 12240 MSR_UNC_ARB_0_PERFEVTSEL0
Uncore Arb Unit 0, Counter 0 Event Select MSR Package
Register Address: 2FD1H, 12241 MSR_UNC_ARB_0_PERFEVTSEL1
Uncore Arb Unit 0, Counter 1 Event Select MSR Package
Register Address: 2FD2H, 12242 MSR_UNC_ARB_0_PERFCTR0
Uncore Arb Unit 0, Performance Counter 0 Package
Register Address: 2FD3H, 12243 MSR_UNC_ARB_0_PERFCTR1
Uncore Arb Unit 0, Performance Counter 1 Package
Register Address: 2FD4H, 12244 MSR_UNC_ARB_0_PERF_STATUS
Uncore Arb Unit 0, Performance Status Package
Register Address: 2FD5H, 12245 MSR_UNC_ARB_0_PERF_CTRL
Uncore Arb Unit 0, Performance Control Package
Register Address: 2FD8H, 12248 MSR_UNC_ARB_1_PERFEVTSEL0
Uncore Arb Unit 1, Counter 0 Event Select MSR Package
Register Address: 2FD9H, 12249 MSR_UNC_ARB_1_PERFEVTSEL1
Uncore Arb Unit 1, Counter 1 Event Select MSR Package
Register Address: 2FDAH, 12250 MSR_UNC_ARB_1_PERFCTR0
Uncore Arb Unit 1, Performance Counter 0 Package
Register Address: 2FDBH, 12251 MSR_UNC_ARB_1_PERFCTR1
Uncore Arb Unit 1, Performance Counter 1 Package
Register Address: 2FDCH, 12252 MSR_UNC_ARB_1_PERF_STATUS
Uncore Arb Unit 1, Performance Status Package
Register Address: 2FDDH, 12253 MSR_UNC_ARB_1_PERF_CTRL
Uncore Arb Unit 1, Performance Control Package
Register Address: 2FDEH, 12254 MSR_UNC_PERF_FIXED_CTRL
Uncore Fixed Counter Control (R/W) Package
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-380 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.6 MSRs Introduced in the Intel® Xeon® Scalable Processor Family
The Intel
®
Xeon
®
Scalable Processor Family (CPUID Signature DisplayFamily_DisplayModel value of 06_55H)
supports the MSRs listed in Table 2-50.
19:0 Reserved.
20 Enable overflow propagation.
21 Reserved.
22 Enable counting.
63:23 Reserved.
Register Address: 2FDFH, 12255 MSR_UNC_PERF_FIXED_CTR
Uncore Fixed Counter Package
43:0 Current count.
63:44 Reserved.
Register Address: 2FF0H, 12272 MSR_UNC_PERF_GLOBAL_CTRL
Uncore PMU Global Control Package
0 Slice 0 select.
1 Slice 1 select.
2 Slice 2 select.
3 Slice 3 select.
4 Slice 4 select.
18:5 Reserved.
29 Enable all uncore counters.
30 Enable wake on PMI.
31 Enable Freezing counter when overflow.
63:32 Reserved.
Register Address: 2FF2H, 12274 MSR_UNC_PERF_GLOBAL_STATUS
Uncore PMU Main Status Package
0 Fixed counter overflowed.
1 An ARB counter overflowed.
2 Reserved.
3 A CBox counter overflowed (on any slice).
63:4 Reserved.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Table 2-49. Uncore PMU MSRs Supported by 12th and 13th Generation Intel® Core™ Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-381
MODEL-SPECIFIC REGISTERS (MSRS)
Control Features in Intel 64 Processor (R/W)
See Table 2-2.
Thread
0Lock (R/WL)
1 Enable VMX Inside SMX Operation (R/WL)
2 Enable VMX Outside SMX Operation (R/WL)
14:8 SENTER Local Functions Enables (R/WL)
15 SENTER Global Functions Enable (R/WL)
18 SGX Global Functions Enable (R/WL)
20 LMCE_ENABLED (R/WL)
63:21 Reserved.
Register Address: 4EH, 78 IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W) Package
0LockOut (R/WO)
See Table 2-2.
1Enable_PPIN (R/W)
See Table 2-2.
63:2 Reserved.
Register Address: 4FH, 79 IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O) Package
63:0 Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
See Table 2-26.
Package
22:16 Reserved.
23 PPIN_CAP (R/O)
See Table 2-26.
Package
27:24 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
See Table 2-26.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
See Table 2-26.
Package
30 Programmable TJ OFFSET (R/O)
See Table 2-26.
Package
39:31 Reserved.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-382 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
47:40 Maximum Efficiency Ratio (R/O)
See Table 2-26.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W)
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or
ACPI C-states. See http://biosbits.org.
Core
2:0 Package C-State Limit (R/W)
Specifies the lowest processor-specific C-state code name (consuming the
least power) for the package. The default is set as factory-configured
package C-state limit.
The following C-state code name encodings are supported:
000b: C0/C1 (no package C-state support)
001b: C2
010b: C6 (non-retention)
011b: C6 (retention)
111b: No Package C state limits. All C states supported by the processor
are available.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
14:11 Reserved.
15 CFG Lock (R/WO)
16 Automatic C-State Conversion Enable (R/W)
If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).
24:17 Reserved.
25 C3 State Auto Demotion Enable (R/W)
26 C1 State Auto Demotion Enable (R/W)
27 Enable C3 Undemotion (R/W)
28 Enable C1 Undemotion (R/W)
29 Package C State Demotion Enable (R/W)
30 Package C State Undemotion Enable (R/W)
63:31 Reserved.
Register Address: 179H, 377 IA32_MCG_CAP
Global Machine Check Capability (R/O) Thread
7:0 Count.
8 MCG_CTL_P
9MCG_EXT_P
10 MCP_CMCI_P
11 MCG_TES_P
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-383
MODEL-SPECIFIC REGISTERS (MSRS)
15:12 Reserved.
23:16 MCG_EXT_CNT
24 MCG_SER_P
25 MCG_EM_P
26 MCG_ELOG_P
63:27 Reserved.
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in SMM.
Thread
57:0 Reserved.
58 SMM_Code_Access_Chk (SMM-RO)
If set to 1 indicates that the SMM code access restriction is supported and
a host-space interface is available to SMM handler.
59 Long_Flow_Indication (SMM-RO)
If set to 1 indicates that the SMM long flow indicator is supported and a
host-space interface is available to SMM handler.
63:60 Reserved.
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Core
0 Thermal Status (R/O)
See Table 2-2.
1 Thermal Status Log (R/WC0)
See Table 2-2.
2 PROTCHOT # or FORCEPR# Status (R/O)
See Table 2-2.
3 PROTCHOT # or FORCEPR# Log (R/WC0)
See Table 2-2.
4 Critical Temperature Status (R/O)
See Table 2-2.
5 Critical Temperature Status Log (R/WC0)
See Table 2-2.
6 Thermal Threshold #1 Status (R/O)
See Table 2-2.
7 Thermal Threshold #1 Log (R/WC0)
See Table 2-2.
8 Thermal Threshold #2 Status (R/O)
See Table 2-2.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-384 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
9 Thermal Threshold #2 Log (R/WC0)
See Table 2-2.
10 Power Limitation Status (R/O)
See Table 2-2.
11 Power Limitation Log (R/WC0)
See Table 2-2.
12 Current Limit Status (R/O)
See Table 2-2.
13 Current Limit Log (R/WC0)
See Table 2-2.
14 Cross Domain Limit Status (R/O)
See Table 2-2.
15 Cross Domain Limit Log (R/WC0)
See Table 2-2.
22:16 Digital Readout (R/O)
See Table 2-2.
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O)
See Table 2-2.
31 Reading Valid (R/O)
See Table 2-2.
63:32 Reserved.
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Package
15:0 Reserved.
23:16 Temperature Target (R/O)
See Table 2-26.
27:24 TCC Activation Offset (R/W)
See Table 2-26.
63:28 Reserved.
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
This register defines the ratio limits. RATIO[0:7] must be populated in ascending order. RATIO[i+1] must be less than
or equal to RATIO[i]. Entries with RATIO[i] will be ignored. If any of the rules above are broken, the configuration is
silently rejected. If the programmed ratio is:
• Above the fused ratio for that core count, it will be clipped to the fuse limits (assuming !OC).
• Below the min supported ratio, it will be clipped.
Package
7:0 RATIO_0
Defines ratio limits.
15:8 RATIO_1
Defines ratio limits.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-385
MODEL-SPECIFIC REGISTERS (MSRS)
23:16 RATIO_2
Defines ratio limits.
31:24 RATIO_3
Defines ratio limits.
39:32 RATIO_4
Defines ratio limits.
47:40 RATIO_5
Defines ratio limits.
55:48 RATIO_6
Defines ratio limits.
63:56 RATIO_7
Defines ratio limits.
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT_CORES
This register defines the active core ranges for each frequency point. NUMCORE[0:7] must be populated in ascending
order. NUMCORE[i+1] must be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored. The last valid
entry must have NUMCORE >= the number of cores in the SKU. If any of the rules above are broken, the configuration
is silently rejected.
Package
7:0 NUMCORE_0
Defines the active core ranges for each frequency point.
15:8 NUMCORE_1
Defines the active core ranges for each frequency point.
23:16 NUMCORE_2
Defines the active core ranges for each frequency point.
31:24 NUMCORE_3
Defines the active core ranges for each frequency point.
39:32 NUMCORE_4
Defines the active core ranges for each frequency point.
47:40 NUMCORE_5
Defines the active core ranges for each frequency point.
55:48 NUMCORE_6
Defines the active core ranges for each frequency point.
63:56 NUMCORE_7
Defines the active core ranges for each frequency point.
Register Address: 280H, 640 IA32_MC0_CTL2
See Table 2-2. Core
Register Address: 281H, 641 IA32_MC1_CTL2
See Table 2-2. Core
Register Address: 282H, 642 IA32_MC2_CTL2
See Table 2-2. Core
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-386 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 283H, 643 IA32_MC3_CTL2
See Table 2-2. Core
Register Address: 284H, 644 IA32_MC4_CTL2
See Table 2-2. Package
Register Address: 285H, 645 IA32_MC5_CTL2
See Table 2-2. Package
Register Address: 286H, 646 IA32_MC6_CTL2
See Table 2-2. Package
Register Address: 287H, 647 IA32_MC7_CTL2
See Table 2-2. Package
Register Address: 288H, 648 IA32_MC8_CTL2
See Table 2-2. Package
Register Address: 289H, 649 IA32_MC9_CTL2
See Table 2-2. Package
Register Address: 28AH, 650 IA32_MC10_CTL2
See Table 2-2. Package
Register Address: 28BH, 651 IA32_MC11_CTL2
See Table 2-2. Package
Register Address: 28CH, 652 IA32_MC12_CTL2
See Table 2-2. Package
Register Address: 28DH, 653 IA32_MC13_CTL2
See Table 2-2. Package
Register Address: 28EH, 654 IA32_MC14_CTL2
See Table 2-2. Package
Register Address: 28FH, 655 IA32_MC15_CTL2
See Table 2-2. Package
Register Address: 290H, 656 IA32_MC16_CTL2
See Table 2-2. Package
Register Address: 291H, 657 IA32_MC17_CTL2
See Table 2-2. Package
Register Address: 292H, 658 IA32_MC18_CTL2
See Table 2-2. Package
Register Address: 293H, 659 IA32_MC19_CTL2
See Table 2-2. Package
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC0 reports MC errors from the IFU module.
Core
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-387
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC0 reports MC errors from the IFU module.
Core
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC0 reports MC errors from the IFU module.
Core
Register Address: 403H, 1027 IA32_MC0_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC0 reports MC errors from the IFU module.
Core
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC1 reports MC errors from the DCU module.
Core
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC1 reports MC errors from the DCU module.
Core
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC1 reports MC errors from the DCU module.
Core
Register Address: 407H, 1031 IA32_MC1_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC1 reports MC errors from the DCU module.
Core
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC2 reports MC errors from the DTLB module.
Core
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC2 reports MC errors from the DTLB module.
Core
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC2 reports MC errors from the DTLB module.
Core
Register Address: 40BH, 1035 IA32_MC2_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC2 reports MC errors from the DTLB module.
Core
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC3 reports MC errors from the MLC module.
Core
Register Address: 40DH, 1037 IA32_MC3_STATUS
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-388 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC3 reports MC errors from the MLC module.
Core
Register Address: 40EH, 1038 IA32_MC3_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC3 reports MC errors from the MLC module.
Core
Register Address: 40FH, 1039 IA32_MC3_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC3 reports MC errors from the MLC module.
Core
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
Package
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
Package
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
Package
Register Address: 413H, 1043 IA32_MC4_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
Package
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from a link interconnect module.
Package
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from a link interconnect module.
Package
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from a link interconnect module.
Package
Register Address: 417H, 1047 IA32_MC5_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC5 reports MC errors from a link interconnect module.
Package
Register Address: 418H, 1048 IA32_MC6_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 419H, 1049 IA32_MC6_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-389
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 41AH, 1050 IA32_MC6_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41BH, 1051 IA32_MC6_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC6 reports MC errors from the integrated I/O module.
Package
Register Address: 41CH, 1052 IA32_MC7_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the M2M 0.
Package
Register Address: 41DH, 1053 IA32_MC7_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the M2M 0.
Package
Register Address: 41EH, 1054 IA32_MC7_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the M2M 0.
Package
Register Address: 41FH, 1055 IA32_MC7_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC7 reports MC errors from the M2M 0.
Package
Register Address: 420H, 1056 IA32_MC8_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the M2M 1.
Package
Register Address: 421H, 1057 IA32_MC8_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the M2M 1.
Package
Register Address: 422H, 1058 IA32_MC8_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the M2M 1.
Package
Register Address: 423H, 1059 IA32_MC8_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC8 reports MC errors from the M2M 1.
Package
Register Address: 424H, 1060 IA32_MC9_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 425H, 1061 IA32_MC9_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 426H, 1062 IA32_MC9_ADDR
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-390 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 427H, 1063 IA32_MC9_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 428H, 1064 IA32_MC10_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 429H, 1065 IA32_MC10_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 42AH, 1066 IA32_MC10_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 42BH, 1067 IA32_MC10_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 42CH, 1068 IA32_MC11_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 42DH, 1069 IA32_MC11_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 42EH, 1070 IA32_MC11_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 42FH, 1071 IA32_MC11_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC9 - MC11 report MC errors from the CHA.
Package
Register Address: 430H, 1072 IA32_MC12_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC12 report MC errors from each channel of a link interconnect module.
Package
Register Address: 431H, 1073 IA32_MC12_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC12 report MC errors from each channel of a link interconnect module.
Package
Register Address: 432H, 1074 IA32_MC12_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC12 report MC errors from each channel of a link interconnect module.
Package
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-391
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 433H, 1075 IA32_MC12_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC12 report MC errors from each channel of a link interconnect module.
Package
Register Address: 434H, 1076 IA32_MC13_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 435H, 1077 IA32_MC13_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 436H, 1078 IA32_MC13_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 437H, 1079 IA32_MC13_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 438H, 1080 IA32_MC14_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 439H, 1081 IA32_MC14_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 43AH, 1082 IA32_MC14_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 43BH, 1083 IA32_MC14_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 43CH, 1084 IA32_MC15_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 43DH, 1085 IA32_MC15_STATUS
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 43EH, 1086 IA32_MC15_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 43FH, 1087 IA32_MC15_MISC
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-392 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 440H, 1088 IA32_MC16_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 441H, 1089 IA32_MC16_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 442H, 1090 IA32_MC16_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 443H, 1091 IA32_MC16_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 444H, 1092 IA32_MC17_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 445H, 1093 IA32_MC17_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 446H, 1094 IA32_MC17_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 447H, 1095 IA32_MC17_MISC
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 448H, 1096 IA32_MC18_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 449H, 1097 IA32_MC18_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 44AH, 1098 IA32_MC18_ADDR
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Register Address: 44BH, 1099 IA32_MC18_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Banks MC13 through MC 18 report MC errors from the integrated memory controllers.
Package
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-393
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 44CH, 1100 IA32_MC19_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a link interconnect module.
Package
Register Address: 44DH, 1101 IA32_MC19_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a link interconnect module.
Package
Register Address: 44EH, 1102 IA32_MC19_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a link interconnect module.
Package
Register Address: 44FH, 1103 IA32_MC19_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC19 reports MC errors from a link interconnect module.
Package
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O) Package
3:0 Power Units
See Section 15.10.1, “RAPL Interfaces.”
Package
7:4 Reserved. Package
12:8 Energy Status Units
Energy related information (in Joules) is based on the multiplier, 1/2^ESU;
where ESU is an unsigned integer represented by bits 12:8. Default value
is 0EH (or 61 micro-joules).
Package
15:13 Reserved. Package
19:16 Time Units
See Section 15.10.1, “RAPL Interfaces.”
Package
63:20 Reserved.
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Energy consumed by DRAM devices.
Package
31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32 Reserved.
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-394 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 620H, 1568 MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Out of reset, the min_ratio and max_ratio fields represent the widest possible range of uncore frequencies. Writing to
these fields allows software to control the minimum and the maximum frequency that hardware will select.
Package
63:15 Reserved.
14:8 MIN_RATIO
Writing to this field controls the minimum possible ratio of the LLC/Ring.
7 Reserved.
6:0 MAX_RATIO
This field is used to limit the max ratio of the LLC/Ring.
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
Reserved (R/O)
Reads return 0.
Package
Register Address: C8DH, 3213 IA32_QM_EVTSEL
Monitoring Event Select Register (R/W)
If CPUID.(EAX=07H, ECX=0):EBX.RDT-M[bit 12] = 1.
Thread
7:0 EventID (R/W)
Event encoding:
0x00: No monitoring.
0x01: L3 occupancy monitoring.
0x02: Total memory bandwidth monitoring.
0x03: Local memory bandwidth monitoring.
All other encoding reserved.
31:8 Reserved.
41:32 RMID (R/W)
63:42 Reserved.
Register Address: C8FH, 3215 IA32_PQR_ASSOC
Resource Association Register (R/W) Thread
9:0 RMID
31:10 Reserved.
51:32 CLOS (R/W)
63: 52 Reserved.
Register Address: C90H, 3216 IA32_L3_QOS_MASK_0
L3 Class Of Service Mask - CLOS 0 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=0.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 0 enforcement.
63:20 Reserved.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-395
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C91H, 3217 IA32_L3_QOS_MASK_1
L3 Class Of Service Mask - CLOS 1 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=1.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 1 enforcement.
63:20 Reserved.
Register Address: C92H, 3218 IA32_L3_QOS_MASK_2
L3 Class Of Service Mask - CLOS 2 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=2.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 2 enforcement.
63:20 Reserved.
Register Address: C93H, 3219 IA32_L3_QOS_MASK_3
L3 Class Of Service Mask - CLOS 3 (R/W).
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=3.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 3 enforcement.
63:20 Reserved.
Register Address: C94H, 3220 IA32_L3_QOS_MASK_4
L3 Class Of Service Mask - CLOS 4 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=4.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 4 enforcement.
63:20 Reserved.
Register Address: C95H, 3221 IA32_L3_QOS_MASK_5
L3 Class Of Service Mask - CLOS 5 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=5.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 5 enforcement.
63:20 Reserved.
Register Address: C96H, 3222 IA32_L3_QOS_MASK_6
L3 Class Of Service Mask - CLOS 6 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=6.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 6 enforcement.
63:20 Reserved.
Register Address: C97H, 3223 IA32_L3_QOS_MASK_7
L3 Class Of Service Mask - CLOS 7 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=7.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 7 enforcement.
63:20 Reserved.
Register Address: C98H, 3224 IA32_L3_QOS_MASK_8
L3 Class Of Service Mask - CLOS 8 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=8.
Package
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
2-396 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
0:19 CBM: Bit vector of available L3 ways for CLOS 8 enforcement.
63:20 Reserved.
Register Address: C99H, 3225 IA32_L3_QOS_MASK_9
L3 Class Of Service Mask - CLOS 9 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=9.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 9 enforcement.
63:20 Reserved.
Register Address: C9AH, 3226 IA32_L3_QOS_MASK_10
L3 Class Of Service Mask - CLOS 10 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=10.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 10 enforcement.
63:20 Reserved.
Register Address: C9BH, 3227 IA32_L3_QOS_MASK_11
L3 Class Of Service Mask - CLOS 11 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=11.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 11 enforcement.
63:20 Reserved.
Register Address: C9CH, 3228 IA32_L3_QOS_MASK_12
L3 Class Of Service Mask - CLOS 12 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=12.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 12 enforcement.
63:20 Reserved.
Register Address: C9DH, 3229 IA32_L3_QOS_MASK_13
L3 Class Of Service Mask - CLOS 13 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=13.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 13 enforcement.
63:20 Reserved.
Register Address: C9EH, 3230 IA32_L3_QOS_MASK_14
L3 Class Of Service Mask - CLOS 14 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=14.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 14 enforcement.
63:20 Reserved.
Register Address: C9FH, 3231 IA32_L3_QOS_MASK_15
L3 Class Of Service Mask - CLOS 15 (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0] >=15.
Package
0:19 CBM: Bit vector of available L3 ways for CLOS 15 enforcement.
63:20 Reserved.
Table 2-50. MSRs Supported by the Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_55H (Contd.)
Register Address: Hex, Decimal Register Name (Former Register Name)
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-397
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.7 MSRs Specific to the 3rd Generation Intel® Xeon® Scalable Processor Family Based on
Ice Lake Microarchitecture
The 3rd generation Intel
®
Xeon
®
Scalable Processor Family based on Ice Lake microarchitecture (CPUID Signature
DisplayFamily_DisplayModel value of 06_6AH or 06_6CH) support the MSRs listed in Table 2-51.
Table 2-51. MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 612H, 1554 MSR_PACKAGE_ENERGY_TIME_STATUS
Package energy consumed by the entire CPU (R/W) Package
31:0 Total amount of energy consumed since last reset.
63:32 Total time elapsed when the energy was last updated. This is a monotonic
increment counter with auto wrap back to zero after overflow. Unit is
10ns.
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
Allows software to set power limits for the DRAM domain and measurement attributes associated with each limit. Package
14:0 DRAM_PP_PWR_LIM:
Power Limit[0] for DDR domain. Units = Watts, Format = 11.3, Resolution =
0.125W, Range = 0-2047.875W.
15 PWR_LIM_CTRL_EN:
Power Limit[0] enable bit for DDR domain.
16 Reserved.
23:17 CTRL_TIME_WIN:
Power Limit[0] time window Y value, for DDR domain. Actual time_window
for RAPL is:
(1/1024 seconds) * (1+(x/4)) * (2^y)
62:24 Reserved.
63 PP_PWR_LIM_LOCK:
When set, this entire register becomes read-only. This bit will typically be
set by BIOS during boot.
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
31:0 Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32 Reserved.
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM Power Parameters (R/W) Package
2-398 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
14:0 Spec DRAM Power (DRAM_TDP):
The Spec power allowed for DRAM. The TDP setting is
typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
15 Reserved.
30:16 Minimal DRAM Power (DRAM_MIN_PWR):
The minimal power setting allowed for DRAM. Lower
values will be clamped to this value. The minimum
setting is typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
31 Reserved.
46:32 Maximal Package Power (DRAM_MAX_PWR):
The maximal power setting allowed for DRAM. Higher
values will be clamped to this value. The maximum
setting is typical (not guaranteed).
The units for this value are defined in
MSR_DRAM_POWER_INFO_UNIT[PWR_UNIT].
47 Reserved.
54:48
Maximal Time Window (DRAM_MAX_WIN):
The maximal time window allowed for the DRAM.
Higher values will be clamped to this value.
x = PKG_MAX_WIN[54:53]
y = PKG_MAX_WIN[52:48]
The timing interval window is a floating-point number given by 1.x
*power(2,y).
The unit of measurement is defined in
MSR_DRAM_POWER_INFO_UNIT[TIME_UNIT].
62:55 Reserved.
63
LOCK:
Lock bit to lock the register.
Register Address: 981H, 2433 IA32_TME_CAPABILITY
See Table 2-2.
Register Address: 982H, 2434 IA32_TME_ACTIVATE
See Table 2-2.
Register Address: 983H, 2435 IA32_TME_EXCLUDE_MASK
See Table 2-2.
Register Address: 984H, 2436 IA32_TME_EXCLUDE_BASE
See Table 2-2.
Table 2-51. MSRs Supported by the 3rd Generation Intel® Xeon® Scalable Processor Family with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_6AH or 06_6CH (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-399
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.8 MSRs Specific to the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
The 4th generation Intel
®
Xeon
®
Scalable Processor Family based on Sapphire Rapids microarchitecture (CPUID
Signature DisplayFamily_DisplayModel value of 06_8FH) and the 5th generation Intel
®
Xeon
®
Scalable Processor
Family based on Emerald Rapids microarchitecture (CPUID Signature DisplayFamily_DisplayModel value of
06_CFH) both support the MSRs listed in Section 2.17, “MSRs In the 6th—13th Generation Intel® Core™ Proces-
sors, 1st—5th Generation Intel® Xeon® Scalable Processor Families, Intel® Core™ Ultra 7 Processors, 8th Gener-
ation Intel® Core™ i3 Processors, and Intel® Xeon® E Processors,” including Table 2-52. For an MSR listed in Table
2-52 that also appears in the model-specific tables of prior generations, Table 2-52 supersedes prior generation
tables.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 33H, 51 MSR_MEMORY_CTRL
Memory Control Register (R/W) Core
27:0 Reserved.
28 UC_LOCK_DISABLE
If set to 1, a UC lock will cause a #GP(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
29 SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
31:30 Reserved.
Register Address: A7H, 167 MSR_BIOS_DEBUG
BIOS DEBUG (R/O)
See Table 2-45.
Thread
Register Address: BCH, 188 IA32_MISC_PACKAGE_CTLS
Power Filtering Control (R/W)
IA32_ARCH_CAPABILITIES[bit 10] enumerates support for this MSR.
See Table 2-2.
Package
Register Address: CFH, 207 IA32_CORE_CAPABILITIES
IA32 Core Capabilities Register (R/W)
If CPUID.(EAX=07H, ECX=0):EDX[30] = 1.
This MSR provides an architectural enumeration function for model-specific behavior.
Core
0 Reserved: returns zero.
1 Reserved: returns zero.
2 INTEGRITY_CAPABILITIES
When set to 1, the processor supports MSR_INTEGRITY_CAPABILITIES.
3 RSM_IN_CPL0_ONLY
Indicates that RSM will only be allowed in CPL0 and will #GP for all non-
CPL0 privilege levels.
4 UC_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 28 of MSR_MEMORY_CTRL (MSR
address 33H).
2-400 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
5 SPLIT_LOCK_DISABLE_SUPPORTED
When read as 1, software can set bit 29 of MSR_MEMORY_CTRL.
6 Reserved: returns zero.
7 UC_STORE_THROTTLING_SUPPORTED
Indicates that the snoop filter quality of service MSRs are supported on
this core. This is based on the existence of a non-inclusive cache and the
L2/MLC QoS feature supported.
63:8 Reserved: returns zero.
Register Address: E1H, 225 IA32_UMWAIT_CONTROL
UMWAIT Control (R/W)
See Table 2-2.
Register Address: EDH, 237 MSR_RAR_CONTROL
RAR Control (R/W) Thread
63:32 Reserved.
31 ENABLE
RAR events are recognized. When RAR is not enabled, RARs are dropped.
30 IGNORE_IF
Allow RAR servicing at the RLP regardless of the value of RFLAGS.IF.
29:0 Reserved.
Register Address: EEH, 238 MSR_RAR_ACTION_VECTOR_BASE
Pointer to RAR Action Vector (R/W) Thread
63:MAXPHYADDR Reserved.
MAXPHYADDR-1:6 VECTOR_PHYSICAL_ADDRESS
Pointer to the physical address of the 64B aligned RAR action vector.
5:0 Reserved.
Register Address: EFH, 239 MSR_RAR_PAYLOAD_TABLE_BASE
Pointer to Base of RAR Payload Table (R/W) Thread
63:MAXPHYADDR Reserved.
MAXPHYADDR-1:12 TABLE_PHYSICAL_ADDRESS
Pointer to the base physical address of the 4K aligned RAR payload table.
11:0 Reserved.
Register Address: F0H, 240 MSR_RAR_INFO
Read Only RAR Information (RO) Thread
63:38 Always zero.
37:32 Table Max Index
Maximum supported payload table index.
31:0 Supported payload type bitmap. A value of 1 in bit position [i] indicates
that payload type [i] is supported.
Register Address: 105H, 261 MSR_CORE_BIST
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-401
MODEL-SPECIFIC REGISTERS (MSRS)
Core BIST (R/W)
Controls Array BIST activation and status checking as part of FUSA.
Core
31:0 BIST_ARRAY
Bitmap indicating which arrays to run BIST on (WRITE).
Bitmap indicating which arrays were not processed, i.e., completion mask
(READ).
39:32 BANK
Array bank of the [least significant set bit] array indicated in EAX to start
BIST(WRITE).
Array bank interrupted or failed (READ).
47:40 DWORD
Array dword of the [least significant set bit] array indicated in EAX to
start BIST (WRITE).
Array dword interrupted or failed (READ).
62:48 Reserved.
63 CTRL_RESULT
Indicates whether WRMSR should signal Machine-Check upon BIST-error
(WRITE).
BIST result PASS(0)/FAIL(1) of the (least significant set bit) array
indicated in EAX (READ).
Register Address: 10AH, 266 IA32_ARCH_CAPABILITIES
Enumeration of Architectural Features (R/O)
See Table 2-2.
Register Address: 1A4H, 420 MSR_PREFETCH_CONTROL
Prefetch Disable Bits (R/W)
0 L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches additional lines of
code or data into the L2 cache.
1 L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the cache
line that comprises a cache line pair (128 bytes).
2 DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next cache
line into L1 data cache.
3 DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses sequential load
history (based on instruction pointer of previous loads) to determine
whether to prefetch additional lines.
4 Reserved.
5 AMP_PREFETCH_DISABLE
If 1, disables the L2 Adaptive Multipath Probability (AMP) prefetcher.
63:6 Reserved.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-402 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1ADH, 429 MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turbo Ratio Limit (R/W)
See Table 2-46.
Package
Register Address: 1AEH, 430 MSR_TURBO_RATIO_LIMIT_CORES
See Table 2-50. Package
Register Address: 1C4H, 452 IA32_XFD
Extended Feature Detect (R/W)
See Table 2-2.
Register Address: 1C5H, 453 IA32_XFD_ERR
XFD Error Code (R/W)
See Table 2-2.
Register Address: 2C2H, 706 MSR_COPY_SCAN_HASHES
COPY_SCAN_HASHES (W) Die
63:0 SCAN_HASH_ADDR
Contains the linear address of the SCAN Test HASH Binary loaded into
memory.
Register Address: 2C3H, 707 MSR_SCAN_HASHES_STATUS
SCAN_HASHES_STATUS (R/O)
15:0 CHUNK_SIZE
Chunk size of the test in KB.
Die
23:16 NUM_CHUNKS
Total number of chunks.
Die
31:24 Reserved: all zeros.
39:32 ERROR_CODE
The error-code refers to the LP that runs WRMSR(2C2H).
0x0: No error reported.
0x1: Attempt to copy scan-hashes when copy already in progress.
0x2: Secure Memory not set up correctly.
0x3: Scan-image header Image_info.ProgramID doesn't match
RDMSR(2D9H)[31:24], or scan-image header Processor-Signature doesn't
match F/M/S, or scan-image header Processor-Flags doesn't match
PlatformID.
0x4: Reserved
0x5: Integrity check failed.
0x6: Re-install of scan test image attempted when current scan test
image is in use by other LPs.
Thread
50:40 Reserved: set to all zeros.
62:51 MAX_CORE_LIMIT
Maximum Number of cores that can run Intel® In-field Scan simultaneously
minus 1.
0 means 1 core at a time.
Die
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-403
MODEL-SPECIFIC REGISTERS (MSRS)
63 Valid
Valid bit is set when COPY_SCAN_HASHES has completed successfully.
Die
Register Address: 2C4H, 708 MSR_AUTHENTICATE_AND_COPY_CHUNK
AUTHENTICATE_AND_COPY_CHUNK (W) Die
7:0 CHUNK_INDEX
Chunk Index, should be less than the total number of chunks defined by
NUM_CHUNKS (MSR_SCAN_HASHES_STATUS[23:16]).
63:8 CHUNK_ADDR
Bits 63:8 of 256B aligned Linear address of scan chunk in memory.
Register Address: 2C5H, 709 MSR_CHUNKS_AUTHENTICATION_STATUS
CHUNKS_AUTHENTICATION_STATUS (R/O)
7:0 VALID_CHUNKS
Total number of Valid (authenticated) chunks.
Die
15:8 TOTAL_CHUNKS
Total number of chunks.
Die
31:16 Reserved: all zeros.
39:32 ERROR_CODE
The error code refers to the LP that runs WRMSR(2C4H).
0x0: No error reported.
0x1: Attempt to authenticate a CHUNK which is already marked as
authentic or is currently being installed by another core.
0x2: CHUNK authentication error. HASH of chunk did not match expected
value.
Thread
63:40 Reserved: set to all zeros.
Register Address: 2C6H, 710 MSR_ACTIVATE_SCAN
ACTIVATE_SCAN (W) Thread
7:0 CHUNK_START_INDEX
Indicates chunk index to start from.
15:8 CHUNK_STOP_INDEX
Indicates what chunk index to stop at (inclusive).
31:16 Reserved: all zeros.
62:32 THREAD_WAIT_DELAY
TSC based delay to allow threads to rendezvous.
63 SIGNAL_MCE
If 1, then on scan-error log MC in MC4_STATUS and signal MCE if machine
check signaling enabled in MC4_CTL[0].
If 0, then no logging/no signaling.
Register Address: 2C7H, 711 MSR_SCAN_STATUS
SCAN_STATUS (R/O)
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-404 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
7:0 CHUNK_NUM
SCAN Chunk that was reached.
Core
15:8 CHUNK_STOP_INDEX
Indicates what chunk index to stop at (inclusive). Maps to same field in
WRMSR(ACTIVATE_SCAN).
Core
31:16 Reserved: return all zeros.
39:32 ERROR_CODE
0x0: No error.
0x1: SCAN operation did not start. Other thread did not join in time.
0x2: SCAN operation did not start. Interrupt occurred prior to threads
rendezvous.
0x3: SCAN operation did not start. Power Management conditions are
inadequate to run Intel In-field Scan.
0x4: SCAN operation did not start. Non-valid chunks in the range
CHUNK_STOP_INDEX : CHUNK_START_INDEX.
0x5: SCAN operation did not start. Mismatch in arguments between
threads T0/T1.
0x6: SCAN operation did not start. Core not capable of performing SCAN
currently.
0x8: SCAN operation did not start. Exceeded number of Logical
Processors (LP) allowed to run Intel In-field Scan concurrently.
MAX_CORE_LIMIT exceeded.
0x9: Interrupt occurred. Scan operation aborted prematurely, not all
chunks requested have been executed.
Thread
61:40 Reserved: return all zeros.
62 SCAN_CONTROL_ERROR
Scan-System-Controller malfunction.
Core
63 SCAN_SIGNATURE_ERROR
Core failed SCAN-SIGNATURE checking for this chunk.
Core
Register Address: 2C8H, 712 MSR_SCAN_MODULE_ID
SCAN_MODULE_ID (R/O) Module
31:0 RevID of the currently installed scan test image. Maps to Revision field in
external header (offset 4).
63:32 Reserved: return all zeros.
Register Address: 2C9H, 713 MSR_LAST_SAF_WP
LAST_SAF_WP (R/O) Core
31:0 LAST_WP
Provides information about the core when the last
WRMSR(ACTIVATE_SCAN) was executed. Available only if enumerated in
MSR_INTEGRITY_CAPABILITIES[10:9].
63:32 Reserved: return all zeros.
Register Address: 2D9H, 729 MSR_INTEGRITY_CAPABILITIES
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-405
MODEL-SPECIFIC REGISTERS (MSRS)
INTEGRITY_CAPABILITIES (R/O) Module
0STARTUP_SCAN_BIST
When set, supports Intel In-field Scan.
3:1 Reserved: return all zeros.
4 PERIODIC_SCAN_BIST
When set, supports Intel In-field Scan.
23:5 Reserved: return all zeros.
31:24 ID of the scan programs supported for this part. WRMSR(2C2H) verifies
this value against the corresponding value in the scan-image header, i.e.,
Image_info.
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Package
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Package
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Package
Register Address: 413H, 1043 IA32_MC4_MISC
See Section 16.3.2.1, “IA32_MCi_CTL MSRs,” through Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
Bank MC4 reports MC errors from the PCU module.
If SIGNAL_MCE is set, a Scan Status is logged in MC4_STATUS and MC4_MISC.
Package
Register Address: 492H, 1170 IA32_VMX_PROCBASED_CTLS3
Capability Reporting Register of Tertiary Processor-Based VM-Execution Controls (R/O)
See Table 2-2.
Register Address: 493H, 1171 IA32_VMX_EXIT_CTLS2
Capability Reporting Register of Secondary VM-Exit Controls (R/O)
See Table 2-2.
Register Address: 540H, 1344 MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
See Table 2-47.
Thread
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
Energy consumed by DRAM devices.
Package
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-406 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
31:0 Energy in 61 micro-joules. Requires BIOS configuration to enable DRAM
RAPL mode 0 (Direct VR).
63:32 Reserved.
Register Address: 64DH, 1613 MSR_PLATFORM_ENERGY_STATUS
Platform Energy Status (R/O) Package
31:0 TOTAL_ENERGY_CONSUMED
Total energy consumption in J (32.0), in 10nsec units.
63:32 TIME_STAMP
Time stamp (U32.0).
Register Address: 65CH, 1628 MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W-L) Package
16:0 POWER_LIMIT_1
The average power limit value that the platform must not exceed over a
time window as specified by the Power_Limit_1_TIME field.
The default value is the Thermal Design Power (TDP) and varies with
product skus. The unit is specified in MSR_RAPL_POWER_UNIT.
17 POWER_LIMIT_1_EN
When set, the processor can apply control policies such that the platform
average power does not exceed the Power_Limit_1 value over an
exponential weighted moving average of the time window.
18 CRITICAL_POWER_CLAMP_1
When set, the processor can go below the OS-requested P States to
maintain the power below the specified Power_Limit_1 value.
25:19 POWER_LIMIT_1_TIME
This indicates the time window over which the Power_Limit_1 value
should be maintained.
This field is made up of two numbers from the following equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, and the unit is specified in
MSR_RAPL_POWER_UNIT[Time Unit].
31:26 Reserved.
48:32 POWER_LIMIT_2
This is the Duration Power limit value that the platform must not exceed.
The unit is specified in MSR_RAPL_POWER_UNIT.
49 Enable Platform Power Limit #2
When set, enables the processor to apply control policy such that the
platform power does not exceed Platform Power limit #2 over the Short
Duration time window.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-407
MODEL-SPECIFIC REGISTERS (MSRS)
50 Platform Clamping Limitation #2
When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit #2
value.
57:51 POWER_LIMIT_2_TIME
This indicates the time window over which the Power_Limit_2 value
should be maintained.
This field has the same format as the POWER_LIMIT_1_TIME field.
62:58 Reserved.
63 LOCK
Setting this bit will lock all other bits of this MSR until system RESET.
Register Address: 665H, 1637 MSR_PLATFORM_POWER_INFO
Platform Power Information (R/W) Package
16:0 MAX_PPL1
Maximum PP L1 value.
The unit is specified in MSR_RAPL_POWER_UNIT.
31:17 MIN_PPL1
Minimum PP L1 value.
The unit is specified in MSR_RAPL_POWER_UNIT.
48:32 MAX_PPL2
Maximum PP L2 value.
The unit is specified in MSR_RAPL_POWER_UNIT.
55:49 MAX_TW
Maximum time window.
The unit is specified in MSR_RAPL_POWER_UNIT.
62:56 Reserved.
63 LOCK
Setting this bit will lock all other bits of this MSR until system RESET.
Register Address: 666H, 1638 MSR_PLATFORM_RAPL_SOCKET_PERF_STATUS
Platform RAPL Socket Performance Status (R/O) Package
31:0 Count of limited performance due to platform RAPL limit.
Register Address: 6A0H, 1696 IA32_U_CET
Configure User Mode CET (R/W)
See Table 2-2.
Register Address: 6A2H, 1698 IA32_S_CET
Configure Supervisor Mode CET (R/W)
See Table 2-2.
Register Address: 6A4H, 1700 IA32_PL0_SSP
Linear address to be loaded into SSP on transition to privilege level 0. (R/W)
See Table 2-2.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-408 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6A5H, 1701 IA32_PL1_SSP
Linear address to be loaded into SSP on transition to privilege level 1. (R/W)
See Table 2-2.
Register Address: 6A6H, 1702 IA32_PL2_SSP
Linear address to be loaded into SSP on transition to privilege level 2. (R/W)
See Table 2-2.
Register Address: 6A7H, 1703 IA32_PL3_SSP
Linear address to be loaded into SSP on transition to privilege level 3. (R/W)
See Table 2-2.
Register Address: 6A8H, 1704 IA32_INTERRUPT_SSP_TABLE_ADDR
Linear address of a table of seven shadow stack pointers that are selected in IA-32e mode using the IST index (when
not 0) from the interrupt gate descriptor. (R/W)
See Table 2-2.
Register Address: 6E1H, 1761 IA32_PKRS
Specifies the PK permissions associated with each protection domain for supervisor pages (R/W)
See Table 2-2.
Register Address: 776H, 1910 IA32_HWP_CTL
See Table 2-2.
Register Address: 981H, 2433 IA32_TME_CAPABILITY
Memory Encryption Capability MSR
See Table 2-2.
Register Address: 985H, 2437 IA32_UINTR_RR
User Interrupt Request Register (R/W)
See Table 2-2.
Register Address: 986H, 2438 IA32_UINTR_HANDLER
User Interrupt Handler Address (R/W)
See Table 2-2.
Register Address: 987H, 2439 IA32_UINTR_STACKADJUST
User Interrupt Stack Adjustment (R/W)
See Table 2-2.
Register Address: 988H, 2440 IA32_UINTR_MISC
User-Interrupt Target-Table Size and Notification Vector (R/W)
See Table 2-2.
Register Address: 989H, 2441 IA32_UINTR_PD
User Interrupt PID Address (R/W)
See Table 2-2.
Register Address: 98AH, 2442 IA32_UINTR_TT
User-Interrupt Target Table (R/W)
See Table 2-2.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-409
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: C70H, 3184 MSR_B1_PMON_EVNT_SEL0
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C71H, 3185 MSR_B1_PMON_CTR0
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C72H, 3186 MSR_B1_PMON_EVNT_SEL1
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C73H, 3187 MSR_B1_PMON_CTR1
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C74H, 3188 MSR_B1_PMON_EVNT_SEL2
Uncore B-box 1 perfmon event select MSR. Package
Register Address: C75H, 3189 MSR_B1_PMON_CTR2
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C76H, 3190 MSR_B1_PMON_EVNT_SEL3
Uncore B-box 1vperfmon event select MSR. Package
Register Address: C77H, 3191 MSR_B1_PMON_CTR3
Uncore B-box 1 perfmon counter MSR. Package
Register Address: C82H, 3122 MSR_W_PMON_BOX_OVF_CTRL
Uncore W-box perfmon local box overflow control MSR. Package
Register Address: C8FH, 3215 IA32_PQR_ASSOC
See Table 2-2.
Register Address: C90H−C9EH, 3216−
3230
IA32_L3_QOS_MASK_0 through IA32_L3_QOS_MASK_14
See Table 2-50. Package
Register Address: D10H−D17H, 3344−
3351
IA32_L2_QOS_MASK_[0-7]
IA32_CR_L2_QOS_MASK_[0-7]
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
≥ 0. See Table 2-2.
Core
Register Address: D93H, 3475 IA32_PASID
See Table 2-2.
Register Address: 1200H−121FH, 4608−
4639
IA32_LBR_x_INFO
Last Branch Record Entry X Info Register (R/W)
See Table 2-2.
Register Address: 1406H, 5126 IA32_MCU_CONTROL
See Table 2-2.
Register Address: 14CEH, 5326 IA32_LBR_CTL
Last Branch Record Enabling and Configuration Register (R/W)
See Table 2-2.
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-410 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.17.9 MSRs Introduced in the Intel® Core™ Ultra 7 Processor Supporting Performance Hybrid
Architecture
Table 2-53 lists additional MSRs for the Intel Core Ultra 7 processor with a CPUID Signature DisplayFamily_Display-
Model value of 06_AAH. Table 2-54 lists the MSRs unique to the processor P-core. Table 2-55 lists the MSRs unique
to the processor E-core.
Register Address: 14CFH, 5327 IA32_LBR_DEPTH
Last Branch Record Maximum Stack Depth Register (R/W)
See Table 2-2.
Register Address: 1500H−151FH, 5376−
5407
IA32_LBR_x_FROM_IP
Last Branch Record Entry X Source IP Register (R/W)
See Table 2-2.
Register Address: 1600H−161FH, 5632−
5663
IA32_LBR_x_TO_IP
Last Branch Record Entry X Destination IP Register (R/W)
See Table 2-2.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 33H, 51 MSR_MEMORY_CTRL
Memory Control Register Core
26:0 Reserved.
27 UC_STORE_THROTTLE
If set to 1, when enabled, the processor will only allow one in-
progress UC store at a time.
28 UC_LOCK_DISABLE
If set to 1, a UC lock will cause a #GP(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
29 SPLIT_LOCK_DISABLE
If set to 1, a split lock will cause an #AC(0) exception.
See Section 9.1.2.3, “Features to Disable Bus Locks.”
63:30 Reserved.
Register Address: 7AH, 122 IA32_FEATURE_ACTIVATION
Feature Activation (R/W)
Implements Feature Activation command. WRMSR to this address activates all 'activatable' features on this thread.
See Table 2-2.
Register Address: 80H, 128 MSR_TRACE_HUB_STH_ACPIBAR_BASE
Table 2-52. Additional MSRs Supported by the 4th and 5th Generation Intel® Xeon® Scalable Processor Families
(CPUID Signature DisplayFamily_DisplayModel Values of 06_8FH and 06_CFH) (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-411
MODEL-SPECIFIC REGISTERS (MSRS)
MSR_TRACE_HUB_STH_ACPIBAR_BASE (R/W)
This register is used by BIOS to program Trace Hub STH base address that will be used by AET messages.
Thread
0LOCK
Lock bit. If set, this MSR cannot be re-written anymore. The lock
bit has to be set in order for the AET packets to be directed to
Trace Hub MMIO.
17:1 Reserved.
45:18 ADDRESS
AET target address in Trace Hub MMIO space.
63:46 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration (R/W) Core
3:0 PKG_C_STATE_LIMIT
Specifies the lowest processor-specific C-state code name
(consuming the least power) for the package.
The default is set as factory-configured package C-state limit.
The following C-state code name encodings may be supported:
0000b: C0/C1 (no package C-state support)
0001b: C2
0010b: C3
0011b: C6
0100b: C7
0101b: C7s
0110b: C8
0111b: C9
1000b: C10
7:4 MAX_CORE_C_STATE
Possible values are: 0000
−reserved; 0001−C1; 0010−C3,
0011−C6.
9:8 Reserved.
10 IO_MWAIT_REDIRECTION_ENABLE
When set, will map IO_read instructions sent to IO registers
PMG_IO_BASE_ADDR.PMB0+0/1/2 to MWAIT(C2,3,4) instructions;
applies to deepc4 too.
14:11 Reserved.
15 CFG_LOCK
When set, locks bits 15:0 of this register for further writes, until
the next reset occurs.
24:16 Reserved.
25 C3_STATE_AUTO_DEMOTION_ENABLE
When set, processor will conditionally demote C6/C7 requests to
C3 based on uncore auto-demote information.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-412 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
26 C1_STATE_AUTO_DEMOTION_ENABLE
When set, processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.
27 ENABLE_C3_UNDEMOTION
Enable Un-Demotion from Demoted C3.
28 ENABLE_C1_UNDEMOTION
Enable Un-Demotion from Demoted C1.
29 ENABLE_PKGC_AUTODEMOTION
Enable Package C-State Auto-Demotion. It enables use of the
history of past package C-state depth and residence, as a factor in
determining C-State depth.
30 ENABLE_PKGC_UNDEMOTION
Enable Package C-State Un-Demotion. It enables considering
cases where demotion was the incorrect decision in determining
C-State depth.
31 TIMED_MWAIT_ENABLE
When set, enables Timed MWAIT feature. MWAIT would #GP on
attempts to do setup MWAIT timer if this bit is not set.
63:32 Reserved.
Register Address: E4H, 228 MSR_IO_CAPTURE_BASE
IO Capture Base (R/W)
Power Management IO Redirection in C-state. See http://biosbits.org.
Core
15:0 LVL_2_BASE_ADDRESS
Specifies the base address visible to software for IO redirection. If
MSR_PKG_CST_CONFIG_CONTROL.IO_MWAIT_REDIRECTION_ENA
BLE, reads to this address will be consumed by the power
management logic and decoded to MWAIT instructions. When IO
port address redirection is enabled, this is the IO port address
reported to the OS/software.
18:16 CST_RANGE
Specifies the encoding value of the maximum C-State code name
to be included when IO read to MWAIT redirection is enabled by
MSR_PKG_CST_CONFIG_CONTROL.IO_MWAIT_REDIRECTION_ENA
BLE:
000b
−C3 is the max C-State to include.
001b
−C6 is the max C-State to include.
010b
−C7 is the max C-State to include.
63:19 Reserved.
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Feature Configuration (R/W) Core
0AESNI_LOCK
Once this bit is set, writes to this register will not be allowed.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-413
MODEL-SPECIFIC REGISTERS (MSRS)
1AESNI_DISABLE
This bit disables Advanced Encryption Standard feature on this
processor core. To disable AES, BIOS will write '11 to this MSR on
every core.
63:2 Reserved.
Register Address: 140H, 320 MSR_FEATURE_ENABLES
Feature Enable (R/W)
Miscellaneous enables for thread specific features.
Thread
0 CPUID_GP_ON_CPL_GT_0
Causes CPUID to #GP if CPL greater than 0 and not in SMM.
63:1 Reserved.
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target (R/W)
Legacy register holding temperature related constants for Platform use.
Package
6:0 TCC Offset Time Window
Describes the RATL averaging time window.
7 TCC Offset Clamping Bit
When enabled will allow RATL throttling below P1.
15:8 Temperature Control Offset
Fan Temperature Target Offset (a.k.a. T-Control) indicates the
relative offset from the Thermal Monitor Trip Temperature at
which fans should be engaged.
23:16 TCC Activation Temperature
The minimum temperature at which PROCHOT# will be asserted.
The value is degrees C.
30:24 TCC Activation Offset
Specifies a temperature offset in degrees C from the temperature
target (bits 23:16). PROCHOT# will assert at the offset target
temperature. Write is permitted only if
MSR_PLATFORM_INFO[30] is set.
31 LOCKED
When set, this entire register becomes read-only.
63:2 Reserved.
Register Address: 1A4H, 420 MSR_PREFETCH_CONTROL
PREFETCH Control (R/W)
Prefetch disable bits.
Thread
0 L2_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L2 hardware prefetcher, which fetches
additional lines of code or data into the L2 cache.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-414 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
1 L2_ADJACENT_CACHE_LINE_PREFETCHER_DISABLE
If 1, disables the adjacent cache line prefetcher, which fetches the
cache line that comprises a cache line pair (128 bytes).
2 DCU_HARDWARE_PREFETCHER_DISABLE
If 1, disables the L1 data cache prefetcher, which fetches the next
cache line into L1 data cache.
3 DCU_IP_PREFETCHER_DISABLE
If 1, disables the L1 data cache IP prefetcher, which uses
sequential load history (based on instruction pointer of previous
loads) to determine whether to prefetch additional lines.
4 DCU_NEXT_PAGE_PREFETCH_DISABLE
If 1, disables Next Page prefetcher.
5AMP_PREFETCH_DISABLE
If 1, disables L2 Adaptive Multipath Probability (AMP) prefetcher.
6 LLC_PAGE_PREFETCH_DISABLE
If 1, disables the LLC Page prefetcher.
7AOP_PREFETCH_DISABLE
8 STREAM_PREFETCH_CODE_FETCH_DISABLE
63:9 Reserved.
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0
OFFCORE_RSP_0 (R/W)
Offcore Response Event Select Register
Thread
0 TRUE_DEMAND_CACHE_LOAD
Demand Data Rd = DCU reads (includes partials) that is not tagged
homeless.
1DEMAND_RFO
Demand Instruction fetch = IFU Fetches. ItoM or RFO that is not
tagged homeless.
2 DEMAND_CODE_READ
Demand Instruction fetch = IFU Fetches. CRd or CRd_UC.
3 CORE_MODIFIED_WRITEBACK
WBMtoI or WBMtoE.
4 HW_PREFETCH_MLC_LOAD
L2 prefetcher requests triggered by reads from MEC (except
those triggered by I-side).
5 HW_PREFETCH_MLC_RFO
L2 prefetcher requests triggered by RFOs.
6 HW_PREFETCH_MLC_CODE
L2 prefetcher requests triggered by I-side requests.
7 HW_PREFETCH_LLC_LOAD
LLC prefetch requests triggered by DRd.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-415
MODEL-SPECIFIC REGISTERS (MSRS)
8 HW_PREFETCH_LLC_RFO
LLC prefetch requests triggered by RFO.
9 HW_PREFETCH_LLC_CODE
LLC prefetch requests triggered by CRd.
10 L1_HWPREFETCH
Covers Hardware PFRFO, PFNEAR, PFMED, PFFAR, PFHW, PFNTA,
PFNPP, PFIPP including the homeless versions.
11 ALL_STREAMING_STORE
Write Combining. WCiL or WCiLF.
12 CORE_NON_MODIFIED_WB
WBEFtoI or WBEFtoE.
13 LLC_PREFETCH
LLC prefetch of load/code/RFO.
14 L1_SWPREFETCH
Covers Software PFRFO, PFNEAR, PFMED, PFFAR, PFHW, PFNTA,
PFNPP, PFIPP including the homeless versions.
15 OTHER
Includes CLFlush, CLFlushOPT, CLDemote, CLWB, Enqueue
SetMonitor, PortIn, IntA, Lock, SplitLock, Unlock, SpCyc, ClrMonitor,
PortOut, IntPriUp, IntLog, IntPhy, EOI, RdCurr, WbStoI, LLCWBInv,
LLCInv, NOP, PCOMMIT.
16 ANY_RESP
Match on any response.
17 SUPPLIER_NONE
No Supplier Details. DATA_PRE [6:3] = 0.
18 LLC_HIT_M_STATE
LLC/L3, M-state, DATA_PRE [6:3] = 2.
19 LLC_HIT_E_STATE
LLC/L3, E-state, DATA_PRE [6:3] = 4.
20 LLC_HIT_S_STATE
LLC/L3, S-state, DATA_PRE [6:3] = 6.
21 LLC_HIT_F_STATE
LLC/L3, F-state, DATA_PRE [6:3] = 8.
22 FAR_MEM_LOCAL
Far Memory, Local, DATA_PRE [6:3] = 1.
23 FAR_MEM_REMOTE_0_HOP
Far Memory, Remote 0-hop, DATA_PRE [6:3] = 3.
24 FAR_MEM_REMOTE_1_HOP
Far Memory, Remote 1-hop, DATA_PRE [6:3] = 5.
25 FAR_MEM_REMOTE_2_PLUS_HOP
Far Memory, Rem 2+ hop, DATA_PRE [6:3] = 7.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-416 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
26 NEAR_MEM_MISS_LOCAL_NODE
LLC Miss Local Node. Near Memory, Local DATA_PRE [6:3] = E.
27 NEAR_MEM_REMOTE_0_HOP
Near Memory, Remote 0-hop, DATA_PRE [6:3] = B
28 NEAR_MEM_REMOTE_1_HOP
Near Memory, Remote 1-hop, DATA_PRE [6:3] = D.
29 NEAR_MEM_REMOTE_2_PLUS_HOP
Near Memory, Remote 2+ hop, DATA_PRE [6:3] = F.
30 SPL_HIT
Snoop Info: SPL-hit, DATA_PRE [2:0] = 6.
31 SNOOP_NONE
No details as to Snoop-related info. Snoop Info: None, DATA_PRE
[2:0] = 0.
32 NOT_NEEDED
No snoop was needed to satisfy the request. Snoop Info: Not
needed, DATA_PRE [2:0] = 1.
33 MISS
No snoop was needed to satisfy the request. Snoop Info: Miss,
DATA_PRE [2:0] = 2.
34 HIT_NO_FWD
A snoop was needed and it Hits in at least one snooped cache. Hit
denotes a cache-line was valid before snoop effect. Snoop Info:
Hit No Fwd, DATA_PRE [2:0] = 3.
35 HIT_EF_WITH_FWD
A snoop was needed and data was Forwarded from a remote
socket. Snoop Info: Hit EF w/Fwd, DATA_PRE [2:0] = 4.
36 HITM
A snoop was needed and it HitMed in local or remote cache. HitM
denotes a cache-line was modified before snoop effect. Snoop
Info: HitM, DATA_PRE [2:0] = 5.
37 NON_DRAM
Target was non-DRAM system address. Snoop Info: HitM,
DATA_PRE [2:0] = 5.
38 GO_ERR
GO-ERR, RspData[3:0] = 0100.
39 GO_NO_GO
GO-NoGO, RspData[3:0] = 0111.
40 INPKG_MEM_LOCAL
In-package Memory, Local, DATA_PRE [6:3] = 9.
41 INPKG_MEM_NONLOCAL
In-package Memory, Non-Local, DATA_PRE [6:3] = C.
43:42 Reserved.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-417
MODEL-SPECIFIC REGISTERS (MSRS)
44 UC_LOAD
PRd or UCRdF.
45 UC_STORE
WiL.
46 PARTIAL_STREAMING_STORES
WCiL.
47 FULL_STREAMING_STORES
WCiLF.
48 L1_MODIFIED_WB
EVICTION EXTTYPE from MEC.
49 L2_MODIFIED_WB
WBMtoI or WBMtoE.
50 PSMI
MemPushWr_NS (PSMI only).
51 ITOM
ItoM.
63:52 Reserved.
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
OFFCORE_RSP_1 (R/W)
Offcore Response Event Select Register. See MSR_OFFCORE_RSP_0 (at1A6H).
Thread
Register Address: 1AAH, 426 MSR_MISC_PWR_MGMT
Miscellaneous Power Management Control (R/W)
Various model-specific features enumeration. See http://biosbits.org.
Package
0 Reserved.
1 ENABLE_HWP_VOTING_RIGHT
When set (1), The CPU will take into account thread HWP requests
for threads that have voting rights only (ignores thread requests
if they do not have voting rights). When reset(0), The CPU will
take into account all thread HWP requests, even for threads that
don't have voting rights. Setting this bit will cause the HWP Base
feature bit to be reported in CPUID as present; clearing will cause
it to be reported as non-present.
5:2 Reserved.
6 ENABLE_HWP
Setting this bit will cause the HWP Base feature bit to report as
present in CPUID; clearing this bit will cause CPUID to report the
feature as non-present.
7 ENABLE_HWP_INTERRUPT
Setting this bit will cause the HWP Interrupt feature
CPUID[6].EAX[8] bit to report as present; clearing will report as
non-present.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-418 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
8 ENABLE_OUT_OF_BAND_AUTONOMOUS
Setting this bit will cause the HWP Autonomous feature bit to
report as present; clearing will report as non-present.
11:9 Reserved.
12 ENABLE_HWP_EPP
Enable HWP EPP. Setting this bit (1) will cause the HWP
CPUID[6].EAX[10] Energy Performance Preference bit to report
as present (1); clearing will report as non-present (0).
13 LOCK
Setting this bit will prevent the BIOS specific bits from changing
until the next reset. i.e., only Bits [0,22] which are meant for OS
use can be changed once the LOCK bit is set.
63:14 Reserved.
Register Address: 1ADH, 429 MSR_PRIMARY_TURBO_RATIO_LIMIT
Primary Maximum Turbo Ratio Limit (R/W)
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1. Specifies Maximum Ratio Limit for each
group. Maximum ratio for groups with more cores must decrease monotonically.
Package
7:0 MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8 MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16 MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24 MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32 MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40 MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48 MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56 MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 1F1H, 497 MSR_CRASHLOG_CONTROL
Crash Log Control (R/W)
Write data to a Crash Log configuration.
Thread
0 CDDIS
CrashDump_Disable: If set, indicates that Crash Dump is disabled.
1EN_GPRS
Collect GPRs on a crash dump. Only meaningful when CDDIS is
zero.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-419
MODEL-SPECIFIC REGISTERS (MSRS)
2EN_GPRS_IN_SMM
Collect GPRs in SMM on a crash dump. Only meaningful when
CDDIS is zero. EN_GPRS will override this control,
3 TRIPLE_FAULT_SHUTDOWN
Collect a crash log on a triple fault shutdown. Only meaningful
when CDDIS is zero.
63:4 Reserved.
Register Address: 1F5H, 501 MSR_PRMRR_PHYS_MASK
Processor Reserved Memory Range Register - Physical Mask (R/W) Core
9:0 Reserved.
10 LOCK
Once set, this bit prevents software from modifying the PRMRR.
11 VALID
This bit serves as the enable for the PRMRR; the PRMRR must be
LOCKed before it can be enabled.
19:12 Reserved.
45:20 MASK
PRMRR Address Mask.
63:46 Reserved.
Register Address: 1FCH, 508 MSR_POWER_CTL
Power Control Register (R/W)
See http://biosbits.org.
Package
0 ENABLE_BIDIR_PROCHOT
Used to enable or disable the response to PROCHOT# input.
When set/enabled, the platform can force the CPU to throttle to a
lower power condition such as Pn/Pm by asserting prochot#.
When clear/disabled (default), the CPU ignores the status of the
prochot input signal.
1C1E_ENABLE
When set to '1', will enable the CPU to switch to the Minimum
Enhanced Intel SpeedStep Technology operating point when all
execution cores enter MWAIT (C1).
2 SAPM_IMC_C2_POLICY
This bit determines if self-refresh activation is allowed when
entering Package C2 State. If it is set to 0b, PCODE will keep the
FORCE_SR_OFF bit asserted in Package C2 State and allow its
negation according to the defined latency negotiations with the
PCH and Display Engine in Package C3 and deeper states.
Otherwise, self-refresh is allowed in Package C2 State.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-420 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
3FAST_BRK_SNP_EN
This bit controls the VID swing rate for the OTHER_SNP_WAKE
events that are detected by the iMPH. This is the event that is
detected by the iMPH when a non-DMI snoopable request is
observed while UCLK domain is not functional.
0b: Use slow VID swing rate.
1b: Use fast VID swing rate.
17:4 Reserved.
18 PWR_PERF_PLTFRM_OVR
Power performance platform override.
19 EE_TURBO_DISABLE
Setting this bit disables the P-States energy efficiency
optimization. Default value is 0. Disable/enable the energy
efficiency optimization in P-State legacy mode (when
IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
turbo range or into PERF_MIN_CTL value if it is not zero set. In
HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an
effect between the OS desired or OS maximize to the OS minimize
performance setting.
20 RTH_DISABLE
Setting this bit disables the Race to Halt optimization and avoids
this optimization limitation to execute below the most efficient
frequency ratio. Default value is 0 for processors that support
Race to Halt optimization.
21 DIS_PROCHOT_OUT
Prochot output disable.
22 PROCHOT_RESPONSE
Prochhot configurable response enable.
23 VR_THERM_ALERT_DISABLE_LOCK
When set to 1, locks PROCHOT related bits of this MSR. Once set,
a reset is required to clear this bit.
24 VR_THERM_ALERT_DISABLE
When set to 1, disables the VR_THERMAL_ALERT signaling.
25 DISABLE_RING_EE
Disable Ring EE.
26 DISABLE_SA_OPTIMIZATION
Disable SA optimization.
27 DISABLE_OOK
Disable OOK.
28 DISABLE_AUTONOMOUS
Disable HWP autonomous mode.
29 Reserved.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-421
MODEL-SPECIFIC REGISTERS (MSRS)
30 CSTATE_PREWAKE_DISABLE
C-state pre-wake disable.
63:31 Reserved.
Register Address: 2A0H, 672 MSR_PRMRR_BASE_0
Processor Reserved Memory Range Register - Physical Base Control Register (R/W) Core
2:0 MEMTYPE
Memory type for PRMRR accesses.
3CONFIGURED
PRMRR base configured.
19:4 Reserved.
45:20 BASE
PRMRR base address.
63:46 Reserved.
Register Address: 474H, 1140 IA32_MC29_CTL
MC29_CTL. See Table 2-2. Package
Register Address: 475H, 1141 IA32_MC29_STATUS
MC29_STATUS. See Table 2-2. Package
Register Address: 476H, 1142 IA32_MC29_ADDR
MC29_ADDR. See Table 2-2. Package
Register Address: 477H, 1143 IA32_MC29_MISC
MC29_MISC. See Table 2-2. Package
Register Address: 478H, 1144 IA32_MC30_CTL
MC30_CTL. See Table 2-2. Package
Register Address: 479H, 1145 IA32_MC30_STATUS
MC30_STATUS. See Table 2-2. Package
Register Address: 47AH, 1146 IA32_MC30_ADDR
MC30_ADDR. See Table 2-2. Package
Register Address: 47BH, 1147 IA32_MC30_MISC
MC30_MISC. See Table 2-2. Package
Register Address: 47CH, 1148 IA32_MC31_CTL
MC31_CTL. See Table 2-2. Package
Register Address: 47DH, 1149 IA32_MC31_STATUS
MC31_STATUS. See Table 2-2. Package
Register Address: 47EH, 1150 IA32_MC31_ADDR
MC31_ADDR. See Table 2-2. Package
Register Address: 47FH, 1151 IA32_MC31_MISC
MC31_MISC. See Table 2-2. Package
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-422 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 4E0H, 1248 MSR_SMM_FEATURE_CONTROL
Enhanced SMM Feature Control (R/W)
Reports SMM capability enhancement.
Package
0LOCK
When set, locks this register from further changes.
1 SMM_CPU_SAVE_EN
If 0, SMI/RSM will save/restore state in SMRAM
If 1, SMI/RSM will save/restore state from SRAM.
2 SMM_CODE_CHK_EN
When clear (default) none of the logical processors are prevented
from executing SMM code outside the ranges defined by the
SMRR. When set, any logical processor in the package that
attempts to execute SMM code not within the ranges defined by
the SMRR will assert an unrecoverable MCE.
63:3 Reserved.
Register Address: 601H, 1537 MSR_VR_CURRENT_CONFIG
Power Limit 4 (PL4) (R/W)
Package-level maximum power limit (in Watts). It is a proactive, instantaneous limit.
Package
15:0 CURRENT_LIMIT
PL4 Value in 0.125 A increments. This field is locked by
MSR_VR_CURRENT_CONFIG.LOCK. When the LOCK bit is set to 1,
this field becomes Read Only.
30:16 Reserved.
31 LOCK
This bit will lock the CURRENT_LIMIT settings in this register and
will also lock this setting. This means that once set to 1, the
CURRENT_LIMIT setting and this bit become Read Only until the
next Warm Reset.
63:32 Reserved.
Register Address: 620H, 1568 MSR_UNCORE_RATIO_LIMIT
Uncore Ratio Limit (R/W)
Min/Max Ratio Limits for Uncore LLC and Ring.
Package
6:0 MAX_CLR_RATIO
Maximum allowed ratio for the Ring and Last Level Cache (LLC).
7 Reserved.
14:8 MIN_CLR_RATIO
Minimum allowed ratio for the Ring and Last Level Cache (LLC).
63:15 Reserved.
Register Address: 638H, 1592 MSR_PP0_POWER_LIMIT
MSR_PP0_POWER_LIMIT (R/W)
PP0 RAPL power unit control.
Package
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-423
MODEL-SPECIFIC REGISTERS (MSRS)
14:0 IA_PP_PWR_LIM
This is the power limitation on the IA cores power plane.
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].
15 PWR_LIM_CTRL_EN
This bit must be set in order to limit the power of the IA cores
power plane.
0b: IA cores power plane power limitation is disabled.
1b: IA cores power plane power limitation is enabled.
16 PP_CLAMP_LIM
Power Plane Clamping limitation; allow going below P1.
0b: PBM is limited between P1 and P0.
1b: PBM can go below P1.
23:17 CTRL_TIME_WIN
x = CTRL_TIME_WIN[23:22]
y = CTRL_TIME_WIN[21:17]
The timing interval window is Floating Point number given by 1.x
* power(2,y).
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].
The maximal time window is bounded by
PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum time
window is 1 unit of measurement (as defined above).
30:24 Reserved.
31 PP_PWR_LIM_LOCK
When set, all settings in this register are locked and are treated as
Read Only.
63:32 Reserved.
Register Address: 64FH, 1615 MSR_CORE_PERF_LIMIT_REASONS
Core Performance Limit Reasons
Indicator of Frequency Clipping in Processor Cores. (Frequency refers to processor core frequency.)
Package
0PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced below the
operating system request due to assertion of external PROCHOT.
1 THERMAL (R/O)
Thermal Status. When set, frequency is reduced below the
operating system request due to a thermal event.
3:2 Reserved.
4 RSR_LIMIT (R/O)
Residency State Regulation Status. When set, frequency is
reduced below the operating system request due to residency
state regulation limit.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-424 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
5 RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced below the operating system request due to Running
Average Thermal Limit (RATL).
6 VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced below the
operating system request due to a thermal alert from a processor
Voltage Regulator (VR).
7VR_TDC (R/O)
VR Therm Design Current Status. When set, frequency is reduced
below the operating system request due to VR thermal design
current limit.
8OTHER (R/O)
Other Status. When set, frequency is reduced below the operating
system request due to electrical or other constraints.
9 Reserved.
10 PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced below the operating system request due to
package/platform-level power limiting PL1.
11 PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced below the operating system request due to
package/platform-level power limiting PL2/PL3.
12 MAX_TURBO_LIMIT (R/O)
Max Turbo Limit Status. When set, frequency is reduced below
the operating system request due to multi-core turbo limits.
13 TURBO_ATTEN (R/O)
Turbo Transition Attenuation Status. When set, frequency is
reduced below the operating system request due to Turbo
transition attenuation. This prevents performance degradation
due to frequent operating ratio changes.
15:14 Reserved.
16 PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17 THERMAL_LOG (R/W)
Thermal Log When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
19:18 Reserved.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-425
MODEL-SPECIFIC REGISTERS (MSRS)
20 RSR_LIMIT_LOG (R/W)
Residency State Regulation Log. When set, indicates that the
Residency State Regulation Status bit has asserted since the log
bit was last cleared. This log bit will remain set until cleared by
software writing 0.
21 RATL_LOG (R/W)
Running average thermal limit Log, RW, When set by PCODE
indicates that Running average thermal limit has cause IA
frequency clipping. Software should write to this bit to clear the
status in this bit.
22 VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23 VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
TDC Status bit has asserted since the log bit was last cleared. This
log bit will remain set until cleared by software writing 0.
24 OTHER_LOG (R/W)
Other Log. When set, indicates that the Other Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25 Reserved.
26 PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package or Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
27 PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package or Platform Level PL2/PL3 Power
Limiting Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
28 MAX_TURBO_LIMIT_LOG (R/W)
Max Turbo Limit Log. When set, indicates that the Max Turbo Limit
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
29 TURBO_ATTEN_LOG (R/W)
Turbo Transition Attenuation Log. When set, indicates that the
Turbo Transition Attenuation Status bit has asserted since the log
bit was last cleared. This log bit will remain set until cleared by
software writing 0.
63:30 Reserved.
Register Address: 650H, 1616 MSR_SECONDARY_TURBO_RATIO_LIMIT
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-426 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Secondary Maximum Turbo Ratio Limit (R/W)
Software can configure these limits when MSR_PLATFORM_INFO[28] = 1.
Specifies Maximum Ratio Limit for each group. Maximum ratio for groups with more cores must decrease
monotonically.
Package
7:0 MAX_TURBO_GROUP_0:
Maximum turbo ratio limit with 1 core active.
15:8 MAX_TURBO_GROUP_1:
Maximum turbo ratio limit with 2 cores active.
23:16 MAX_TURBO_GROUP_2:
Maximum turbo ratio limit with 3 cores active.
31:24 MAX_TURBO_GROUP_3:
Maximum turbo ratio limit with 4 cores active.
39:32 MAX_TURBO_GROUP_4:
Maximum turbo ratio limit with 5 cores active.
47:40 MAX_TURBO_GROUP_5:
Maximum turbo ratio limit with 6 cores active.
55:48 MAX_TURBO_GROUP_6:
Maximum turbo ratio limit with 7 cores active.
63:56 MAX_TURBO_GROUP_7:
Maximum turbo ratio limit with 8 cores active.
Register Address: 65CH, 1628 MSR_PLATFORM_POWER_LIMIT
Platform Power Limit Control (R/W)
Allows platform BIOS to limit power consumption of the platform devices to the specified values. The Long Duration
power consumption is specified via Platform_Power_Limit_1 and Platform_Power_Limit_1_Time. The Short Duration
power consumption limit is specified via the Platform_Power_Limit_2 with duration chosen by the processor. The
processor implements an exponential-weighted algorithm in the placement of the time windows.
Package
14:0 POWER_LIMIT_1
Average Power limit value which the platform must not exceed
over a time window as specified by Power_Limit_1_TIME field.
The default value is the Thermal Design Power (a.k.a TDP) and
varies with product skus. The unit is specified in
MSR_RAPLPOWER_UNIT.
15 POWER_LIMIT_1_EN
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit 1 over
the time window specified by Power Limit 1 Time Window.
16 CRITICAL_POWER_CLAMP_1
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit 1 value.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-427
MODEL-SPECIFIC REGISTERS (MSRS)
23:17 POWER_LIMIT_1_TIME
Specifies the duration of the time window over which Platform
Power Limit 1 value should be maintained for sustained long
duration. This field is made up of two numbers from the following
equation:
Time Window = (float) ((1+(X/4))*(2^Y)), where:
X = POWER_LIMIT_1_TIME[23:22]
Y = POWER_LIMIT_1_TIME[21:17]
The maximum allowed value in this field is defined in
MSR_PKG_POWER_INFO[PKG_MAX_WIN].
The default value is 0DH, The unit is specified in
MSR_RAPLPOWER_UNIT[Time Unit]
31:24 Reserved.
46:32 POWER_LIMIT_2
Average Power limit value which the platform must not exceed
over the Short Duration time window chosen by the processor.
The recommended default value is 1.25 times the Long Duration
Power Limit (i.e., Platform Power Limit 1).
47 POWER_LIMIT_2_EN
When set, enables the processor to apply control policy such that
the platform power does not exceed Platform Power limit 2 over
the Short Duration time window.
48 CRITICAL_POWER_CLAMP_2
When set, allows the processor to go below the OS requested P
states in order to maintain the power below specified Platform
Power Limit 2 value.
62:49 Reserved.
63 LOCK
Setting this bit will lock all other bits of this MSR until system
RESET.
Register Address: 6BOH, 1712 MSR_GRAPHICS_PERF_LIMIT_REASONS
MSR_GRAPHICS_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Processor Graphics. (Frequency refers to processor graphics frequency.)
Package
0PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced due to
assertion of external PROCHOT.
1 THERMAL (R/O)
Thermal Status. When set, frequency is reduced due to a thermal
event.
4:2 Reserved.
5 RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced due to running average thermal limit.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-428 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
6 VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced due to a
thermal alert from a processor Voltage Regulator.
7VR_TDC (R/O)
VR Thermal Design Current Status. When set, frequency is
reduced due to VR TDC limit.
8OTHER (R/O)
Other Status. When set, frequency is reduced due to electrical or
other constraints.
9 Reserved.
10 PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced due to package/platform-level power
limiting PL1.
11 PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced due to package/platform-level power
limiting PL2/PL3.
12 INEFFICIENT_OPERATION (R/O)
Inefficient Operation Status. When set, processor graphics
frequency is operating below target frequency.
15:13 Reserved.
16 PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17 THERMAL_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
20:18 Reserved.
21 RATL_LOG (R/W)
Running Average Thermal Limit Log. When set, indicates that the
RATL Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23 VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
Therm Alert Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-429
MODEL-SPECIFIC REGISTERS (MSRS)
24 OTHER_LOG (R/W)
Other Log. When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25 Reserved.
26 PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
27 PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
28 INEFFICIENT_OPERATION_LOG (R/W)
Inefficient Operation Log. When set, indicates that the Inefficient
Operation Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
63:29 Reserved.
Register Address: 6B1H, 1713 MSR_RING_PERF_LIMIT_REASONS
MSR_RING_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in the Ring Interconnect. (Frequency refers to ring interconnect in the uncore.)
Package
0PROCHOT (R/O)
PROCHOT Status. When set, frequency is reduced due to
assertion of external PROCHOT.
1 THERMAL (R/O)
Thermal Status. When set, frequency is reduced due to a thermal
event.
4:2 Reserved.
5 RATL (R/O)
Running Average Thermal Limit Status. When set, frequency is
reduced due to running average thermal limit.
6 VR_THERMALERT (R/O)
VR Therm Alert Status. When set, frequency is reduced due to a
thermal alert from a processor Voltage Regulator.
7VR_TDC (R/O)
VR Thermal Design Current Status. When set, frequency is
reduced due to VR TDC limit.
8OTHER (R/O)
Other Status. When set, frequency is reduced due to electrical or
other constraints.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-430 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
9 Reserved.
10 PBM_PL1 (R/O)
Package/Platform-Level Power Limiting PL1 Status. When set,
frequency is reduced due to package/platform-level power
limiting PL1.
11 PBM_PL2 (R/O)
Package/Platform-Level PL2 Power Limiting Status. When set,
frequency is reduced due to package/platform-level power
limiting PL2/PL3.
15:12 Reserved.
16 PROCHOT_LOG (R/W)
PROCHOT Log. When set, indicates that the PROCHOT Status bit
has asserted since the log bit was last cleared. This log bit will
remain set until cleared by software writing 0.
17 THERMAL_LOG (R/W)
Thermal Log. When set, indicates that the Thermal Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
20:18 Reserved.
21 RATL_LOG (R/W)
Running Average Thermal Limit Log. When set, indicates that the
RATL Status bit has asserted since the log bit was last cleared.
This log bit will remain set until cleared by software writing 0.
22 VR_THERMALERT_LOG (R/W)
VR Therm Alert Log. When set, indicates that the VR Therm Alert
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
23 VR_TDC_LOG (R/W)
VR Thermal Design Current Log. When set, indicates that the VR
Therm Alert Status bit has asserted since the log bit was last
cleared. This log bit will remain set until cleared by software
writing 0.
24 OTHER_LOG (R/W)
Other Log. When set, indicates that the OTHER Status bit has
asserted since the log bit was last cleared. This log bit will remain
set until cleared by software writing 0.
25 Reserved.
26 PBM_PL1_LOG (R/W)
Package/Platform-Level PL1 Power Limiting Log. When set,
indicates that the Package/Platform Level PL1 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-431
MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-54 are unique to the Intel Core Ultra 7 processor P-core. These MSRs are not supported
on the processor E-core.
27 PBM_PL2_LOG (R/W)
Package/Platform-Level PL2 Power Limiting Log. When set,
indicates that the Package/Platform Level PL2 Power Limiting
Status bit has asserted since the log bit was last cleared. This log
bit will remain set until cleared by software writing 0.
63:28 Reserved.
Register Address: 9FBH, 2555 IA32_TME_CLEAR_SAVED_KEY
IA32_TME_CLEAR_SAVED_KEY (R/W)
See Table 2-2.
Package
Register Address: 9FFH, 2559 MSR_CORE_MKTME_ACTIVATE
MSR_CORE_MKTME_ACTIVATE (R/O)
MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS].
Core
31:0 Reserved.
35:32 READ_MK_TME_KEYID_BITS
This value will be returned on a RDMSR, but must be zero on a
WRMSR.
63:36 Reserved.
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 30CH, 780 IA32_FIXED_CTR3
Fixed-Function Performance Counter 3 (R/W) Thread
47:0 FIXED_COUNTER
Top-down Microarchitecture Analysis unhalted number of available
slots counter.
63:48 Reserved.
Register Address: 329H, 809 MSR_PERF_METRICS
Performance Metrics (R/W)
This register provides built-in support for Top-down Micro-architecture Analysis (TMA) metrics. It exposes the four
TMA Level 1 metrics where the lower 32 bits are divided into four 8 bit fields, each of which is an integer percentage
of the total TOPDOWN.SLOTS (as reported by fixed counter 3).
Thread
7:0 RETIRING
Percent of utilized by uops that eventually retire (commit).
15:8 BAD_SPECULATION
Percent of Wasted due to incorrect speculation, covering Utilized by
uops that do not retire, or Recovery Bubbles (unutilized slots).
Table 2-53. Additional MSRs Supported by the Intel® Core™ Ultra 7 Processors Supporting Performance Hybrid
Architecture (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-432 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
The MSRs listed in Table 2-48 are unique to the Intel Core Ultra 7 processor E-core. These MSRs are not supported
on the processor P-core.
23:16 FRONTEND_BOUND
Percent of Unutilized slots where Front-end did not deliver a uop
while Back-end is ready.
31:24 BACKEND_BOUND
Percent of Unutilized slots where a uop was not delivered to Back-
end due to lack of Back-end resources.
39:32 MULTI_UOPS
Frontend bound.
47:40 BRANCH_MISPREDICTS
Frontend bound.
55:48 FRONTEND_LATENCY
Frontend bound.
63:56 MEMORY_BOUND
Frontend bound.
Register Address: 540H, 1344 MSR_THREAD_UARCH_CTL
Thread Microarchitectural Control (R/W)
See Table 2-47.
Thread
Register Address: 541H, 1345 MSR_CORE_UARCH_CTL
Core Microarchitecture Control MSR (R/W)
See Table 2-44.
Core
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 4F0H, 1264 MSR_SAF_CTRL
SAF Control (W/O)
Extension to SAF.
Package
0 INVALIDATE_CURRENT_STRIDE
Invalidate all chunks in current stride.
63:1 Reserved.
Register Address: D18H−D1FH, 3352−3359 IA32_L2_MASK_[8-15]
IA32_L2_MASK_[8-15] (R/W)
If CPUID.(EAX=10H, ECX=1):EDX.COS_MAX[15:0]
≥ 0.
Controls MLC (L2) Intel RDT allocation. For more details on CAT/RDT, see Chapter 18, “Debug, Branch Profile, TSC, and
Intel® Resource Director Technology (Intel® RDT) Features.”
Module
15:0 WAY_MASK
Capacity Bit Mask. Available ways vectors for class of service of
IA core. '1 in bit indicates allocation to the way is allowed. '0
indicates allocation to the way is not allowed.
Table 2-54. MSRs Supported by the Intel® Core™ Ultra 7 Processor P-core (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-433
MODEL-SPECIFIC REGISTERS (MSRS)
2.18 MSRS IN THE INTEL® XEON PHI™ PROCESSOR 3200/5200/7200 SERIES
AND THE INTEL® XEON PHI™ PROCESSOR 7215/7285/7295 SERIES
The Intel
®
Xeon Phi™ processor 3200, 5200, 7200 series, with a CPUID Signature DisplayFamily_DisplayModel
value of 06_57H, supports the MSR interfaces listed in Table 2-56. These processors are based on the Knights
Landing microarchitecture. The Intel
®
Xeon Phi™ processor 7215, 7285, 7295 series, with a CPUID Signature
DisplayFamily_DisplayModel value of 06_85H, supports the MSR interfaces listed in Table 2-56 and Table 2-57.
These processors are based on the Knights Mill microarchitecture. Some MSRs are shared between a pair of
processor cores, and the scope is marked as module.
31:16 Reserved.
Register Address: 1309H−130BH, 4873−4875 MSR_RELOAD_FIXED_CTRx
Reload value for IA32_FIXED_CTRx (R/W) Thread
47:0 Value loaded into IA32_FIXED_CTRx when a PEBS record is
generated while PEBS_EN_FIXEDx = 1 and PEBS_OUTPUT =
01B in IA32_PEBS_ENABLE, and FIXED_CTRx is overflowed.
63:48 Reserved.
Register Address: 14C1H−14C8H, 5313 −5320 MSR_RELOAD_PMCx
Reload value for IA32_PMCx (R/W) Thread
47:0 Value loaded into IA32_PMCx when a PEBS record is generated
while PEBS_EN_PMCx = 1 and PEBS_OUTPUT = 01B in
IA32_PEBS_ENABLE, and PMCx is overflowed.
63:48 Reserved.
Register Address: 1A8EH, 6798 MSR_STLB_FILL_TRANSLATION
STLB Fill Translation (W/O)
STLB QoS MSR to fill translations into STLB.
Core
3:0 CLOS
Class of service to use for the fill.
9:4 Reserved.
10 X
Set to 1 when LA is to an executable page.
11 RW
Set to 1 when LA is to a writeable page.
63:12 LA
Logical address to use for fill.
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” Module
Table 2-55. MSRs Supported by the Intel® Core™ Ultra 7 Processor E-core (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-434 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.” Module
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” See Table 2-2. Thread
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Thread
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
Package
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Thread
Register Address: 34H, 52 MSR_SMI_COUNT
SMI Counter (R/O) Thread
31:0 SMI Count (R/O)
63:32 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in Intel 64Processor (R/W)
See Table 2-2.
Thread
0Lock. (R/WL)
1 Reserved.
2 Enable VMX outside SMX operation. (R/WL)
Register Address: 3BH, 59 IA32_TSC_ADJUST
Per-Logical-Processor TSC ADJUST (R/W)
See Table 2-2.
Thread
Register Address: 4EH, 78 IA32_PPIN_CTL (MSR_PPIN_CTL)
Protected Processor Inventory Number Enable Control (R/W) Package
0LockOut (R/WO)
See Table 2-2.
1Enable_PPIN (R/W)
See Table 2-2.
63:2 Reserved
Register Address: 4FH, 79 IA32_PPIN (MSR_PPIN)
Protected Processor Inventory Number (R/O) Package
63:0 Protected Processor Inventory Number (R/O)
See Table 2-2.
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Core
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-435
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Thread
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
See Table 2-2.
Thread
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Thread
Register Address: CEH, 206 MSR_PLATFORM_INFO
Platform Information
Contains power management and other model specific features enumeration. See http://biosbits.org.
Package
7:0 Reserved.
15:8 Maximum Non-Turbo Ratio (R/O)
This is the ratio of the frequency that invariant TSC runs at. Frequency
= ratio * 100 MHz.
Package
27:16 Reserved.
28 Programmable Ratio Limit for Turbo Mode (R/O)
When set to 1, indicates that Programmable Ratio Limit for Turbo mode
is enabled. When set to 0, indicates Programmable Ratio Limit for Turbo
mode is disabled.
Package
29 Programmable TDP Limit for Turbo Mode (R/O)
When set to 1, indicates that TDP Limit for Turbo mode is
programmable. When set to 0, indicates TDP Limit for Turbo mode is
not programmable.
Package
39:30 Reserved.
47:40 Maximum Efficiency Ratio (R/O)
This is the minimum ratio (maximum efficiency) that the processor can
operate, in units of 100MHz.
Package
63:48 Reserved.
Register Address: E2H, 226 MSR_PKG_CST_CONFIG_CONTROL
C-State Configuration Control (R/W) Package
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-436 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2:0 Package C-State Limit (R/W)
Specifies the lowest C-state for the package. This feature does not limit
the processor core C-state. The power-on default value from bit[2:0] of
this register reports the deepest package C-state the processor is
capable to support when manufactured. It is recommended that BIOS
always read the power-on default value reported from this bit field to
determine the supported deepest C-state on the processor and leave it
as default without changing it.
000b - C0/C1 (No package C-state support)
001b - C2
010b - C6 (non retention)*
011b - C6 (Retention)*
100b - Reserved
101b - Reserved
110b - Reserved
111b - No package C-state limit. All C-States supported by the
processor are available.
Note: C6 retention mode provides more power saving than C6 non-
retention mode. Limiting the package to C6 non retention mode does
prevent the MSR_PKG_C6_RESIDENCY counter (MSR 3F9h) from being
incremented.
9:3 Reserved.
10 I/O MWAIT Redirection Enable (R/W)
When set, will map IO_read instructions sent to IO registers at
MSR_PMG_IO_CAPTURE_BASE[15:0] to MWAIT instructions.
14:11 Reserved.
15 CFG Lock (R/O)
When set, locks bits [15:0] of this register for further writes until the
next reset occurs.
25 Reserved.
26 C1 State Auto Demotion Enable (R/W)
When set, the processor will conditionally demote C3/C6/C7 requests
to C1 based on uncore auto-demote information.
27 Reserved.
28 C1 State Auto Undemotion Enable (R/W)
When set, enables Undemotion from Demoted C1.
29 PKG C-State Auto Demotion Enable (R/W)
When set, enables Package C state demotion.
63:30 Reserved.
Register Address: E4H, 228 MSR_PMG_IO_CAPTURE_BASE
Power Management IO Capture Base (R/W) Tile
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-437
MODEL-SPECIFIC REGISTERS (MSRS)
15:0 LVL_2 Base Address (R/W)
Microcode will compare IO-read zone to this base address to determine
if an MWAIT(C2/3/4) needs to be issued instead of the IO-read. Should
be programmed to the chipset Plevel_2 IO address.
22:16 C-State Range (R/W)
The IO-port block size in which IO-redirection will be executed (0-127).
Should be programmed based on the number of LVLx registers existing
in the chipset.
63:23 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Thread
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Thread
Register Address: FEH, 254 IA32_MTRRCAP
Memory Type Range Register (R)
See Table 2-2.
Core
Register Address: 13CH, 316 MSR_FEATURE_CONFIG
AES Configuration (RW-L)
Privileged post-BIOS agent must provide a #GP handler to handle unsuccessful read of this MSR.
Core
1:0 AES Configuration (RW-L)
Upon a successful read of this MSR, the configuration of AES
instruction set availability is as follows:
11b: AES instructions are not available until next RESET.
Otherwise, AES instructions are available.
Note, the AES instruction set is not available if read is unsuccessful. If
the configuration is not 01b, AES instructions can be mis-configured if a
privileged agent unintentionally writes 11b.
63:2 Reserved.
Register Address: 140H, 320 MISC_FEATURE_ENABLES
MISC_FEATURE_ENABLES Thread
0 Reserved.
1 User Mode MONITOR and MWAIT (R/W)
If set to 1, the MONITOR and MWAIT instructions do not cause invalid-
opcode exceptions when executed with CPL > 0 or in virtual-8086
mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and
if EAX indicates a C-state other than C0 or C1, the instruction operates
as if EAX indicated the C-state C1.
63:2 Reserved.
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Thread
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-438 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Thread
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Thread
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Thread
Register Address: 17AH, 378 IA32_MCG_STATUS
See Table 2-2. Thread
Register Address: 17DH, 381 MSR_SMM_MCA_CAP
Enhanced SMM Capabilities (SMM-RO)
Reports SMM capability Enhancement. Accessible only while in SMM.
Thread
31:0 Bank Support (SMM-RO)
One bit per MCA bank. If the bit is set, that bank supports Enhanced
MCA (Default all 0; does not support EMCA).
55:32 Reserved.
56 Targeted SMI (SMM-RO)
Set if targeted SMI is supported.
57 SMM_CPU_SVRSTR (SMM-RO)
Set if SMM SRAM save/restore feature is supported.
58 SMM_CODE_ACCESS_CHK (SMM-RO)
Set if SMM code access check feature is supported.
59 Long_Flow_Indication (SMM-RO)
If set to 1, indicates that the SMM long flow indicator is supported and a
host-space interface available to SMM handler.
63:60 Reserved.
Register Address: 186H, 390 IA32_PERFEVTSEL0
Performance Monitoring Event Select Register (R/W)
See Table 2-2.
Thread
7:0 Event Select.
15:8 UMask.
16 USR.
17 OS.
18 Edge.
19 PC.
20 INT.
21 AnyThread.
22 EN.
23 INV.
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-439
MODEL-SPECIFIC REGISTERS (MSRS)
31:24 CMASK.
63:32 Reserved.
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Thread
Register Address: 198H, 408 IA32_PERF_STATUS
See Table 2-2. Package
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Thread
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
Thread
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2.
Module
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2.
Module
0 Thermal Status (R/O)
1 Thermal Status Log (R/WC0)
2 PROTCHOT # or FORCEPR# Status (R/O)
3 PROTCHOT # or FORCEPR# Log (R/WC0)
4 Critical Temperature Status (R/O)
5 Critical Temperature Status Log (R/WC0)
6 Thermal Threshold #1 Status (R/O)
7 Thermal Threshold #1 Log (R/WC0)
8 Thermal Threshold #2 Status (R/O)
9 Thermal Threshold #2 Log (R/WC0)
10 Power Limitation Status (R/O)
11 Power Limitation Log (RWC0)
15:12 Reserved.
22:16 Digital Readout (R/O)
26:23 Reserved.
30:27 Resolution in Degrees Celsius (R/O)
31 Reading Valid (R/O)
63:32 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-440 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Enable Misc. Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
Thread
0 Fast-Strings Enable
2:1 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
6:4 Reserved.
7 Performance Monitoring Available (R)
10:8 Reserved.
11 Branch Trace Storage Unavailable (R/O)
12 Processor Event Based Sampling Unavailable (R/O)
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
18 ENABLE MONITOR FSM (R/W)
21:19 Reserved.
22 Limit CPUID Maxval (R/W)
23 xTPR Message Disable (R/W)
33:24 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
37:35 Reserved.
38 Turbo Mode Disable (R/W)
63:39 Reserved.
Register Address: 1A2H, 418 MSR_TEMPERATURE_TARGET
Temperature Target Package
15:0 Reserved.
23:16 Temperature Target (R)
29:24 Target Offset (R/W)
63:30 Reserved.
Register Address: 1A4H, 420 MSR_MISC_FEATURE_CONTROL
Miscellaneous Feature Control (R/W)
0 DCU Hardware Prefetcher Disable (R/W)
If 1, disables the L1 data cache prefetcher.
Core
1 L2 Hardware Prefetcher Disable (R/W)
If 1, disables the L2 hardware prefetcher.
Core
63:2 Reserved.
Register Address: 1A6H, 422 MSR_OFFCORE_RSP_0
Offcore Response Event Select Register (R/W) Shared
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-441
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1A7H, 423 MSR_OFFCORE_RSP_1
Offcore Response Event Select Register (R/W) Shared
Register Address: 1ADH, 429 MSR_TURBO_RATIO_LIMIT
Maximum Ratio Limit of Turbo Mode for Groups of Cores (R/W) Package
0 Reserved.
7:1 Maximum Number of Cores in Group 0
Number active processor cores which operates under the maximum
ratio limit for group 0.
Package
15:8 Maximum Ratio Limit for Group 0
Maximum turbo ratio limit when the number of active cores are not
more than the group 0 maximum core count.
Package
20:16 Number of Incremental Cores Added to Group 1
Group 1, which includes the specified number of additional cores plus
the cores in group 0, operates under the group 1 turbo max ratio limit =
“group 0 Max ratio limit” - “group ratio delta for group 1”.
Package
23:21 Group Ratio Delta for Group 1
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit to Group 0.
Package
28:24 Number of Incremental Cores Added to Group 2
Group 2, which includes the specified number of additional cores plus all
the cores in group 1, operates under the group 2 turbo max ratio limit =
“group 1 Max ratio limit” - “group ratio delta for group 2”.
Package
31:29 Group Ratio Delta for Group 2
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 1.
Package
36:32 Number of Incremental Cores Added to Group 3
Group 3, which includes the specified number of additional cores plus all
the cores in group 2, operates under the group 3 turbo max ratio limit =
“group 2 Max ratio limit” - “group ratio delta for group 3”.
Package
39:37 Group Ratio Delta for Group 3
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 2.
Package
44:40 Number of Incremental Cores Added to Group 4
Group 4, which includes the specified number of additional cores plus all
the cores in group 3, operates under the group 4 turbo max ratio limit =
“group 3 Max ratio limit” - “group ratio delta for group 4”.
Package
47:45 Group Ratio Delta for Group 4
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 3.
Package
52:48 Number of Incremental Cores Added to Group 5
Group 5, which includes the specified number of additional cores plus all
the cores in group 4, operates under the group 5 turbo max ratio limit =
“group 4 Max ratio limit” - “group ratio delta for group 5”.
Package
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-442 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
55:53 Group Ratio Delta for Group 5
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 4.
Package
60:56 Number of Incremental Cores Added to Group 6
Group 6, which includes the specified number of additional cores plus all
the cores in group 5, operates under the group 6 turbo max ratio limit =
“group 5 Max ratio limit” - “group ratio delta for group 6”.
Package
63:61 Group Ratio Delta for Group 6
An unsigned integer specifying the ratio decrement relative to the Max
ratio limit for Group 5.
Package
Register Address: 1B0H, 432 IA32_ENERGY_PERF_BIAS
See Table 2-2. Thread
Register Address: 1B1H, 433 IA32_PACKAGE_THERM_STATUS
See Table 2-2. Package
Register Address: 1B2H, 434 IA32_PACKAGE_THERM_INTERRUPT
See Table 2-2. Package
Register Address: 1C8H, 456 MSR_LBR_SELECT
Last Branch Record Filtering Select Register (R/W)
See Section 18.9.2, “Filtering of Last Branch Records.”
Thread
0CPL_EQ_0
1 CPL_NEQ_0
2JCC
3 NEAR_REL_CALL
4 NEAR_IND_CALL
5 NEAR_RET
6 NEAR_IND_JMP
7 NEAR_REL_JMP
8 FAR_BRANCH
63:9 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-2) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP.
Thread
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W) Thread
0LBR
Setting this bit to 1 enables the processor to record a running trace of
the most recent branches taken by the processor in the LBR stack.
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-443
MODEL-SPECIFIC REGISTERS (MSRS)
1BTF
Setting this bit to 1 enables the processor to treat EFLAGS.TF as single-
step on branches instead of single-step on instructions.
5:2 Reserved.
6TR
Setting this bit to 1 enables branch trace messages to be sent.
7BTS
Setting this bit enables branch trace messages (BTMs) to be logged in a
BTS buffer.
8BTINT
When clear, BTMs are logged in a BTS buffer in circular fashion. When
this bit is set, an interrupt is generated by the BTS facility when the
BTS buffer is full.
9 BTS_OFF_OS
When set, BTS or BTM is skipped if CPL = 0.
10 BTS_OFF_USR
When set, BTS or BTM is skipped if CPL > 0.
11 FREEZE_LBRS_ON_PMI
When set, the LBR stack is frozen on a PMI request.
12 FREEZE_PERFMON_ON_PMI
When set, each ENABLE bit of the global counter control MSR are frozen
(address 3BFH) on a PMI request.
13 Reserved.
14 FREEZE_WHILE_SMM
When set, freezes perfmon and trace messages while in SMM.
31:15 Reserved.
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record from Linear IP (R) Thread
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record to Linear IP (R) Thread
Register Address: 1F2H, 498 IA32_SMRR_PHYSBASE
See Table 2-2. Core
Register Address: 1F3H, 499 IA32_SMRR_PHYSMASK
See Table 2-2. Core
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
See Table 2-2. Core
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
See Table 2-2. Core
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-444 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Core
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
See Table 2-2. Core
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
See Table 2-2. Core
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
See Table 2-2. Core
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
See Table 2-2. Core
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
See Table 2-2. Core
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
See Table 2-2. Core
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
See Table 2-2. Core
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
See Table 2-2. Core
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
See Table 2-2. Core
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
See Table 2-2. Core
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
See Table 2-2. Core
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
See Table 2-2. Core
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
See Table 2-2. Core
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
See Table 2-2. Core
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
See Table 2-2. Core
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
See Table 2-2. Core
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
See Table 2-2. Core
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
See Table 2-2. Core
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-445
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
See Table 2-2. Core
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
See Table 2-2. Core
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
See Table 2-2. Core
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
See Table 2-2. Core
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
See Table 2-2. Core
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
See Table 2-2. Core
Register Address: 277H, 631 IA32_PAT
See Table 2-2. Core
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2.
Core
Register Address: 309H, 777 IA32_FIXED_CTR0
Fixed-Function Performance Counter Register 0 (R/W)
See Table 2-2.
Thread
Register Address: 30AH, 778 IA32_FIXED_CTR1
Fixed-Function Performance Counter Register 1 (R/W)
See Table 2-2.
Thread
Register Address: 30BH, 779 IA32_FIXED_CTR2
Fixed-Function Performance Counter Register 2 (R/W)
See Table 2-2.
Thread
Register Address: 345H, 837 IA32_PERF_CAPABILITIES
See Table 2-2. See Section 18.4.1, “IA32_DEBUGCTL MSR.” Package
Register Address: 38DH, 909 IA32_FIXED_CTR_CTRL
Fixed-Function-Counter Control Register (R/W)
See Table 2-2.
Thread
Register Address: 38EH, 910 IA32_PERF_GLOBAL_STATUS
See Table 2-2. Thread
Register Address: 38FH, 911 IA32_PERF_GLOBAL_CTRL
See Table 2-2. Thread
Register Address: 390H, 912 IA32_PERF_GLOBAL_OVF_CTRL
See Table 2-2. Thread
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-446 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
See Table 2-2. Thread
Register Address: 3F8H, 1016 MSR_PKG_C3_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
Package
63:0 Package C3 Residency Counter (R/O)
Register Address: 3F9H, 1017 MSR_PKG_C6_RESIDENCY
63:0 Package C6 Residency Counter (R/O) Package
Register Address: 3FAH, 1018 MSR_PKG_C7_RESIDENCY
63:0 Package C7 Residency Counter (R/O) Package
Register Address: 3FCH, 1020 MSR_MC0_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
Module
63:0 Module C0 Residency Counter (R/O)
Register Address: 3FDH, 1021 MSR_MC6_RESIDENCY
63:0 Module C6 Residency Counter (R/O) Module
Register Address: 3FFH, 1023 MSR_CORE_C6_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
Core
63:0 CORE C6 Residency Counter (R/O)
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-447
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 40DH, 1037 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 40EH, 1038 IA32_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Core
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Core
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Core
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-protection
exception.
Core
Register Address: 414H, 1044 IA32_MC5_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Package
Register Address: 415H, 1045 IA32_MC5_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Package
Register Address: 416H, 1046 IA32_MC5_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.” Package
Register Address: 4C1H, 1217 IA32_A_PMC0
See Table 2-2. Thread
Register Address: 4C2H, 1218 IA32_A_PMC1
See Table 2-2. Thread
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2.
Thread
Register Address: 606H, 1542 MSR_RAPL_POWER_UNIT
Unit Multipliers Used in RAPL Interfaces (R/O) Package
3:0 Power Units
See Section 15.10.1, “RAPL Interfaces.”
Package
7:4 Reserved. Package
12:8 Energy Status Units
Energy related information (in Joules) is based on the multiplier,
1/2^ESU; where ESU is an unsigned integer represented by bits 12:8.
Default value is 0EH (or 61 micro-joules).
Package
15:13 Reserved. Package
19:16 Time Units
See Section 15.10.1, “RAPL Interfaces.”
Package
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-448 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
63:20 Reserved.
Register Address: 60DH, 1549 MSR_PKG_C2_RESIDENCY
Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state
parameters or ACPI C-states.
Package
63:0 Package C2 Residency Counter (R/O)
Register Address: 610H, 1552 MSR_PKG_POWER_LIMIT
PKG RAPL Power Limit Control (R/W)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 611H, 1553 MSR_PKG_ENERGY_STATUS
PKG Energy Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 613H, 1555 MSR_PKG_PERF_STATUS
PKG Perf Status (R/O)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 614H, 1556 MSR_PKG_POWER_INFO
PKG RAPL Parameters (R/W)
See Section 15.10.3, “Package RAPL Domain.”
Package
Register Address: 618H, 1560 MSR_DRAM_POWER_LIMIT
DRAM RAPL Power Limit Control (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 619H, 1561 MSR_DRAM_ENERGY_STATUS
DRAM Energy Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61BH, 1563 MSR_DRAM_PERF_STATUS
DRAM Performance Throttling Status (R/O)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 61CH, 1564 MSR_DRAM_POWER_INFO
DRAM RAPL Parameters (R/W)
See Section 15.10.5, “DRAM RAPL Domain.”
Package
Register Address: 638H, 1592 MSR_PP0_POWER_LIMIT
PP0 RAPL Power Limit Control (R/W)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 639H, 1593 MSR_PP0_ENERGY_STATUS
PP0 Energy Status (R/O)
See Section 15.10.4, “PP0/PP1 RAPL Domains.”
Package
Register Address: 648H, 1608 MSR_CONFIG_TDP_NOMINAL
Base TDP Ratio (R/O)
See Table 2-25.
Package
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-449
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 649H, 1609 MSR_CONFIG_TDP_LEVEL1
ConfigTDP Level 1 ratio and power level (R/O)
See Table 2-25.
Package
Register Address: 64AH, 1610 MSR_CONFIG_TDP_LEVEL2
ConfigTDP Level 2 ratio and power level (R/O)
See Table 2-25.
Package
Register Address: 64BH, 1611 MSR_CONFIG_TDP_CONTROL
ConfigTDP Control (R/W)
See Table 2-25.
Package
Register Address: 64CH, 1612 MSR_TURBO_ACTIVATION_RATIO
ConfigTDP Control (R/W)
See Table 2-25.
Package
Register Address: 690H, 1680 MSR_CORE_PERF_LIMIT_REASONS
Indicator of Frequency Clipping in Processor Cores (R/W)
(Frequency refers to processor core frequency.)
Package
0PROCHOT Status (R0)
1 Thermal Status (R0)
5:2 Reserved.
6 VR Therm Alert Status (R0)
7 Reserved.
8 Electrical Design Point Status (R0)
63:9 Reserved.
Register Address: 6E0H, 1760 IA32_TSC_DEADLINE
TSC Target of Local APIC’s TSC Deadline Mode (R/W)
See Table 2-2.
Core
Register Address: 802H, 2050 IA32_X2APIC_APICID
x2APIC ID Register (R/O) Thread
Register Address: 803H, 2051 IA32_X2APIC_VERSION
x2APIC Version Register (R/O) Thread
Register Address: 808H, 2056 IA32_X2APIC_TPR
x2APIC Task Priority Register (R/W) Thread
Register Address: 80AH, 2058 IA32_X2APIC_PPR
x2APIC Processor Priority Register (R/O) Thread
Register Address: 80BH, 2059 IA32_X2APIC_EOI
x2APIC EOI Register (W/O) Thread
Register Address: 80DH, 2061 IA32_X2APIC_LDR
x2APIC Logical Destination Register (R/O) Thread
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-450 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 80FH, 2063 IA32_X2APIC_SIVR
x2APIC Spurious Interrupt Vector Register (R/W) Thread
Register Address: 810H, 2064 IA32_X2APIC_ISR0
x2APIC In-Service Register Bits [31:0] (R/O) Thread
Register Address: 811H, 2065 IA32_X2APIC_ISR1
x2APIC In-Service Register Bits [63:32] (R/O) Thread
Register Address: 812H, 2066 IA32_X2APIC_ISR2
x2APIC In-Service Register Bits [95:64] (R/O) Thread
Register Address: 813H, 2067 IA32_X2APIC_ISR3
x2APIC In-Service Register Bits [127:96] (R/O) Thread
Register Address: 814H, 2068 IA32_X2APIC_ISR4
x2APIC In-Service Register Bits [159:128] (R/O) Thread
Register Address: 815H, 2069 IA32_X2APIC_ISR5
x2APIC In-Service Register Bits [191:160] (R/O) Thread
Register Address: 816H, 2070 IA32_X2APIC_ISR6
x2APIC In-Service Register Bits [223:192] (R/O) Thread
Register Address: 817H, 2071 IA32_X2APIC_ISR7
x2APIC In-Service Register Bits [255:224] (R/O) Thread
Register Address: 818H, 2072 IA32_X2APIC_TMR0
x2APIC Trigger Mode Register Bits [31:0] (R/O) Thread
Register Address: 819H, 2073 IA32_X2APIC_TMR1
x2APIC Trigger Mode Register Bits [63:32] (R/O) Thread
Register Address: 81AH, 2074 IA32_X2APIC_TMR2
x2APIC Trigger Mode Register Bits [95:64] (R/O) Thread
Register Address: 81BH, 2075 IA32_X2APIC_TMR3
x2APIC Trigger Mode Register Bits [127:96] (R/O) Thread
Register Address: 81CH, 2076 IA32_X2APIC_TMR4
x2APIC Trigger Mode Register Bits [159:128] (R/O) Thread
Register Address: 81DH, 2077 IA32_X2APIC_TMR5
x2APIC Trigger Mode Register Bits [191:160] (R/O) Thread
Register Address: 81EH, 2078 IA32_X2APIC_TMR6
x2APIC Trigger Mode Register Bits [223:192] (R/O) Thread
Register Address: 81FH, 2079 IA32_X2APIC_TMR7
x2APIC Trigger Mode Register Bits [255:224] (R/O) Thread
Register Address: 820H, 2080 IA32_X2APIC_IRR0
x2APIC Interrupt Request Register Bits [31:0] (R/O) Thread
Register Address: 821H, 2081 IA32_X2APIC_IRR1
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-451
MODEL-SPECIFIC REGISTERS (MSRS)
x2APIC Interrupt Request Register Bits [63:32] (R/O) Thread
Register Address: 822H, 2082 IA32_X2APIC_IRR2
x2APIC Interrupt Request Register Bits [95:64] (R/O) Thread
Register Address: 823H, 2083 IA32_X2APIC_IRR3
x2APIC Interrupt Request Register Bits [127:96] (R/O) Thread
Register Address: 824H, 2084 IA32_X2APIC_IRR4
x2APIC Interrupt Request Register Bits [159:128] (R/O) Thread
Register Address: 825H, 2085 IA32_X2APIC_IRR5
x2APIC Interrupt Request Register Bits [191:160] (R/O) Thread
Register Address: 826H, 2086 IA32_X2APIC_IRR6
x2APIC Interrupt Request Register Bits [223:192] (R/O) Thread
Register Address: 827H, 2087 IA32_X2APIC_IRR7
x2APIC Interrupt Request Register Bits [255:224] (R/O) Thread
Register Address: 828H, 2088 IA32_X2APIC_ESR
x2APIC Error Status Register (R/W) Thread
Register Address: 82FH, 2095 IA32_X2APIC_LVT_CMCI
x2APIC LVT Corrected Machine Check Interrupt Register (R/W) Thread
Register Address: 830H, 2096 IA32_X2APIC_ICR
x2APIC Interrupt Command Register (R/W) Thread
Register Address: 832H, 2098 IA32_X2APIC_LVT_TIMER
x2APIC LVT Timer Interrupt Register (R/W) Thread
Register Address: 833H, 2099 IA32_X2APIC_LVT_THERMAL
x2APIC LVT Thermal Sensor Interrupt Register (R/W) Thread
Register Address: 834H, 2100 IA32_X2APIC_LVT_PMI
x2APIC LVT Performance Monitor Register (R/W) Thread
Register Address: 835H, 2101 IA32_X2APIC_LVT_LINT0
x2APIC LVT LINT0 Register (R/W) Thread
Register Address: 836H, 2102 IA32_X2APIC_LVT_LINT1
x2APIC LVT LINT1 Register (R/W) Thread
Register Address: 837H, 2103 IA32_X2APIC_LVT_ERROR
x2APIC LVT Error Register (R/W) Thread
Register Address: 838H, 2104 IA32_X2APIC_INIT_COUNT
x2APIC Initial Count Register (R/W) Thread
Register Address: 839H, 2105 IA32_X2APIC_CUR_COUNT
x2APIC Current Count Register (R/O) Thread
Register Address: 83EH, 2110 IA32_X2APIC_DIV_CONF
x2APIC Divide Configuration Register (R/W) Thread
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-452 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-57 lists model-specific registers that are supported by the Intel
®
Xeon Phi™ processor 7215, 7285, 7295
series based on the Knights Mill microarchitecture.
Register Address: 83FH, 2111 IA32_X2APIC_SELF_IPI
x2APIC Self IPI Register (W/O) Thread
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
Thread
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
Thread
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
Thread
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
Thread
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W)
See Table 2-2.
Thread
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
Thread
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
Thread
Register Address: C000_0103H IA32_TSC_AUX
AUXILIARY TSC Signature (R/W)
See Table 2-2
Thread
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Register Address: 9BH, 155 IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W)
This MSR is readable only if VMX is enabled, and writeable only if VMX is enabled and in SMM mode, and is used to
configure the VMX MSEG base address. See Table 2-2.
Core
Register Address: 480H, 1152 IA32_VMX_BASIC
Table 2-56. Selected MSRs Supported by Intel® Xeon Phi™ Processors with a CPUID Signature
DisplayFamily_DisplayModel Value of 06_57H or 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-453
MODEL-SPECIFIC REGISTERS (MSRS)
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2.
Core
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-based VM-execution Controls (R/O)
See Table 2-2.
Core
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-based VM-execution Controls (R/O) Core
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-exit Controls (R/O)
See Table 2-2.
Core
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-entry Controls (R/O)
See Table 2-2.
Core
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Table 2-2.
Core
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Table 2-2.
Core
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Table 2-2.
Core
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Table 2-2.
Core
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Table 2-2.
Core
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Table 2-2.
Core
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Table 2-2.
Core
Register Address: 48CH, 1164 IA32_VMX_EPT_VPID_ENUM
Capability Reporting Register of EPT and VPID (R/O)
See Table 2-2.
Core
Register Address: 48DH, 1165 IA32_VMX_TRUE_PINBASED_CTLS
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
2-454 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.19 MSRS IN THE PENTIUM® 4 AND INTEL® XEON® PROCESSORS
Table 2-58 lists MSRs (architectural and model-specific) that are defined across processor generations based on
Intel NetBurst microarchitecture. The processor can be identified by its CPUID signatures of DisplayFamily
encoding of 0FH, see Table 2-1.
• MSRs with an “IA32_” prefix are designated as “architectural.” This means that the functions of these MSRs and
their addresses remain the same for succeeding families of IA-32 processors.
• MSRs with an “MSR_” prefix are model specific with respect to address functionalities. The column “Model Avail-
ability” lists the model encoding value(s) within the Pentium 4 and Intel Xeon processor family at the specified
register address. The model encoding value of a processor can be queried using CPUID. See “CPUID—CPU
Identification” in Chapter 3 of the Intel
®
64 and IA-32 Architectures Software Developer’s Manual, Volume 2A.
Capability Reporting Register of Pin-Based VM-Execution Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 48EH, 1166 IA32_VMX_TRUE_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 48FH, 1167 IA32_VMX_TRUE_EXIT_CTLS
Capability Reporting Register of VM-Exit Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 490H, 1168 IA32_VMX_TRUE_ENTRY_CTLS
Capability Reporting Register of VM-Entry Flex Controls (R/O)
See Table 2-2.
Core
Register Address: 491H, 1169 IA32_VMX_FMFUNC
Capability Reporting Register of VM-Function Controls (R/O)
See Table 2-2.
Core
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Register Address: 0H, 0 IA32_P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 1H, 1 IA32_P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 6H, 6 IA32_MONITOR_FILTER_LINE_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination.” 3, 4, 6 Shared
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
Time Stamp Counter
See Table 2-2.
0, 1, 2, 3, 4, 6 Unique
Table 2-57. Additional MSRs Supported by the Intel® Xeon Phi™ Processor 7215, 7285, 7295 Series
with a CPUID Signature DisplayFamily_DisplayModel Value of 06_85H (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description Scope
Vol. 4 2-455
MODEL-SPECIFIC REGISTERS (MSRS)
On earlier processors, only the lower 32 bits are writable. On any write to the lower 32 bits, the upper
32 bits are cleared. For processor family 0FH, models 3 and 4: all 64 bits are writable.
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
The operating system can use this MSR to determine “slot” information for the processor and the
proper microcode update to load.
0, 1, 2, 3, 4, 6 Shared
Register Address: 1BH, 27 IA32_APIC_BASE
APIC Location and Status (R/W)
See Table 2-2. See Section 11.4.4, “Local APIC Status and Location.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 2AH, 42 MSR_EBC_HARD_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features.
(R) Indicates current processor configuration.
0, 1, 2, 3, 4, 6 Shared
0Output Tri-state Enabled (R)
Indicates whether tri-state output is enabled (1) or disabled (0) as
set by the strapping of SMI#. The value in this bit is written on
the deassertion of RESET#; the bit is set to 1 when the address
bus signal is asserted.
1 Execute BIST (R)
Indicates whether the execution of the BIST is enabled (1) or
disabled (0) as set by the strapping of INIT#. The value in this bit
is written on the deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
2 In Order Queue Depth (R)
Indicates whether the in order queue depth for the system bus is
1 (1) or up to 12 (0) as set by the strapping of A7#. The value in
this bit is written on the deassertion of RESET#; the bit is set to
1 when the address bus signal is asserted.
3 MCERR# Observation Disabled (R)
Indicates whether MCERR# observation is enabled (0) or disabled
(1) as determined by the strapping of A9#. The value in this bit is
written on the deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
4 BINIT# Observation Enabled (R)
Indicates whether BINIT# observation is enabled (0) or disabled
(1) as determined by the strapping of A10#. The value in this bit
is written on the deassertion of RESET#; the bit is set to 1 when
the address bus signal is asserted.
6:5 APIC Cluster ID (R)
Contains the logical APIC cluster ID value as set by the strapping
of A12# and A11#. The logical cluster ID value is written into the
field on the deassertion of RESET#; the field is set to 1 when the
address bus signal is asserted.
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-456 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
7 Bus Park Disable (R)
Indicates whether bus park is enabled (0) or disabled (1) as set by
the strapping of A15#. The value in this bit is written on the
deassertion of RESET#; the bit is set to 1 when the address bus
signal is asserted.
11:8 Reserved.
13:12 Agent ID (R)
Contains the logical agent ID value as set by the strapping of
BR[3:0]. The logical ID value is written into the field on the
deassertion of RESET#; the field is set to 1 when the address bus
signal is asserted.
63:14 Reserved.
Register Address: 2BH, 43 MSR_EBC_SOFT_POWERON
Processor Soft Power-On Configuration (R/W)
Enables and disables processor features.
0, 1, 2, 3, 4, 6 Shared
0 RCNT/SCNT On Request Encoding Enable (R/W)
Controls the driving of RCNT/SCNT on the request encoding. Set
to enable (1); clear to disabled (0, default).
1 Data Error Checking Disable (R/W)
Set to disable system data bus parity checking; clear to enable
parity checking.
2 Response Error Checking Disable (R/W)
Set to disable (default); clear to enable.
3 Address/Request Error Checking Disable (R/W)
Set to disable (default); clear to enable.
4 Initiator MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator bus requests (default);
clear to enable.
5 Internal MCERR# Disable (R/W)
Set to disable MCERR# driving for initiator internal errors
(default); clear to enable.
6 BINIT# Driver Disable (R/W)
Set to disable BINIT# driver (default); clear to enable driver.
63:7 Reserved.
Register Address: 2CH, 44 MSR_EBC_FREQUENCY_ID
Processor Frequency Configuration
The bit field layout of this MSR varies according to the MODEL value in the CPUID version information.
The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or
greater than 2.
(R) The field Indicates the current processor frequency configuration.
2,3, 4, 6 Shared
15:0 Reserved.
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-457
MODEL-SPECIFIC REGISTERS (MSRS)
18:16 Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
EncodingScalable Bus Speed
000B 100 MHz (Model 2)
000B 266 MHz (Model 3 or 4)
001B 133 MHz
010B 200 MHz
011B 166 MHz
100B 333 MHz (Model 6)
133.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 001B.
166.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 011B.
266.67 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 000B and model encoding =
3 or 4.
333.33 MHz should be utilized if performing calculation with
System Bus Speed when encoding is 100B and model encoding =
6.
All other values are reserved.
23:19 Reserved.
31:24 Core Clock Frequency to System Bus Frequency Ratio (R)
The processor core clock frequency to system bus frequency
ratio observed at the deassertion of the reset pin.
63:32 Reserved.
Register Address: 2CH, 44 MSR_EBC_FREQUENCY_ID
Processor Frequency Configuration (R)
The bit field layout of this MSR varies according to the MODEL value of the CPUID version information.
This bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding less than 2.
Indicates current processor frequency configuration.
0, 1 Shared
20:0 Reserved.
23:21 Scalable Bus Speed (R/W)
Indicates the intended scalable bus speed:
Encoding
Scalable Bus Speed
000B 100 MHz
All others values reserved.
63:24 Reserved.
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in IA-32 Processor (R/W)
See Table 2-2.
(If CPUID.01H:ECX.[bit 5])
3, 4, 6 Unique
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-458 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
BIOS Update Trigger Register (W)
See Table 2-2.
0, 1, 2, 3, 4, 6 Shared
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
0, 1, 2, 3, 4, 6 Unique
Register Address: 9BH, 155 IA32_SMM_MONITOR_CTL
SMM Monitor Configuration (R/W)
See Table 2-2.
3, 4, 6 Unique
Register Address: FEH, 254 IA32_MTRRCAP
MTRR Information
See Section 12.11.1, “MTRR Feature Identification.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 174H, 372 IA32_SYSENTER_CS
CS Register Target for CPL 0 Code (R/W)
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and
SYSEXIT Instructions.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 175H, 373 IA32_SYSENTER_ESP
Stack Pointer for CPL 0 Stack (R/W)
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and
SYSEXIT Instructions.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 176H, 374 IA32_SYSENTER_EIP
CPL 0 Code Entry Point (R/W)
See Table 2-2 and Section 5.8.7, “Performing Fast Calls to System Procedures with the SYSENTER and
SYSEXIT Instructions.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 179H, 377 IA32_MCG_CAP
Machine Check Capabilities (R)
See Table 2-2 and Section 16.3.1.1, “IA32_MCG_CAP MSR.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 17AH, 378 IA32_MCG_STATUS
Machine Check Status (R)
See Table 2-2 and Section 16.3.1.2, “IA32_MCG_STATUS MSR.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 17BH, 379 IA32_MCG_CTL
Machine Check Feature Enable (R/W)
See Table 2-2 and Section 16.3.1.3, “IA32_MCG_CTL MSR.”
Register Address: 180H, 384 MSR_MCG_RAX
Machine Check EAX/RAX Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 181H, 385 MSR_MCG_RBX
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-459
MODEL-SPECIFIC REGISTERS (MSRS)
Machine Check EBX/RBX Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 182H, 386 MSR_MCG_RCX
Machine Check ECX/RCX Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 183H, 387 MSR_MCG_RDX
Machine Check EDX/RDX Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 184H, 388 MSR_MCG_RSI
Machine Check ESI/RSI Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 185H, 389 MSR_MCG_RDI
Machine Check EDI/RDI Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 186H, 390 MSR_MCG_RBP
Machine Check EBP/RBP Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 187H, 391 MSR_MCG_RSP
Machine Check ESP/RSP Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 188H, 392 MSR_MCG_RFLAGS
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-460 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Machine Check EFLAGS/RFLAG Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 189H, 393 MSR_MCG_RIP
Machine Check EIP/RIP Save State
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Contains register state at time of machine check error. When in
non-64-bit modes at the time of the error, bits 63-32 do not
contain valid data.
Register Address: 18AH, 394 MSR_MCG_MISC
Machine Check Miscellaneous
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
0DS
When set, the bit indicates that a page assist or page fault
occurred during DS normal operation. The processors response is
to shut down.
The bit is used as an aid for debugging DS handling code. It is the
responsibility of the user (BIOS or operating system) to clear this
bit for normal operation.
63:1 Reserved.
Register Address: 18BH−18FH,
395−399
MSR_MCG_RESERVED1−MSR_MCG_RESERVED5
Reserved.
Register Address: 190H, 400 MSR_MCG_R8
Machine Check R8
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 191H, 401 MSR_MCG_R9
Machine Check R9D/R9
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 192H, 402 MSR_MCG_R10
Machine Check R10
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-461
MODEL-SPECIFIC REGISTERS (MSRS)
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 193H, 403 MSR_MCG_R11
Machine Check R11
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 194H, 404 MSR_MCG_R12
Machine Check R12
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 195H, 405 MSR_MCG_R13
Machine Check R13
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 196H, 406 MSR_MCG_R14
Machine Check R14
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 197H, 407 MSR_MCG_R15
Machine Check R15
See Section 16.3.2.6, “IA32_MCG Extended Machine Check State MSRs.”
0, 1, 2, 3, 4, 6 Unique
63:0 Registers R8-15 (and the associated state-save MSRs) exist only
in Intel 64 processors. These registers contain valid information
only when the processor is operating in 64-bit mode at the time
of the error.
Register Address: 198H, 408 IA32_PERF_STATUS
See Table 2-2. See Section 15.1, “Enhanced Intel Speedstep® Technology.” 3, 4, 6 Unique
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. See Section 15.1, “Enhanced Intel Speedstep® Technology.” 3, 4, 6 Unique
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-462 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Thermal Monitor Control (R/W)
See Table 2-2 and Section 15.8.3, “Software Controlled Clock Modulation.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
0, 1, 2, 3, 4, 6 Unique
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
0, 1, 2, 3, 4, 6 Shared
Register Address: 19DH, 413 MSR_THERM2_CTL
Thermal Monitor 2 Control
For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last
written. When set, it sets the next target value for TM2 transition.
3Shared
For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2
transition last written. Writes may cause #GP exceptions.
4, 6 Shared
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Miscellaneous Processor Features (R/W) 0, 1, 2, 3, 4, 6 Shared
0 Fast-Strings Enable. See Table 2-2.
1 Reserved.
2 x87 FPU Fopcode Compatibility Mode Enable
3 Thermal Monitor 1 Enable
See Section 15.8.2, “Thermal Monitor,” and Table 2-2.
4Split-Lock Disable
When set, the bit causes an #AC exception to be issued instead
of a split-lock cycle. Operating systems that set this bit must align
system structures to avoid split-lock scenarios.
When the bit is clear (default), normal split-locks are issued to the
bus.
This debug feature is specific to the Pentium 4 processor.
5 Reserved.
6 Third-Level Cache Disable (R/W)
When set, the third-level cache is disabled; when clear (default)
the third-level cache is enabled. This flag is reserved for
processors that do not have a third-level cache.
Note that the bit controls only the third-level cache; and only if
overall caching is enabled through the CD flag of control register
CR0, the page-level cache controls, and/or the MTRRs.
See Section 12.5.4, “Disabling and Enabling the L3 Cache.”
7 Performance Monitoring Available (R)
See Table 2-2.
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-463
MODEL-SPECIFIC REGISTERS (MSRS)
8 Suppress Lock Enable
When set, assertion of LOCK on the bus is suppressed during a
Split Lock access. When clear (default), LOCK is not suppressed.
9 Prefetch Queue Disable
When set, disables the prefetch queue. When clear (default),
enables the prefetch queue.
10 FERR# Interrupt Reporting Enable (R/W)
When set, interrupt reporting through the FERR# pin is enabled;
when clear, this interrupt reporting function is disabled.
When this flag is set and the processor is in the stop-clock state
(STPCLK# is asserted), asserting the FERR# pin signals to the
processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
SMI#, or RESET#) is pending and that the processor should return
to normal operation to handle the interrupt.
This flag does not affect the normal operation of the FERR# pin
(to indicate an unmasked floating-point error) when the STPCLK#
pin is not asserted.
11 Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R)
See Table 2-2.
When set, the processor does not support branch trace storage
(BTS); when clear, BTS is supported.
12 PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
(R)
See Table 2-2.
When set, the processor does not support processor event-based
sampling (PEBS); when clear, PEBS is supported.
13 TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the
die temperature is at the pre-determined threshold, the Thermal
Monitor 2 mechanism is engaged. TM2 will reduce the bus to core
ratio and voltage according to the value last written to
MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change
the VID signals or the bus to core ratio when the processor
enters a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing
CPUID with EAX = 1, then this feature is not supported and BIOS
must not alter the contents of this bit location. The processor is
operating out of spec if both this bit and the TM1 bit are set to
disabled states.
3
17:14 Reserved.
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
3, 4, 6
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-464 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
19 Adjacent Cache Line Prefetch Disable (R/W)
When set to 1, the processor fetches the cache line of the 128-
byte sector containing currently required data. When set to 0, the
processor fetches both cache lines in the sector.
Single processor platforms should not set this bit. Server
platforms should set or clear this bit based on platform
performance observed in validation and testing.
BIOS may contain a setup option that controls the setting of this
bit.
21:20 Reserved.
22 Limit CPUID MAXVAL (R/W)
See Table 2-2.
Setting this can cause unexpected behavior to software that
depends on the availability of CPUID leaves greater than 3.
3, 4, 6
23 xTPR Message Disable (R/W)
See Table 2-2.
Shared
24 L1 Data Cache Context Mode (R/W)
When set, the L1 data cache is placed in shared mode; when clear
(default), the cache is placed in adaptive mode. This bit is only
enabled for IA-32 processors that support Intel Hyper-Threading
Technology. See Section 12.5.6, “L1 Data Cache Context Mode.”
When L1 is running in adaptive mode and CR3s are identical, data
in L1 is shared across logical processors. Otherwise, L1 is not
shared and cache use is competitive.
If the Context ID feature flag (ECX[10]) is set to 0 after executing
CPUID with EAX = 1, the ability to switch modes is not supported.
BIOS must not alter the contents of IA32_MISC_ENABLE[24].
33:25 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Unique
63:35 Reserved.
Register Address: 1A1H, 417 MSR_PLATFORM_BRV
Platform Feature Requirements (R) 3, 4, 6 Shared
17:0 Reserved.
18 PLATFORM Requirements
When set to 1, indicates the processor has specific platform
requirements. The details of the platform requirements are listed
in the respective data sheets of the processor.
63:19 Reserved.
Register Address: 1D7H, 471 MSR_LER_FROM_LIP
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-465
MODEL-SPECIFIC REGISTERS (MSRS)
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
See Section 18.13.3, “Last Exception Records.”
0, 1, 2, 3, 4, 6 Unique
31:0 From Linear IP
Linear address of the last branch instruction.
63:32 Reserved.
Register Address: 1D7H, 471 MSR_LER_FROM_LIP
63:0 From Linear IP
Linear address of the last branch instruction (If IA-32e mode is
active).
Unique
Register Address: 1D8H, 472 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction that the processor executed
prior to the last exception that was generated or the last interrupt that was handled.
See Section 18.13.3, “Last Exception Records.”
0, 1, 2, 3, 4, 6 Unique
31:0 From Linear IP
Linear address of the target of the last branch instruction.
63:32 Reserved.
Register Address: 1D8H, 472 MSR_LER_TO_LIP
63:0 From Linear IP
Linear address of the target of the last branch instruction (If IA-
32e mode is active).
Unique
Register Address: 1D9H, 473 MSR_DEBUGCTLA
Debug Control (R/W)
Controls how several debug features are used. Bit definitions are discussed in the referenced section.
See Section 18.13.1, “MSR_DEBUGCTLA MSR.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 1DAH, 474 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/O)
Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that
points the index of the MSR containing the most recent branch record).
See Section 18.13.2, “LBR Stack for Processors Based on Intel NetBurst® Microarchitecture,” and
addresses 1DBH-1DEH and 680H-68FH.
0, 1, 2, 3, 4, 6 Unique
Register Address: 1DBH, 475 MSR_LASTBRANCH_0
Last Branch Record 0 (R/O)
One of four last branch record registers on the last branch record stack. It contains pointers to the
source and destination instruction for one of the last four branches, exceptions, or interrupts that the
processor took.
MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH,
models 0H-02H. They have been replaced by the MSRs at 680H-68FH and 6C0H-6CFH.
See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based
on Skylake Microarchitecture.”
0, 1, 2 Unique
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-466 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 1DCH, 476 MSR_LASTBRANCH_1
Last Branch Record 1
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
0, 1, 2 Unique
Register Address: 1DDH, 477 MSR_LASTBRANCH_2
Last Branch Record 2
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
0, 1, 2 Unique
Register Address: 1DEH, 478 MSR_LASTBRANCH_3
Last Branch Record 3
See description of the MSR_LASTBRANCH_0 MSR at 1DBH.
0, 1, 2 Unique
Register Address: 200H, 512 IA32_MTRR_PHYSBASE0
Variable Range Base MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 201H, 513 IA32_MTRR_PHYSMASK0
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 202H, 514 IA32_MTRR_PHYSBASE1
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 203H, 515 IA32_MTRR_PHYSMASK1
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 204H, 516 IA32_MTRR_PHYSBASE2
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 205H, 517 IA32_MTRR_PHYSMASK2
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs”.
0, 1, 2, 3, 4, 6 Shared
Register Address: 206H, 518 IA32_MTRR_PHYSBASE3
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 207H, 519 IA32_MTRR_PHYSMASK3
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 208H, 520 IA32_MTRR_PHYSBASE4
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 209H, 521 IA32_MTRR_PHYSMASK4
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-467
MODEL-SPECIFIC REGISTERS (MSRS)
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 20AH, 522 IA32_MTRR_PHYSBASE5
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 20BH, 523 IA32_MTRR_PHYSMASK5
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 20CH, 524 IA32_MTRR_PHYSBASE6
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 20DH, 525 IA32_MTRR_PHYSMASK6
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 20EH, 526 IA32_MTRR_PHYSBASE7
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 20FH, 527 IA32_MTRR_PHYSMASK7
Variable Range Mask MTRR
See Section 12.11.2.3, “Variable Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 250H, 592 IA32_MTRR_FIX64K_00000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 258H, 600 IA32_MTRR_FIX16K_80000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 259H, 601 IA32_MTRR_FIX16K_A0000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 268H, 616 IA32_MTRR_FIX4K_C0000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 269H, 617 IA32_MTRR_FIX4K_C8000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs”.
0, 1, 2, 3, 4, 6 Shared
Register Address: 26AH, 618 IA32_MTRR_FIX4K_D0000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs”.
0, 1, 2, 3, 4, 6 Shared
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-468 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 26BH, 619 IA32_MTRR_FIX4K_D8000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 26CH, 620 IA32_MTRR_FIX4K_E0000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 26DH, 621 IA32_MTRR_FIX4K_E8000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 26EH, 622 IA32_MTRR_FIX4K_F0000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 26FH, 623 IA32_MTRR_FIX4K_F8000
Fixed Range MTRR
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 277H, 631 IA32_PAT
Page Attribute Table
See Section 12.11.2.2, “Fixed Range MTRRs.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2 and Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
0, 1, 2, 3, 4, 6 Shared
Register Address: 300H, 768 MSR_BPU_COUNTER0
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 301H, 769 MSR_BPU_COUNTER1
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 302H, 770 MSR_BPU_COUNTER2
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 303H, 771 MSR_BPU_COUNTER3
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 304H, 772 MSR_MS_COUNTER0
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 305H, 773 MSR_MS_COUNTER1
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 306H, 774 MSR_MS_COUNTER2
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 307H, 775 MSR_MS_COUNTER3
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 308H, 776 MSR_FLAME_COUNTER0
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-469
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 309H, 777 MSR_FLAME_COUNTER1
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 30AH, 778 MSR_FLAME_COUNTER2
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 30BH, 779 MSR_FLAME_COUNTER3
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 30CH, 780 MSR_IQ_COUNTER0
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 30DH, 781 MSR_IQ_COUNTER1
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 30EH, 782 MSR_IQ_COUNTER2
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 30FH, 783 MSR_IQ_COUNTER3
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 310H, 784 MSR_IQ_COUNTER4
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 311H, 785 MSR_IQ_COUNTER5
See Section 20.6.3.2, “Performance Counters.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 360H, 864 MSR_BPU_CCCR0
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 361H, 865 MSR_BPU_CCCR1
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 362H, 866 MSR_BPU_CCCR2
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 363H, 867 MSR_BPU_CCCR3
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 364H, 868 MSR_MS_CCCR0
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 365H, 869 MSR_MS_CCCR1
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 366H, 870 MSR_MS_CCCR2
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 367H, 871 MSR_MS_CCCR3
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 368H, 872 MSR_FLAME_CCCR0
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-470 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 369H, 873 MSR_FLAME_CCCR1
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 36AH, 874 MSR_FLAME_CCCR2
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 36BH, 875 MSR_FLAME_CCCR3
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 36CH, 876 MSR_IQ_CCCR0
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 36DH, 877 MSR_IQ_CCCR1
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 36EH, 878 MSR_IQ_CCCR2
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 36FH, 879 MSR_IQ_CCCR3
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 370H, 880 MSR_IQ_CCCR4
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 371H, 881 MSR_IQ_CCCR5
See Section 20.6.3.3, “CCCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A0H, 928 MSR_BSU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A1H, 929 MSR_BSU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A2H, 930 MSR_FSB_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A3H, 931 MSR_FSB_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A4H, 932 MSR_FIRM_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A5H, 933 MSR_FIRM_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A6H, 934 MSR_FLAME_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A7H, 935 MSR_FLAME_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A8H, 936 MSR_DAC_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3A9H, 937 MSR_DAC_ESCR1
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-471
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3AAH, 938 MSR_MOB_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3ABH, 939 MSR_MOB_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3ACH, 940 MSR_PMH_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3ADH, 941 MSR_PMH_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3AEH, 942 MSR_SAAT_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3AFH, 943 MSR_SAAT_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B0H, 944 MSR_U2L_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B1H, 945 MSR_U2L_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B2H, 946 MSR_BPU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B3H, 947 MSR_BPU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B4H, 948 MSR_IS_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B5H, 949 MSR_IS_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B6H, 950 MSR_ITLB_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B7H, 951 MSR_ITLB_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B8H, 952 MSR_CRU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3B9H, 953 MSR_CRU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3BAH, 954 MSR_IQ_ESCR0
See Section 20.6.3.1, “ESCR MSRs.”
This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-
02H.
0, 1, 2 Shared
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-472 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 3BBH, 955 MSR_IQ_ESCR1
See Section 20.6.3.1, “ESCR MSRs.”
This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-
02H.
0, 1, 2 Shared
Register Address: 3BCH, 956 MSR_RAT_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3BDH, 957 MSR_RAT_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3BEH, 958 MSR_SSU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C0H, 960 MSR_MS_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C1H, 961 MSR_MS_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C2H, 962 MSR_TBPU_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C3H, 963 MSR_TBPU_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C4H, 964 MSR_TC_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C5H, 965 MSR_TC_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C8H, 968 MSR_IX_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3C9H, 969 MSR_IX_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3CAH, 970 MSR_ALF_ESCR0
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3CBH, 971 MSR_ALF_ESCR1
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3CCH, 972 MSR_CRU_ESCR2
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3CDH, 973 MSR_CRU_ESCR3
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3E0H, 992 MSR_CRU_ESCR4
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3E1H, 993 MSR_CRU_ESCR5
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-473
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3F0H, 1008 MSR_TC_PRECISE_EVENT
See Section 20.6.3.1, “ESCR MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 3F1H, 1009 IA32_PEBS_ENABLE (MSR_PEBS_ENABLE)
Processor Event Based Sampling (PEBS) (R/W)
Controls the enabling of processor event sampling and replay tagging.
0, 1, 2, 3, 4, 6 Shared
12:0 See https://perfmon-events.intel.com/
.
23:13 Reserved.
24 UOP Tag
Enables replay tagging when set.
25 ENABLE_PEBS_MY_THR (R/W)
Enables PEBS for the target logical processor when set; disables
PEBS when clear (default).
See Section 20.6.4.3, “IA32_PEBS_ENABLE MSR,” for an
explanation of the target logical processor.
This bit is called ENABLE_PEBS in IA-32 processors that do not
support Intel Hyper-Threading Technology.
26 ENABLE_PEBS_OTH_THR (R/W)
Enables PEBS for the target logical processor when set; disables
PEBS when clear (default).
See Section 20.6.4.3, “IA32_PEBS_ENABLE MSR,” for an
explanation of the target logical processor.
This bit is reserved for IA-32 processors that do not support Intel
Hyper-Threading Technology.
63:27 Reserved.
Register Address: 3F2H, 1010 MSR_PEBS_MATRIX_VERT
See https://perfmon-events.intel.com/. 0, 1, 2, 3, 4, 6 Shared
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in
the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
0, 1, 2, 3, 4, 6 Shared
Register Address: 403H, 1027 IA32_MC0_MISC
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-474 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.”
The IA32_MC0_MISC MSR is either not implemented or does not contain additional information if the
MISCV flag in the IA32_MC0_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
0, 1, 2, 3, 4, 6 Shared
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in
the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
0, 1, 2, 3, 4, 6 Shared
Register Address: 407H, 1031 IA32_MC1_MISC
See Section 16.3.2.4, “IA32_MC
i_MISC MSRs.”
The IA32_MC1_MISC MSR is either not implemented or does not contain additional information if the
MISCV flag in the IA32_MC1_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
Shared
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in
the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes
to this MSR will cause a general-protection exception.
Register Address: 40BH, 1035 IA32_MC2_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the
MISCV flag in the IA32_MC2_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
Register Address: 40CH, 1036 IA32_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 40DH, 1037 IA32_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 40EH, 1038 IA32_MC3_ADDR
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-475
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in
the IA32_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
0, 1, 2, 3, 4, 6 Shared
Register Address: 40FH, 1039 IA32_MC3_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC3_MISC MSR is either not implemented or does not contain additional information if the
MISCV flag in the IA32_MC3_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
0, 1, 2, 3, 4, 6 Shared
Register Address: 410H, 1040 IA32_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 411H, 1041 IA32_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” 0, 1, 2, 3, 4, 6 Shared
Register Address: 412H, 1042 IA32_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in
the IA32_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
Register Address: 413H, 1043 IA32_MC4_MISC
See Section 16.3.2.4, “IA32_MCi_MISC MSRs.”
The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the
MISCV flag in the IA32_MC4_STATUS register is clear.
When not implemented in the processor, all reads and writes to this MSR will cause a general-
protection exception.
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2 and Appendix A.1, “Basic VMX Information.”
3, 4, 6 Unique
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Table 2-2 and Appendix A.3, “VM-Execution Controls.”
3, 4, 6 Unique
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and Table 2-2.
3, 4, 6 Unique
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-Exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls,” and Table 2-2.
3, 4, 6 Unique
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-476 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Capability Reporting Register of VM-Entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls,” and Table 2-2.
3, 4, 6 Unique
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data,” and Table 2-2.
3, 4, 6 Unique
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.
3, 4, 6 Unique
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0,” and Table 2-2.
3, 4, 6 Unique
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.
3, 4, 6 Unique
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4,” and Table 2-2.
3, 4, 6 Unique
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration,” and Table 2-2.
3, 4, 6 Unique
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls,” and Table 2-2.
3, 4, 6 Unique
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”
0, 1, 2, 3, 4, 6 Unique
Register Address: 680H, 1664 MSR_LASTBRANCH_0_FROM_IP
Last Branch Record 0 (R/W)
One of 16 pairs of last branch record registers on the last branch record stack (680H-68FH). This part
of the stack contains pointers to the source instruction for one of the last 16 branches, exceptions, or
interrupts taken by the processor.
The MSRs at 680H-68FH, 6C0H-6CfH are not available in processor releases before family 0FH, model
03H. These MSRs replace MSRs previously located at 1DBH-1DEH. which performed the same function
for early releases.
See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based
on Skylake Microarchitecture.”
3, 4, 6 Unique
Register Address: 681H, 1665 MSR_LASTBRANCH_1_FROM_IP
Last Branch Record 1
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 682H, 1666 MSR_LASTBRANCH_2_FROM_IP
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-477
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 2
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 683H, 1667 MSR_LASTBRANCH_3_FROM_IP
Last Branch Record 3
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 684H, 1668 MSR_LASTBRANCH_4_FROM_IP
Last Branch Record 4
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 685H, 1669 MSR_LASTBRANCH_5_FROM_IP
Last Branch Record 5
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 686H, 1670 MSR_LASTBRANCH_6_FROM_IP
Last Branch Record 6
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 687H, 1671 MSR_LASTBRANCH_7_FROM_IP
Last Branch Record 7
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 688H, 1672 MSR_LASTBRANCH_8_FROM_IP
Last Branch Record 8
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 689H, 1673 MSR_LASTBRANCH_9_FROM_IP
Last Branch Record 9
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 68AH, 1674 MSR_LASTBRANCH_10_FROM_IP
Last Branch Record 10
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 68BH, 1675 MSR_LASTBRANCH_11_FROM_IP
Last Branch Record 11
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 68CH, 1676 MSR_LASTBRANCH_12_FROM_IP
Last Branch Record 12
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 68DH, 1677 MSR_LASTBRANCH_13_FROM_IP
Last Branch Record 13
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 68EH, 1678 MSR_LASTBRANCH_14_FROM_IP
Last Branch Record 14
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-478 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 68FH, 1679 MSR_LASTBRANCH_15_FROM_IP
Last Branch Record 15
See description of MSR_LASTBRANCH_0 at 680H.
3, 4, 6 Unique
Register Address: 6C0H, 1728 MSR_LASTBRANCH_0_TO_IP
Last Branch Record 0 (R/W)
One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part
of the stack contains pointers to the destination instruction for one of the last 16 branches,
exceptions, or interrupts that the processor took.
See Section 18.12, “Last Branch, Call Stack, Interrupt, and Exception Recording for Processors based
on Skylake Microarchitecture.”
3, 4, 6 Unique
Register Address: 6C1H, 1729 MSR_LASTBRANCH_1_TO_IP
Last Branch Record 1
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C2H, 1730 MSR_LASTBRANCH_2_TO_IP
Last Branch Record 2
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C3H, 1731 MSR_LASTBRANCH_3_TO_IP
Last Branch Record 3
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C4H, 1732 MSR_LASTBRANCH_4_TO_IP
Last Branch Record 4
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C5H, 1733 MSR_LASTBRANCH_5_TO_IP
Last Branch Record 5
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C6H, 1734 MSR_LASTBRANCH_6_TO_IP
Last Branch Record 6
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C7H, 1735 MSR_LASTBRANCH_7_TO_IP
Last Branch Record 7
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C8H, 1736 MSR_LASTBRANCH_8_TO_IP
Last Branch Record 8
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6C9H, 1737 MSR_LASTBRANCH_9_TO_IP
Last Branch Record 9
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6CAH, 1738 MSR_LASTBRANCH_10_TO_IP
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-479
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 10
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6CBH, 1739 MSR_LASTBRANCH_11_TO_IP
Last Branch Record 11
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6CCH, 1740 MSR_LASTBRANCH_12_TO_IP
Last Branch Record 12
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6CDH, 1741 MSR_LASTBRANCH_13_TO_IP
Last Branch Record 13
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6CEH, 1742 MSR_LASTBRANCH_14_TO_IP
Last Branch Record 14
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: 6CFH, 1743 MSR_LASTBRANCH_15_TO_IP
Last Branch Record 15
See description of MSR_LASTBRANCH_0 at 6C0H.
3, 4, 6 Unique
Register Address: C000_0080H IA32_EFER
Extended Feature Enables
See Table 2-2.
3, 4, 6 Unique
Register Address: C000_0081H IA32_STAR
System Call Target Address (R/W)
See Table 2-2.
3, 4, 6 Unique
Register Address: C000_0082H IA32_LSTAR
IA-32e Mode System Call Target Address (R/W)
See Table 2-2.
3, 4, 6 Unique
Register Address: C000_0084H IA32_FMASK
System Call Flag Mask (R/W)
See Table 2-2.
3, 4, 6 Unique
Register Address: C000_0100H IA32_FS_BASE
Map of BASE Address of FS (R/W)
See Table 2-2.
3, 4, 6 Unique
Register Address: C000_0101H IA32_GS_BASE
Map of BASE Address of GS (R/W)
See Table 2-2.
3, 4, 6 Unique
Register Address: C000_0102H IA32_KERNEL_GS_BASE
Swap Target of BASE Address of GS (R/W)
See Table 2-2.
3, 4, 6 Unique
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
2-480 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.19.1 MSRs Unique to Intel
®
Xeon
®
Processor MP with L3 Cache
The MSRs listed in Table 2-59 apply to Intel
®
Xeon
®
Processor MP with up to 8MB level three cache. These proces-
sors can be detected by enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as
input) to detect the presence of the third level cache, and with CPUID reporting family encoding 0FH, model
encoding 3 or 4 (see CPUID instruction for more details).
The MSRs listed in Table 2-60 apply to Intel
®
Xeon
®
Processor 7100 series. These processors can be detected by
enumerating the deterministic cache parameter leaf of CPUID instruction (with EAX = 4 as input) to detect the
NOTES
1. For HT-enabled processors, there may be more than one logical processors per physical unit. If an MSR is Shared, this means that
one MSR is shared between logical processors. If an MSR is unique, this means that each logical processor has its own MSR.
Table 2-59. MSRs Unique to 64-bit Intel® Xeon® Processor MP with Up to an 8 MB L3 Cache
Register Address: Hex Register Name
Register Information
Model
Availability
Shared/
Unique
Register Address: 107CCH MSR_IFSB_BUSQ0
IFSB BUSQ Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte
L3 Cache.”
3, 4 Shared
Register Address: 107CDH MSR_IFSB_BUSQ1
IFSB BUSQ Event Control and Counter Register (R/W) 3, 4 Shared
Register Address: 107CEH MSR_IFSB_SNPQ0
IFSB SNPQ Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte
L3 Cache.”
3, 4 Shared
Register Address: 107CFH MSR_IFSB_SNPQ1
IFSB SNPQ Event Control and Counter Register (R/W) 3, 4 Shared
Register Address: 107D0H MSR_EFSB_DRDY0
EFSB DRDY Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte
L3 Cache.”
3, 4 Shared
Register Address: 107D1H MSR_EFSB_DRDY1
EFSB DRDY Event Control and Counter Register (R/W) 3, 4 Shared
Register Address: 107D2H MSR_IFSB_CTL6
IFSB Latency Event Control Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte
L3 Cache.”
3, 4 Shared
Register Address: 107D3H MSR_IFSB_CNTR7
IFSB Latency Event Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte
L3 Cache.”
3, 4 Shared
Table 2-58. MSRs in the Pentium® 4 and Intel® Xeon® Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Model
Availability
Shared/
Unique
1
Vol. 4 2-481
MODEL-SPECIFIC REGISTERS (MSRS)
presence of the third level cache, and with CPUID reporting family encoding 0FH, model encoding 6 (See CPUID
instruction for more details.). The performance monitoring MSRs listed in Table 2-60 are shared between logical
processors in the same core, but are replicated for each core.
2.20 MSRS IN INTEL® CORE™ SOLO AND INTEL® CORE™
DUO PROCESSORS
Model-specific registers (MSRs) for Intel Core Solo, Intel Core Duo processors, and Dual-core Intel Xeon processor
LV are listed in Table 2-61. The column “Shared/Unique” applies to Intel Core Duo processor. “Unique” means each
processor core has a separate MSR, or a bit field in an MSR governs only a core independently. “Shared” means the
MSR or the bit field in an MSR address governs the operation of both processor cores.
Table 2-60. MSRs Unique to Intel® Xeon® Processor 7100 Series
Register Address: Hex Register Name
Register Information
Model
Availability
Shared/
Unique
Register Address: 107CCH MSR_EMON_L3_CTR_CTL0
GBUSQ Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3
Cache.”
6Shared
Register Address: 107CDH MSR_EMON_L3_CTR_CTL1
GBUSQ Event Control and Counter Register (R/W) 6 Shared
Register Address: 107CEH MSR_EMON_L3_CTR_CTL2
GSNPQ Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3
Cache.”
6Shared
Register Address: 107CFH MSR_EMON_L3_CTR_CTL3
GSNPQ Event Control and Counter Register (R/W) 6 Shared
Register Address: 107D0H MSR_EMON_L3_CTR_CTL4
FSB Event Control and Counter Register (R/W)
See Section 20.6.6, “Performance Monitoring on 64-bit Intel® Xeon® Processor MP with Up to 8-MByte L3
Cache.”
6Shared
Register Address: 107D1H MSR_EMON_L3_CTR_CTL5
FSB Event Control and Counter Register (R/W) 6 Shared
Register Address: 107D2H MSR_EMON_L3_CTR_CTL6
FSB Event Control and Counter Register (R/W) 6 Shared
Register Address: 107D3H MSR_EMON_L3_CTR_CTL7
FSB Event Control and Counter Register (R/W) 6 Shared
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Register Address: 0H, 0 P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2. Unique
Register Address: 1H, 1 P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors,” and Table 2-2. Unique
2-482 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 6H, 6 IA32_MONITOR_FILTER_SIZE
See Section 9.10.5, “Monitor/Mwait Address Range Determination,” and Table 2-2. Unique
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and Table 2-2. Unique
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2. The operating system can use this MSR to determine “slot” information for the processor and the proper
microcode update to load.
Shared
Register Address: 1BH, 27 IA32_APIC_BASE
See Section 11.4.4, “Local APIC Status and Location,” and Table 2-2. Unique
Register Address: 2AH, 42 MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration (R/W)
Enables and disables processor features; (R) indicates current processor configuration.
Shared
0 Reserved.
1 Data Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processor implements R/W.
2 Response Error Checking Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processor implements R/W.
3 MCERR# Drive Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processor implements R/W.
4 Address Parity Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processor implements R/W.
6: 5 Reserved.
7 BINIT# Driver Enable (R/W)
1 = Enabled; 0 = Disabled.
Note: Not all processor implements R/W.
8Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled.
9Execute BIST (R/O)
1 = Enabled; 0 = Disabled.
10 MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
11 Reserved.
12 BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-483
MODEL-SPECIFIC REGISTERS (MSRS)
13 Reserved
14 1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes
15 Reserved.
17:16 APIC Cluster ID (R/O)
18 System Bus Frequency (R/O)
0 = 100 MHz.
1 = Reserved.
19 Reserved.
21: 20 Symmetric Arbitration ID (R/O)
26:22 Clock Frequency Ratio (R/O)
Register Address: 3AH, 58 IA32_FEATURE_CONTROL
Control Features in IA-32 Processor (R/W)
See Table 2-2.
Unique
Register Address: 40H, 64 MSR_LASTBRANCH_0
Last Branch Record 0 (R/W)
One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32
hold the ‘to’ address. See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”
Unique
Register Address: 41H, 65 MSR_LASTBRANCH_1
Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 42H, 66 MSR_LASTBRANCH_2
Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 43H, 67 MSR_LASTBRANCH_3
Last Branch Record 3 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 44H, 68 MSR_LASTBRANCH_4
Last Branch Record 4 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 45H, 69 MSR_LASTBRANCH_5
Last Branch Record 5 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 46H, 70 MSR_LASTBRANCH_6
Last Branch Record 6 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 47H, 71 MSR_LASTBRANCH_7
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-484 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 7 (R/W)
See description of MSR_LASTBRANCH_0.
Unique
Register Address: 79H, 121 IA32_BIOS_UPDT_TRIG
BIOS Update Trigger Register (W)
See Table 2-2.
Unique
Register Address: 8BH, 139 IA32_BIOS_SIGN_ID
BIOS Update Signature ID (R/W)
See Table 2-2.
Unique
Register Address: C1H, 193 IA32_PMC0
Performance Counter Register
See Table 2-2.
Unique
Register Address: C2H, 194 IA32_PMC1
Performance Counter Register
See Table 2-2.
Unique
Register Address: CDH, 205 MSR_FSB_FREQ
Scaleable Bus Speed (R/O)
This field indicates the scalable bus clock speed.
Shared
2:0 • 101B: 100 MHz (FSB 400)
• 001B: 133 MHz (FSB 533)
• 011B: 167 MHz (FSB 667)
133.33 MHz should be utilized if performing calculation with System Bus Speed
when encoding is 101B.
166.67 MHz should be utilized if performing calculation with System Bus Speed
when encoding is 001B.
63:3 Reserved.
Register Address: E7H, 231 IA32_MPERF
Maximum Performance Frequency Clock Count (R/W)
See Table 2-2.
Unique
Register Address: E8H, 232 IA32_APERF
Actual Performance Frequency Clock Count (R/W)
See Table 2-2.
Unique
Register Address: FEH, 254 IA32_MTRRCAP
See Table 2-2. Unique
Register Address: 11EH, 281 MSR_BBL_CR_CTL3
Control Register 3
Used to configure the L2 Cache.
Shared
0 L2 Hardware Enabled (R/O)
1 = If the L2 is hardware-enabled.
0 = Indicates if the L2 is hardware-disabled.
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-485
MODEL-SPECIFIC REGISTERS (MSRS)
7:1 Reserved.
8 L2 Enabled (R/W)
1 = L2 cache has been initialized.
0 = Disabled (default).
Until this bit is set the processor will not respond to the WBINVD instruction or
the assertion of the FLUSH# input.
22:9 Reserved.
23 L2 Not Present (R/O)
0 = L2 Present.
1 = L2 Not Present.
63:24 Reserved.
Register Address: 174H, 372 IA32_SYSENTER_CS
See Table 2-2. Unique
Register Address: 175H, 373 IA32_SYSENTER_ESP
See Table 2-2. Unique
Register Address: 176H, 374 IA32_SYSENTER_EIP
See Table 2-2. Unique
Register Address: 179H, 377 IA32_MCG_CAP
See Table 2-2. Unique
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status Unique
0RIPV
When set, this bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) can be
used to restart the program. If this bit is cleared, the program cannot be reliably
restarted.
1EIPV
When set, this bit indicates that the instruction addressed by the instruction
pointer pushed on the stack (when the machine check was generated) is directly
associated with the error.
2MCIP
When set, this bit indicates that a machine check has been generated. If a second
machine check is detected while this bit is still set, the processor enters a
shutdown state. Software should write this bit to 0 after processing a machine
check exception.
63:3 Reserved
Register Address: 186H, 390 IA32_PERFEVTSEL0
See Table 2-2. Unique
Register Address: 187H, 391 IA32_PERFEVTSEL1
See Table 2-2. Unique
Register Address: 198H, 408 IA32_PERF_STATUS
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-486 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2. Shared
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2. Unique
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W)
See Table 2-2.
Unique
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2 and Section 15.8.2, “Thermal Monitor.”
Unique
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2 and Section 15.8.2, “Thermal Monitor”.
Unique
Register Address: 19DH, 413 MSR_THERM2_CTL
Thermal Monitor 2 Control Unique
15:0 Reserved.
16 TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock
duty cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect.
Neither TM1 nor TM2 will be enabled.
63:16 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Miscellaneous Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
2:0 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
See Table 2-2.
Unique
6:4 Reserved.
7 Performance Monitoring Available (R)
See Table 2-2.
Shared
9:8 Reserved.
10 FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break event within
the processor
0 = Indicates compatible FERR# signaling behavior
This bit must be set to 1 to support XAPIC interrupt model usage.
Shared
11 Branch Trace Storage Unavailable (R/O)
See Table 2-2.
Shared
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-487
MODEL-SPECIFIC REGISTERS (MSRS)
12 Reserved.
13 TM2 Enable (R/W)
When this bit is set (1) and the thermal sensor indicates that the die temperature
is at the pre-determined threshold, the Thermal Monitor 2 mechanism is
engaged. TM2 will reduce the bus to core ratio and voltage according to the value
last written to MSR_THERM2_CTL bits 15:0.
When this bit is clear (0, default), the processor does not change the VID signals
or the bus to core ratio when the processor enters a thermal managed state.
If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX =
1, then this feature is not supported and BIOS must not alter the contents of this
bit location. The processor is operating out of spec if both this bit and the TM1
bit are set to disabled states.
Shared
15:14 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
1 = Enhanced Intel SpeedStep Technology enabled
Shared
18 ENABLE MONITOR FSM (R/W)
See Table 2-2.
Shared
19 Reserved.
22 Limit CPUID Maxval (R/W)
See Table 2-2.
Setting this bit may cause behavior in software that depends on the availability
of CPUID leaves greater than 2.
Shared
33:23 Reserved.
34 XD Bit Disable (R/W)
See Table 2-3.
Shared
63:35 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most recent branch record.
See MSR_LASTBRANCH_0_FROM_IP (at 40H).
Unique
Register Address: 1D9H, 473 IA32_DEBUGCTL
Debug Control (R/W)
Controls how several debug features are used. Bit definitions are discussed in Table 2-2.
Unique
Register Address: 1DDH, 477 MSR_LER_FROM_LIP
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was
generated or the last interrupt that was handled.
Unique
Register Address: 1DEH, 478 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last
exception that was generated or the last interrupt that was handled.
Unique
Register Address: 200H, 512 MTRRphysBase0
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-488 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Memory Type Range Registers Unique
Register Address: 201H, 513 MTRRphysMask0
Memory Type Range Registers Unique
Register Address: 202H, 514 MTRRphysBase1
Memory Type Range Registers Unique
Register Address: 203H, 515 MTRRphysMask1
Memory Type Range Registers Unique
Register Address: 204H, 516 MTRRphysBase2
Memory Type Range Registers Unique
Register Address: 205H, 517 MTRRphysMask2
Memory Type Range Registers Unique
Register Address: 206H, 518 MTRRphysBase3
Memory Type Range Registers Unique
Register Address: 207H, 519 MTRRphysMask3
Memory Type Range Registers Unique
Register Address: 208H, 520 MTRRphysBase4
Memory Type Range Registers Unique
Register Address: 209H, 521 MTRRphysMask4
Memory Type Range Registers Unique
Register Address: 20AH, 522 MTRRphysBase5
Memory Type Range Registers Unique
Register Address: 20BH, 523 MTRRphysMask5
Memory Type Range Registers Unique
Register Address: 20CH, 524 MTRRphysBase6
Memory Type Range Registers Unique
Register Address: 20DH, 525 MTRRphysMask6
Memory Type Range Registers Unique
Register Address: 20EH, 526 MTRRphysBase7
Memory Type Range Registers Unique
Register Address: 20FH, 527 MTRRphysMask7
Memory Type Range Registers Unique
Register Address: 250H, 592 MTRRfix64K_00000
Memory Type Range Registers Unique
Register Address: 258H, 600 MTRRfix16K_80000
Memory Type Range Registers Unique
Register Address: 259H, 601 MTRRfix16K_A0000
Memory Type Range Registers Unique
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-489
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 268H, 616 MTRRfix4K_C0000
Memory Type Range Registers Unique
Register Address: 269H, 617 MTRRfix4K_C8000
Memory Type Range Registers Unique
Register Address: 26AH, 618 MTRRfix4K_D0000
Memory Type Range Registers Unique
Register Address: 26BH, 619 MTRRfix4K_D8000
Memory Type Range Registers Unique
Register Address: 26CH, 620 MTRRfix4K_E0000
Memory Type Range Registers Unique
Register Address: 26DH, 621 MTRRfix4K_E8000
Memory Type Range Registers Unique
Register Address: 26EH, 622 MTRRfix4K_F0000
Memory Type Range Registers Unique
Register Address: 26FH, 623 MTRRfix4K_F8000
Memory Type Range Registers Unique
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
See Table 2-2 and Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
Unique
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Unique
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will
cause a general-protection exception.
Unique
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Unique
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will
cause a general-protection exception.
Unique
Register Address: 408H, 1032 IA32_MC2_CTL
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-490 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.” Unique
Register Address: 409H, 1033 IA32_MC2_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the
IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will
cause a general-protection exception.
Unique
Register Address: 40CH, 1036 MSR_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.” Unique
Register Address: 40DH, 1037 MSR_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.” Unique
Register Address: 40EH, 1038 MSR_MC4_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause
a general-protection exception.
Unique
Register Address: 410H, 1040 IA32_MC3_CTL
IA32_MC3_CTL See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.”
Register Address: 411H, 1041 IA32_MC3_STATUS
IA32_MC3_STATUS See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 412H, 1042 MSR_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the
MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause
a general-protection exception.
Unique
Register Address: 413H, 1043 MSR_MC3_MISC
Machine Check Error Reporting Register - contains additional information describing the machine-check error if the
MISCV flag in the IA32_MCi_STATUS register is set.
Unique
Register Address: 414H, 1044 MSR_MC5_CTL
Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit
(or group of hardware units).
Unique
Register Address: 415H, 1045 MSR_MC5_STATUS
Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is
set. Software is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them
causes a general-protection exception.
Unique
Register Address: 416H, 1046 MSR_MC5_ADDR
Machine Check Error Reporting Register - contains the address of the code or data memory location that produced the
machine-check error if the ADDRV flag in the IA32_MCi_STATUS register is set.
Unique
Register Address: 417H, 1047 MSR_MC5_MISC
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-491
MODEL-SPECIFIC REGISTERS (MSRS)
Machine Check Error Reporting Register - contains additional information describing the machine-check error if the
MISCV flag in the IA32_MCi_STATUS register is set.
Unique
Register Address: 480H, 1152 IA32_VMX_BASIC
Reporting Register of Basic VMX Capabilities (R/O)
See Table 2-2 and Appendix A.1, “Basic VMX Information.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 481H, 1153 IA32_VMX_PINBASED_CTLS
Capability Reporting Register of Pin-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 482H, 1154 IA32_VMX_PROCBASED_CTLS
Capability Reporting Register of Primary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 483H, 1155 IA32_VMX_EXIT_CTLS
Capability Reporting Register of VM-Exit Controls (R/O)
See Appendix A.4, “VM-Exit Controls.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 484H, 1156 IA32_VMX_ENTRY_CTLS
Capability Reporting Register of VM-Entry Controls (R/O)
See Appendix A.5, “VM-Entry Controls.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 485H, 1157 IA32_VMX_MISC
Reporting Register of Miscellaneous VMX Capabilities (R/O)
See Appendix A.6, “Miscellaneous Data.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 486H, 1158 IA32_VMX_CR0_FIXED0
Capability Reporting Register of CR0 Bits Fixed to 0 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 487H, 1159 IA32_VMX_CR0_FIXED1
Capability Reporting Register of CR0 Bits Fixed to 1 (R/O)
See Appendix A.7, “VMX-Fixed Bits in CR0.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 488H, 1160 IA32_VMX_CR4_FIXED0
Capability Reporting Register of CR4 Bits Fixed to 0 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 489H, 1161 IA32_VMX_CR4_FIXED1
Capability Reporting Register of CR4 Bits Fixed to 1 (R/O)
See Appendix A.8, “VMX-Fixed Bits in CR4.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 48AH, 1162 IA32_VMX_VMCS_ENUM
Capability Reporting Register of VMCS Field Enumeration (R/O)
See Appendix A.9, “VMCS Enumeration.” (If CPUID.01H:ECX.[bit 5])
Unique
Register Address: 48BH, 1163 IA32_VMX_PROCBASED_CTLS2
Capability Reporting Register of Secondary Processor-Based VM-Execution Controls (R/O)
See Appendix A.3, “VM-Execution Controls.” (If CPUID.01H:ECX.[bit 5] and IA32_VMX_PROCBASED_CTLS[bit 63])
Unique
Register Address: 600H, 1536 IA32_DS_AREA
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
2-492 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
2.21 MSRS IN THE PENTIUM M PROCESSOR
Model-specific registers (MSRs) for the Pentium M processor are similar to those described in Section 2.22 for P6
family processors. The following table describes new MSRs and MSRs whose behavior has changed on the Pentium
M processor.
DS Save Area (R/W)
See Table 2-2 and Section 20.6.3.4, “Debug Store (DS) Mechanism.”
Unique
31:0 DS Buffer Management Area
Linear address of the first byte of the DS buffer management area.
63:32 Reserved.
Register Address: C000_0080H IA32_EFER
See Table 2-2. Unique
10:0 Reserved.
11 Execute Disable Bit Enable
63:12 Reserved.
Table 2-62. MSRs in Pentium M Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Register Address: 0H, 0 P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.”
Register Address: 1H, 1 P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
Register Address: 10H, 16 IA32_TIME_STAMP_COUNTER
See Section 18.17, “Time-Stamp Counter,” and see Table 2-2.
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
See Table 2-2.
The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load.
Register Address: 2AH, 42 MSR_EBL_CR_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features.
(R) Indicates current processor configuration.
0Reserved.
1 Data Error Checking Enable (R)
0 = Disabled.
Always 0 on the Pentium M processor.
Table 2-61. MSRs in Intel® Core™ Solo, Intel® Core™ Duo Processors, and Dual-Core Intel® Xeon® Processor LV (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Shared/
Unique
Vol. 4 2-493
MODEL-SPECIFIC REGISTERS (MSRS)
2 Response Error Checking Enable (R)
0 = Disabled.
Always 0 on the Pentium M processor.
3 MCERR# Drive Enable (R)
0 = Disabled.
Always 0 on the Pentium M processor.
4 Address Parity Enable (R)
0 = Disabled.
Always 0 on the Pentium M processor.
6:5 Reserved.
7 BINIT# Driver Enable (R)
1 = Enabled; 0 = Disabled.
Always 0 on the Pentium M processor.
8 Output Tri-state Enabled (R/O)
1 = Enabled; 0 = Disabled.
9Execute BIST (R/O)
1 = Enabled; 0 = Disabled.
10 MCERR# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
Always 0 on the Pentium M processor.
11 Reserved.
12 BINIT# Observation Enabled (R/O)
1 = Enabled; 0 = Disabled.
Always 0 on the Pentium M processor.
13 Reserved.
14 1 MByte Power on Reset Vector (R/O)
1 = 1 MByte; 0 = 4 GBytes.
Always 0 on the Pentium M processor.
15 Reserved.
17:16 APIC Cluster ID (R/O)
Always 00B on the Pentium M processor.
18 System Bus Frequency (R/O)
0 = 100 MHz.
1 = Reserved.
Always 0 on the Pentium M processor.
19 Reserved.
21: 20 Symmetric Arbitration ID (R/O)
Always 00B on the Pentium M processor.
26:22 Clock Frequency Ratio (R/O)
Register Address: 40H, 64 MSR_LASTBRANCH_0
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-494 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Branch Record 0 (R/W)
One of 8 last branch record registers on the last branch record stack: bits 31-0 hold the ‘from’ address and bits 63-32 hold the to
address.
See also:
• Last Branch Record Stack TOS at 1C9H.
• Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”
Register Address: 41H, 65 MSR_LASTBRANCH_1
Last Branch Record 1 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 42H, 66 MSR_LASTBRANCH_2
Last Branch Record 2 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 43H, 67 MSR_LASTBRANCH_3
Last Branch Record 3 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 44H, 68 MSR_LASTBRANCH_4
Last Branch Record 4 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 45H, 69 MSR_LASTBRANCH_5
Last Branch Record 5 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 46H, 70 MSR_LASTBRANCH_6
Last Branch Record 6 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 47H, 71 MSR_LASTBRANCH_7
Last Branch Record 7 (R/W)
See description of MSR_LASTBRANCH_0.
Register Address: 119H, 281 MSR_BBL_CR_CTL
Control Register
Used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup response.
63:0 Reserved.
Register Address: 11EH, 281 MSR_BBL_CR_CTL3
Control Register 3
Used to configure the L2 Cache.
0 L2 Hardware Enabled (R/O)
1 = If the L2 is hardware-enabled.
0 = Indicates if the L2 is hardware-disabled.
4:1 Reserved.
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-495
MODEL-SPECIFIC REGISTERS (MSRS)
5 ECC Check Enable (R/O)
This bit enables ECC checking on the cache data bus. ECC is always generated on
write cycles.
0 = Disabled (default).
1 = Enabled.
For the Pentium M processor, ECC checking on the cache data bus is always enabled.
7:6 Reserved.
8L2 Enabled (R/W)
1 = L2 cache has been initialized.
0 = Disabled (default).
Until this bit is set the processor will not respond to the WBINVD instruction or the
assertion of the FLUSH# input.
22:9 Reserved.
23 L2 Not Present (R/O)
0 = L2 Present.
1 = L2 Not Present.
63:24 Reserved.
Register Address: 179H, 377 IA32_MCG_CAP
Read-only register that provides information about the machine-check architecture of the processor.
7:0 Count (R/O)
Indicates the number of hardware unit error reporting banks available in the
processor.
8 IA32_MCG_CTL Present (R/O)
1 = Indicates that the processor implements the MSR_MCG_CTL register found at
MSR 17BH.
0 = Not supported.
63:9 Reserved.
Register Address: 17AH, 378 IA32_MCG_STATUS
Global Machine Check Status
0RIPV
When set, this bit indicates that the instruction addressed by the instruction pointer
pushed on the stack (when the machine check was generated) can be used to restart
the program. If this bit is cleared, the program cannot be reliably restarted.
1EIPV
When set, this bit indicates that the instruction addressed by the instruction pointer
pushed on the stack (when the machine check was generated) is directly associated
with the error.
2MCIP
When set, this bit indicates that a machine check has been generated. If a second
machine check is detected while this bit is still set, the processor enters a shutdown
state. Software should write this bit to 0 after processing a machine check exception.
63:3 Reserved.
Register Address: 198H, 408 IA32_PERF_STATUS
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-496 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
See Table 2-2.
Register Address: 199H, 409 IA32_PERF_CTL
See Table 2-2.
Register Address: 19AH, 410 IA32_CLOCK_MODULATION
Clock Modulation (R/W).
See Table 2-2 and Section 15.8.3, “Software Controlled Clock Modulation.”
Register Address: 19BH, 411 IA32_THERM_INTERRUPT
Thermal Interrupt Control (R/W)
See Table 2-2 and Section 15.8.2, “Thermal Monitor.”
Register Address: 19CH, 412 IA32_THERM_STATUS
Thermal Monitor Status (R/W)
See Table 2-2 and Section 15.8.2, “Thermal Monitor.”
Register Address: 19DH, 413 MSR_THERM2_CTL
Thermal Monitor 2 Control
15:0 Reserved.
16 TM_SELECT (R/W)
Mode of automatic thermal monitor:
0 = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty
cycle)
1 = Thermal Monitor 2 (thermally-initiated frequency transitions)
If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect.
Neither TM1 nor TM2 will be enabled.
63:16 Reserved.
Register Address: 1A0H, 416 IA32_MISC_ENABLE
Enable Miscellaneous Processor Features (R/W)
Allows a variety of processor functions to be enabled and disabled.
2:0 Reserved.
3 Automatic Thermal Control Circuit Enable (R/W)
1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel
Thermal Monitor feature. This allows processor clocks to be automatically
modulated based on the processor's thermal sensor operation.
0 = Disabled (default).
The automatic thermal control circuit enable bit determines if the thermal control
circuit (TCC) will be activated when the processor's internal thermal sensor
determines the processor is about to exceed its maximum operating temperature.
When the TCC is activated and TM1 is enabled, the processors clocks will be forced to
a 50% duty cycle. BIOS must enable this feature.
The bit should not be confused with the on-demand thermal control circuit enable bit.
6:4 Reserved.
7 Performance Monitoring Available (R)
1 = Performance monitoring enabled.
0 = Performance monitoring disabled.
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-497
MODEL-SPECIFIC REGISTERS (MSRS)
9:8 Reserved.
10 FERR# Multiplexing Enable (R/W)
1 = FERR# asserted by the processor to indicate a pending break event within the
processor.
0 = Indicates compatible FERR# signaling behavior.
This bit must be set to 1 to support XAPIC interrupt model usage.
Branch Trace Storage Unavailable (R/O)
1 = Processor doesn’t support branch trace storage (BTS)
0 = BTS is supported
12 Processor Event Based Sampling Unavailable (R/O)
1 = Processor does not support processor event based sampling (PEBS);
0 = PEBS is supported.
The Pentium M processor does not support PEBS.
15:13 Reserved.
16 Enhanced Intel SpeedStep Technology Enable (R/W)
1 = Enhanced Intel SpeedStep Technology enabled.
On the Pentium M processor, this bit may be configured to be read-only.
22:17 Reserved.
23 xTPR Message Disable (R/W)
When set to 1, xTPR messages are disabled. xTPR messages are optional messages
that allow the processor to inform the chipset of its priority. The default is processor
specific.
63:24 Reserved.
Register Address: 1C9H, 457 MSR_LASTBRANCH_TOS
Last Branch Record Stack TOS (R/W)
Contains an index (bits 0-3) that points to the MSR containing the most recent branch record. See also:
• MSR_LASTBRANCH_0_FROM_IP (at 40H).
• Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”
Register Address: 1D9H, 473 MSR_DEBUGCTLB
Debug Control (R/W)
Controls how several debug features are used. Bit definitions are discussed in the referenced section.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors).”
Register Address: 1DDH, 477 MSR_LER_TO_LIP
Last Exception Record To Linear IP (R)
This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that
was generated or the last interrupt that was handled.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors),” and Section 18.16.2, “Last Branch and
Last Exception MSRs.”
Register Address: 1DEH, 478 MSR_LER_FROM_LIP
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-498 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Last Exception Record From Linear IP (R)
Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the
last interrupt that was handled.
See Section 18.15, “Last Branch, Interrupt, and Exception Recording (Pentium M Processors),” and Section 18.16.2, “Last Branch and
Last Exception MSRs.”
Register Address: 2FFH, 767 IA32_MTRR_DEF_TYPE
Default Memory Types (R/W)
Sets the memory type for the regions of physical memory that are not mapped by the MTRRs.
See Section 12.11.2.1, “IA32_MTRR_DEF_TYPE MSR.”
Register Address: 400H, 1024 IA32_MC0_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Register Address: 401H, 1025 IA32_MC0_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 402H, 1026 IA32_MC0_ADDR
See Section 14.3.2.3., “IA32_MCi_ADDR MSRs”.
The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register
is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Register Address: 404H, 1028 IA32_MC1_CTL
See Section 16.3.2.1, “IA32_MC
i_CTL MSRs.”
Register Address: 405H, 1029 IA32_MC1_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 406H, 1030 IA32_MC1_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register
is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Register Address: 408H, 1032 IA32_MC2_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Register Address: 409H, 1033 IA32_MC2_STATUS
See Chapter 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 40AH, 1034 IA32_MC2_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register
is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Register Address: 40CH, 1036 MSR_MC4_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Register Address: 40DH, 1037 MSR_MC4_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 40EH, 1038 MSR_MC4_ADDR
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-499
MODEL-SPECIFIC REGISTERS (MSRS)
2.22 MSRS IN THE P6 FAMILY PROCESSORS
The following MSRs are defined for the P6 family processors. The MSRs in this table that are shaded are available
only in the Pentium II and Pentium III processors. Beginning with the Pentium 4 processor, some of the MSRs in this
list have been designated as “architectural” and have had their names changed. See Table 2-2 for a list of the archi-
tectural MSRs.
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register
is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Register Address: 410H, 1040 MSR_MC3_CTL
See Section 16.3.2.1, “IA32_MCi_CTL MSRs.”
Register Address: 411H, 1041 MSR_MC3_STATUS
See Section 16.3.2.2, “IA32_MCi_STATUS MSRS.”
Register Address: 412H, 1042 MSR_MC3_ADDR
See Section 16.3.2.3, “IA32_MCi_ADDR MSRs.”
The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register
is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.
Register Address: 600H, 1536 IA32_DS_AREA
DS Save Area (R/W)
See Table 2-2.
Points to the DS buffer management area, which is used to manage the BTS and PEBS buffers. See Section 20.6.3.4, “Debug Store
(DS) Mechanism.”
31:0 DS Buffer Management Area
Linear address of the first byte of the DS buffer management area.
63:32 Reserved.
Table 2-63. MSRs in the P6 Family Processors
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Register Address: 0H, 0 P5_MC_ADDR
See Section 2.23, “MSRs in Pentium Processors.”
Register Address: 1H, 1 P5_MC_TYPE
See Section 2.23, “MSRs in Pentium Processors.”
Register Address: 10H, 16 TSC
See Section 18.17, “Time-Stamp Counter.”
Register Address: 17H, 23 IA32_PLATFORM_ID
Platform ID (R)
The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load.
49:0 Reserved.
Table 2-62. MSRs in Pentium M Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-500 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
52:50 Platform Id (R)
Contains information concerning the intended platform for the processor.
52 51 50
0 0 0 Processor Flag 0
0 0 1 Processor Flag 1
0 1 0 Processor Flag 2
0 1 1 Processor Flag 3
1 0 0 Processor Flag 4
1 0 1 Processor Flag 5
1 1 0 Processor Flag 6
1 1 1 Processor Flag 7
56:53 L2 Cache Latency Read.
59:57 Reserved.
60 Clock Frequency Ratio Read.
63:61 Reserved.
Register Address: 1BH, 27 APIC_BASE
Section 11.4.4, “Local APIC Status and Location.”
7:0 Reserved.
8 Boot Strap Processor Indicator Bit
1 = BSP
10:9 Reserved.
11 APIC Global Enable Bit - Permanent till reset
1 = Enabled.
0 = Disabled.
31:12 APIC Base Address.
63:32 Reserved.
Register Address: 2AH, 42 EBL_CR_POWERON
Processor Hard Power-On Configuration
(R/W) Enables and disables processor features, and (R) indicates current processor configuration.
0Reserved
1
1 Data Error Checking Enable (R/W)
1 = Enabled.
0 = Disabled.
2 Response Error Checking Enable FRCERR Observation Enable (R/W)
1 = Enabled.
0 = Disabled.
3AERR# Drive Enable (R/W)
1 = Enabled.
0 = Disabled.
4BERR# Enable for Initiator Bus Requests (R/W)
1 = Enabled.
0 = Disabled.
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-501
MODEL-SPECIFIC REGISTERS (MSRS)
5Reserved.
6 BERR# Driver Enable for Initiator Internal Errors (R/W)
1 = Enabled.
0 = Disabled.
7BINIT# Driver Enable (R/W)
1 = Enabled.
0 = Disabled.
8Output Tri-state Enabled (R)
1 = Enabled.
0 = Disabled.
9Execute BIST (R)
1 = Enabled.
0 = Disabled.
10 AERR# Observation Enabled (R)
1 = Enabled.
0 = Disabled.
11 Reserved.
12 BINIT# Observation Enabled (R)
1 = Enabled.
0 = Disabled.
13 In Order Queue Depth (R)
1 = 1.
0 = 8.
14 1-MByte Power on Reset Vector (R)
1 = 1MByte.
0 = 4GBytes.
15 FRC Mode Enable (R)
1 = Enabled.
0 = Disabled.
17:16 APIC Cluster ID (R)
19:18 System Bus Frequency (R)
00 = 66MHz.
10 = 100Mhz.
01 = 133MHz.
11 = Reserved.
21: 20 Symmetric Arbitration ID (R)
25:22 Clock Frequency Ratio (R)
26 Low Power Mode Enable (R/W)
27 Clock Frequency Ratio
63:28 Reserved.
1
Register Address: 33H, 51 MSR_TEST_CTRL
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-502 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Test Control Register
29:0 Reserved.
30 Streaming Buffer Disable
31 Disable LOCK#
Assertion for split locked access.
Register Address: 79H, 121 BIOS_UPDT_TRIG
BIOS Update Trigger Register.
Register Address: 88H, 136 BBL_CR_D0[63:0]
Chunk 0 data register D[63:0]: used to write to and read from the L2.
Register Address: 89H, 137 BBL_CR_D1
Chunk 1 data register D[63:0]: used to write to and read from the L2.
Register Address: 8AH, 138 BBL_CR_D2
Chunk 2 data register D[63:0]: used to write to and read from the L2.
Register Address: 8BH, 139 BIOS_SIGN/BBL_CR_D3
BIOS Update Signature Register or Chunk 3 data register D[63:0].
Used to write to and read from the L2 depending on the usage model.
Register Address: C1H, 193 PerfCtr0 (PERFCTR0)
Performance Counter Register
See Table 2-2.
Register Address: C2H, 194 PerfCtr1 (PERFCTR1)
Performance Counter Register
See Table 2-2.
Register Address: FEH, 254 MTRRcap
Memory Type Range Registers
Register Address: 116H, 278 BBL_CR_ADDR
Address register: used to send specified address (A31-A3) to L2 during cache initialization accesses.
2:0 Reserved; set to 0.
31:3 Address bits [35:3].
63:32 Reserved.
Register Address: 118H, 280 BBL_CR_DECC
Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
Register Address: 119H, 281 BBL_CR_CTL
Control register: used to program L2 commands to be issued via cache configuration accesses mechanism. Also receives L2 lookup
response.
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-503
MODEL-SPECIFIC REGISTERS (MSRS)
4:0 L2 Command:
01100 = Data Read w/ LRU update (RLU).
01110 = Tag Read w/ Data Read (TRR).
01111 = Tag Inquire (TI).
00010 = L2 Control Register Read (CR).
00011 = L2 Control Register Write (CW).
010 + MESI encode = Tag Write w/ Data Read (TWR).
111 + MESI encode = Tag Write w/ Data Write (TWW).
100 + MESI encode = Tag Write (TW).
6:5
7 State to L2
9:8 Reserved.
11:10 Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11
Way to L2
13:12 Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00
Way from L2
15:14 State from L2.
16 Reserved.
17 L2 Hit.
18 Reserved.
20:19 User supplied ECC.
21 Processor number:
2
Disable = 1.
Enable = 0.
Reserved.
63:22 Reserved.
Register Address: 11AH, 282 BBL_CR_TRIG
Trigger register: used to initiate a cache configuration accesses access, Write only with Data = 0.
Register Address: 11BH, 283 BBL_CR_BUSY
Busy register: indicates when a cache configuration accesses L2 command is in progress. D[0] = 1 = BUSY.
Register Address: 11EH, 286 BBL_CR_CTL3
Control register 3: used to configure the L2 Cache.
0 L2 Configured (read/write).
4:1 L2 Cache Latency (read/write).
5 ECC Check Enable (read/write).
6 Address Parity Check Enable (read/write).
7 CRTN Parity Check Enable (read/write).
8 L2 Enabled (read/write).
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-504 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
10:9 L2 Associativity (read only):
00 = Direct Mapped.
01 = 2 Way.
10 = 4 Way.
11 = Reserved.
12:11 Number of L2 banks (read only).
17:13 Cache size per bank (read/write):
00001 = 256 KBytes.
00010 = 512 KBytes.
00100 = 1 MByte.
01000 = 2 MBytes.
10000 = 4 MBytes.
18 Cache State error checking enable (read/write).
19 Reserved.
22:20 L2 Physical Address Range support:
111 = 64 GBytes.
110 = 32 GBytes.
101 = 16 GBytes.
100 = 8 GBytes.
011 = 4 GBytes.
010 = 2 GBytes.
001 = 1 GByte.
000 = 512 MBytes.
23 L2 Hardware Disable (read only).
24 Reserved.
25 Cache bus fraction (read only).
63:26 Reserved.
Register Address: 174H, 372 SYSENTER_CS_MSR
CS register target for CPL 0 code
Register Address: 175H, 373 SYSENTER_ESP_MSR
Stack pointer for CPL 0 stack
Register Address: 176H, 374 SYSENTER_EIP_MSR
CPL 0 code entry point
Register Address: 179H, 377 MCG_CAP
Machine Check Global Control Register
Register Address: 17AH, 378 MCG_STATUS
Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software
is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection
exception.
Register Address: 17BH, 379 MCG_CTL
Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of
hardware units).
Register Address: 186H, 390 PerfEvtSel0 (EVNTSEL0)
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-505
MODEL-SPECIFIC REGISTERS (MSRS)
Performance Event Select Register 0 (R/W)
7:0 Event Select
Refer to Performance Counter section for a list of event encodings.
15:8 UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
16 USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17 OS
Controls the counting of events at Privilege level of 0.
18 E
Occurrence/Duration Mode Select:
1 = Occurrence.
0 = Duration.
19 PC
Enabled the signaling of performance counter overflow via BP0 pin.
20 INT
Enables the signaling of counter overflow via input to APIC:
1 = Enable.
0 = Disable.
22 ENABLE
Enables the counting of performance events in both counters:
1 = Enable.
0 = Disable.
23 INV
Inverts the result of the CMASK condition:
1 = Inverted.
0 = Non-Inverted.
31:24 CMASK (Counter Mask)
Register Address: 187H, 391 PerfEvtSel1 (EVNTSEL1)
Performance Event Select for Counter 1 (R/W)
7:0 Event Select
Refer to Performance Counter section for a list of event encodings.
15:8 UMASK (Unit Mask)
Unit mask register set to 0 to enable all count options.
16 USER
Controls the counting of events at Privilege levels of 1, 2, and 3.
17 OS
Controls the counting of events at Privilege level of 0.
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-506 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
18 E
Occurrence/Duration Mode Select:
1 = Occurrence.
0 = Duration.
19 PC
Enabled the signaling of performance counter overflow via BP0 pin.
20 INT
Enables the signaling of counter overflow via input to APIC.
1 = Enable.
0 = Disable.
23 INV
Inverts the result of the CMASK condition.
1 = Inverted.
0 = Non-Inverted.
31:24 CMASK (Counter Mask)
Register Address: 1D9H, 473 DEBUGCTLMSR
Enables last branch, interrupt, and exception recording; taken branch breakpoints; the breakpoint reporting pins; and trace messages.
This register can be written to using the WRMSR instruction, when operating at privilege level 0 or when in real-address mode.
0 Enable/Disable Last Branch Records
1 Branch Trap Flag
2 Performance Monitoring/Break Point Pins
3 Performance Monitoring/Break Point Pins
4 Performance Monitoring/Break Point Pins
5 Performance Monitoring/Break Point Pins
6 Enable/Disable Execution Trace Messages
31:7 Reserved.
Register Address: 1DBH, 475 LASTBRANCHFROMIP
32-bit register for recording the instruction pointers for the last branch, interrupt, or exception that the processor took prior to a
debug exception being generated.
Register Address: 1DCH, 476 LASTBRANCHTOIP
32-bit register for recording the instruction pointers for the last branch, interrupt, or exception that the processor took prior to a
debug exception being generated.
Register Address: 1DDH, 477 LASTINTFROMIP
Last INT from IP
Register Address: 1DEH, 478 LASTINTTOIP
Last INT to IP
Register Address: 200H, 512 MTRRphysBase0
Memory Type Range Registers
Register Address: 201H, 513 MTRRphysMask0
Memory Type Range Registers
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-507
MODEL-SPECIFIC REGISTERS (MSRS)
Register Address: 202H, 514 MTRRphysBase1
Memory Type Range Registers
Register Address: 203H, 515 MTRRphysMask1
Memory Type Range Registers
Register Address: 204H, 516 MTRRphysBase2
Memory Type Range Registers
Register Address: 205H, 517 MTRRphysMask2
Memory Type Range Registers
Register Address: 206H, 518 MTRRphysBase3
Memory Type Range Registers
Register Address: 207H, 519 MTRRphysMask3
Memory Type Range Registers
Register Address: 208H, 520 MTRRphysBase4
Memory Type Range Registers
Register Address: 209H, 521 MTRRphysMask4
Memory Type Range Registers
Register Address: 20AH, 522 MTRRphysBase5
Memory Type Range Registers
Register Address: 20BH, 523 MTRRphysMask5
Memory Type Range Registers
Register Address: 20CH, 524 MTRRphysBase6
Memory Type Range Registers
Register Address: 20DH, 525 MTRRphysMask6
Memory Type Range Registers
Register Address: 20EH, 526 MTRRphysBase7
Memory Type Range Registers
Register Address: 20FH, 527 MTRRphysMask7
Memory Type Range Registers
Register Address: 250H, 592 MTRRfix64K_00000
Memory Type Range Registers
Register Address: 258H, 600 MTRRfix16K_80000
Memory Type Range Registers
Register Address: 259H, 601 MTRRfix16K_A0000
Memory Type Range Registers
Register Address: 268H, 616 MTRRfix4K_C0000
Memory Type Range Registers
Register Address: 269H, 617 MTRRfix4K_C8000
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-508 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Memory Type Range Registers
Register Address: 26AH, 618 MTRRfix4K_D0000
Memory Type Range Registers
Register Address: 26BH, 619 MTRRfix4K_D8000
Memory Type Range Registers
Register Address: 26CH, 620 MTRRfix4K_E0000
Memory Type Range Registers
Register Address: 26DH, 621 MTRRfix4K_E8000
Memory Type Range Registers
Register Address: 26EH, 622 MTRRfix4K_F0000
Memory Type Range Registers
Register Address: 26FH, 623 MTRRfix4K_F8000
Memory Type Range Registers
Register Address: 2FFH, 767 MTRRdefType
Memory Type Range Registers
2:0 Default memory type
10 Fixed MTRR enable
11 MTRR Enable
Register Address: 400H, 1024 MC0_CTL
Machine Check Error Reporting Register - controls signaling of #MC for errors produced by a particular hardware unit (or group of
hardware units).
Register Address: 401H, 1025 MC0_STATUS
Machine Check Error Reporting Register - contains information related to a machine-check error if its VAL (valid) flag is set. Software
is responsible for clearing IA32_MCi_STATUS MSRs by explicitly writing 0s to them; writing 1s to them causes a general-protection
exception.
15:0 MC_STATUS_MCACOD
31:16 MC_STATUS_MSCOD
57 MC_STATUS_DAM
58 MC_STATUS_ADDRV
59 MC_STATUS_MISCV
60 MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.)
61 MC_STATUS_UC
62 MC_STATUS_O
63 MC_STATUS_V
Register Address: 402H, 1026 MC0_ADDR
Register Address: 403H, 1027 MC0_MISC
Defined in MCA architecture but not implemented in the P6 family processors.
Register Address: 404H, 1028 MC1_CTL
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
Vol. 4 2-509
MODEL-SPECIFIC REGISTERS (MSRS)
2.23 MSRS IN PENTIUM PROCESSORS
The following MSRs are defined for the Pentium processors. The P5_MC_ADDR, P5_MC_TYPE, and TSC MSRs
(named IA32_P5_MC_ADDR, IA32_P5_MC_TYPE, and IA32_TIME_STAMP_COUNTER in the Pentium 4 processor)
are architectural; that is, code that accesses these registers will run on Pentium 4 and P6 family processors without
generating exceptions (see Section 2.1, “Architectural MSRs”). The CESR, CTR0, and CTR1 MSRs are unique to
Pentium processors; code that accesses these registers will generate exceptions on Pentium 4 and P6 family
processors.
Register Address: 405H, 1029 MC1_STATUS
Bit definitions same as MC0_STATUS.
Register Address: 406H, 1030 MC1_ADDR
Register Address: 407H, 1031 MC1_MISC
Defined in MCA architecture but not implemented in the P6 family processors.
Register Address: 408H, 1032 MC2_CTL
Register Address: 409H, 1033 MC2_STATUS
Bit definitions same as MC0_STATUS.
Register Address: 40AH, 1034 MC2_ADDR
Register Address: 40BH, 1035 MC2_MISC
Defined in MCA architecture but not implemented in the P6 family processors.
Register Address: 40CH, 1036 MC4_CTL
Register Address: 40DH, 1037 MC4_STATUS
Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.
Register Address: 40EH, 1038 MC4_ADDR
Defined in MCA architecture but not implemented in P6 Family processors.
Register Address: 40FH, 1039 MC4_MISC
Defined in MCA architecture but not implemented in the P6 family processors.
Register Address: 410H, 1040 MC3_CTL
Register Address: 411H, 1041 MC3_STATUS
Bit definitions same as MC0_STATUS.
Register Address: 412H, 1042 MC3_ADDR
Register Address: 413H, 1043 MC3_MISC
Defined in MCA architecture but not implemented in the P6 family processors.
NOTES
1. Bit 0 of this register has been redefined several times, and is no longer used in P6 family processors.
2. The processor number feature may be disabled by setting bit 21 of the BBL_CR_CTL MSR (model-specific register address 119h) to
“1”. Once set, bit 21 of the BBL_CR_CTL may not be cleared. This bit is write-once. The processor number feature will be disabled
until the processor is reset.
3. The Pentium III processor will prevent FSB frequency overclocking with a new shutdown mechanism. If the FSB frequency selected
is greater than the internal FSB frequency the processor will shutdown. If the FSB selected is less than the internal FSB frequency
the BIOS may choose to use bit 11 to implement its own shutdown policy.
Table 2-63. MSRs in the P6 Family Processors (Contd.)
Register Address: Hex, Decimal Register Name
Register Information / Bit Fields Bit Description
2-510 Vol. 4
MODEL-SPECIFIC REGISTERS (MSRS)
Table 2-64. MSRs in the Pentium Processor
Register Address: Hex, Decimal
Register Name
Register Information
Register Address: 0H, 0 P5_MC_ADDR
See Section 16.10.2, “Pentium
Processor Machine-Check Exception Handling.”
Register Address: 1H, 1 P5_MC_TYPE
See Section 16.10.2, “Pentium
Processor Machine-Check Exception Handling.”
Register Address: 10H, 16 TSC
See Section 18.17, “Time-Stamp Counter.”
Register Address: 11H, 17 CESR
See Section 20.6.9.1, “Control and Event Select Register (CESR).”
Register Address: 12H, 18 CTR0
Section 20.6.9.3, “Events Counted.”
Register Address: 13H, 19 CTR1
Section 20.6.9.3, “Events Counted.”
Vol. 4 INDEX-1
INDEX
A
Advanced programmable interrupt controller (see I/O APIC or Local
APIC)
APIC (see I/O APIC or Local APIC)
B
Backlink (see Previous task link)
Branch trace message (see BTM)
Branch trace store (see BTS)
BTS (branch trace store) facilities
BTS_UNAVAILABLE flag,
IA32_MISC_ENABLE MSR, 2-463
C
Capability MSRs
See VMX capability MSRs
Context, task (see Task state)
Current privilege level (see CPL)
D
Debug store (see DS)
DEBUGCTLMSR MSR,
2-506
Debugging facilities
see DS (debug store) mechanism
G
Global descriptor table register (see GDTR)
Global descriptor table (see GDT)
I
IA32_APIC_BASE MSR, 2-455
IA32_BIOS_SIGN_ID MSR, 2-458
IA32_BIOS_UPDT_TRIG MSR, 2-457
IA32_CLOCK_MODULATION MSR, 2-71, 2-87, 2-98, 2-154, 2-202,
2-439, 2-461, 2-462, 2-486, 2-496
IA32_CTL MSR, 2-458
IA32_DEBUGCTL MSR, 2-465
IA32_DS_AREA MSR, 2-476
IA32_MCG_CAP MSR, 2-458
IA32_MCG_MISC MSR, 2-460
IA32_MCG_R10 MSR, 2-460
IA32_MCG_R11 MSR, 2-461
IA32_MCG_R15 MSR, 2-461
IA32_MCG_RAX MSR, 2-458
IA32_MCG_RBX MSR, 2-458
IA32_MCG_RFLAGS MSR, 2-459
IA32_MCG_RIP MSR, 2-460
IA32_MCi_ADDR MSR, 2-473
IA32_MCi_CTL MSR, 2-473
IA32_MCi_MISC MSR, 2-473
IA32_MCi_STATUS MSR, 2-473
IA32_MISC_ENABLE MSR, 2-462
IA32_MTRRCAP MSR, 2-458
IA32_MTRR_PHYS BASEn MTRR, 2-466
IA32_MTRR_PHYSBASEn MTRR, 2-466
IA32_MTRR_PHYSMASKn MTRR, 2-466
IA32_P5_MC_ADDR MSR, 2-454
IA32_P5_MC_TYPE MSR, 2-454
IA32_PEBS_ENABLE MSR, 2-473
IA32_PLATFORM_ID, 2-66, 2-82, 2-149, 2-197, 2-434, 2-455, 2-482,
2-492, 2-499
IA32_STATUS MSR, 2-458
IA32_SYSENTER_CS MSR, 2-458
IA32_SYSENTER_EIP MSR, 2-458
IA32_SYSENTER_ESP MSR, 2-458
IA32_TERM_CONTROL MSR, 2-71, 2-87, 2-98, 2-154, 2-202
IA32_THERM_INTERRUPT MSR, 2-462
IA32_THERM_STATUS MSR, 2-462
IA32_TIME_STAMP_COUNTER MSR, 2-454
IA32_VMX_BASIC MSR, 2-79, 2-93, 2-103, 2-164, 2-213, 2-475,
2-491
IA32_VMX_CR0_FIXED0 MSR, 2-80, 2-93, 2-103, 2-165, 2-213,
2-476, 2-491
IA32_VMX_CR0_FIXED1 MSR, 2-80, 2-93, 2-104, 2-165, 2-213,
2-476, 2-491
IA32_VMX_CR4_FIXED0 MSR, 2-80, 2-93, 2-104, 2-165, 2-213,
2-476, 2-491
IA32_VMX_CR4_FIXED1 MSR, 2-80, 2-93, 2-104, 2-165, 2-213,
2-214, 2-476, 2-491
IA32_VMX_ENTRY_CTLS MSR, 2-79, 2-93, 2-103, 2-165, 2-213,
2-475, 2-491
IA32_VMX_EXIT_CTLS MSR, 2-79, 2-93, 2-103, 2-164, 2-213, 2-475,
2-491
IA32_VMX_MISC MSR, 2-79, 2-93, 2-103, 2-165, 2-213, 2-476, 2-491
IA32_VMX_PINBASED_CTLS MSR, 2-79, 2-93, 2-103, 2-164, 2-213,
2-475, 2-491
IA32_VMX_PROCBASED_CTLS MSR, 2-79, 2-80, 2-93, 2-103, 2-104,
2-164, 2-165, 2-213, 2-214, 2-262, 2-475, 2-491
IA32_VMX_VMCS_ENUM MSR, 2-476
Intel Core Solo and Duo processors
model-specific registers,
2-481
Interrupts
interrupt descriptor table register (see IDTR)
interrupt descriptor table (see IDT)
IPI (see interprocessor interrupt)
L
Last branch
record stack,
2-465, 2-476
Local descriptor table register (see LDTR)
Local descriptor table (see LDT)
LVT (see Local vector table)
M
Memory type range registers (see MTRRs)
Model-specific registers (see MSRs)
Modes of operation (see Operating modes)
MSRs
architectural, 2-3
list of, 2-1
P6 family processors, 2-499
Pentium 4 processor, 2-65, 2-82, 2-236, 2-260, 2-276, 2-454,
2-480
Pentium processors, 2-509, 2-510
MSR_DEBUGCTLA MSR, 2-465
INDEX
INDEX-2 Vol. 4
MSR_DEBUGCTLB MSR, 2-74, 2-89, 2-99, 2-157, 2-205, 2-262, 2-442,
2-487, 2-497
MSR_EBC_FREQUENCY_ID MSR, 2-456, 2-457
MSR_EBC_HARD_POWERON MSR, 2-455
MSR_EBC_SOFT_POWERON MSR, 2-456
MSR_LASTBRANCH _TOS, 2-465
MSR_LASTBRANCH_0_TO_IP, 2-478
MSR_LASTBRANCH_n MSR, 2-465
MSR_LASTBRANCH_n_FROM_IP MSR, 2-476
MSR_LASTBRANCH_n_TO_LIP MSR, 2-478
MSR_LER_FROM_LIP MSR, 2-464, 2-465
MSR_LER_TO_LIP MSR, 2-465
MSR_PEBS_MATRIX_VERT MSR, 2-473
MSR_PLATFORM_BRV, 2-464, 2-465, 2-466, 2-467, 2-468, 2-469,
2-470, 2-471, 2-472, 2-473, 2-474, 2-475, 2-476, 2-477,
2-478, 2-479
N
NetBurst microarchitecture (see Intel NetBurst microarchitecture)
Nonmaskable interrupt (see NMI)
P
P5_MC_ADDR MSR, 2-66, 2-82, 2-95, 2-149, 2-197, 2-433, 2-481,
2-492, 2-499, 2-510
P5_MC_TYPE MSR, 2-66, 2-82, 2-95, 2-149, 2-197, 2-434, 2-481,
2-492, 2-499, 2-510
P6 family processors
MSR supported by,
2-499
Page frame (see Page)
PDBR (see CR3 control register)
PEBS_UNAVAILABLE flag
IA32_MISC_ENABLE MSR,
2-463
Pentium 4 processor
MSRs supported,
2-65, 2-82, 2-95, 2-114, 2-116, 2-142, 2-147,
2-454, 2-480
Pentium M processor
MSRs supported by,
2-492
Pentium processor
MSR supported by,
2-509
Precise event-based sampling (see PEBS)
R
Requested privilege level (see RPL)
S
System-management mode (see SMM)
T
Translation lookaside buffer (see TLB)
U
Uncached (UC) memory type (see Strong uncached (UC) memory
type)
V
VMX
capability MSRs
IA32_VMX_BASIC MSR, 2-79, 2-93, 2-103, 2-164, 2-213, 2-475,
2-491
IA32_VMX_CR0_FIXED0 MSR
, 2-80, 2-93, 2-103, 2-165, 2-213,
2-476, 2-491
IA32_VMX_CR0_FIXED1 MSR
, 2-80, 2-93, 2-104, 2-165, 2-213,
2-476, 2-491
IA32_VMX_CR4_FIXED0 MSR
, 2-80, 2-93, 2-104, 2-165, 2-213,
2-476, 2-491
IA32_VMX_CR4_FIXED1 MSR
, 2-80, 2-93, 2-104, 2-165, 2-213,
2-214, 2-476, 2-491
IA32_VMX_ENTRY_CTLS MSR
, 2-79, 2-93, 2-103, 2-165, 2-213,
2-475, 2-491
IA32_VMX_EXIT_CTLS MSR
, 2-79, 2-93, 2-103, 2-164, 2-213,
2-475, 2-491
IA32_VMX_MISC MSR
, 2-79, 2-93, 2-103, 2-165, 2-213, 2-476,
2-491
IA32_VMX_PINBASED_CTLS MSR
, 2-79, 2-93, 2-103, 2-164,
2-213, 2-475, 2-491
IA32_VMX_PROCBASED_CTLS MSR
, 2-79, 2-80, 2-93, 2-103,
2-104, 2-164, 2-165, 2-213, 2-214, 2-262, 2-475, 2-491
IA32_VMX_VMCS_ENUM MSR
, 2-476
W
WC buffer (see Write combining (WC) buffer)
